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Chapter 4 Theory of Operation

PC-DIO-96/PnP User Manual

4-4

© National Instruments Corporation

Digital I/O Connector

All digital I/O is transmitted through a standard, 100-pin, male
connector. Pins 49 and 99 are connected to +5 V through a protection
fuse (F1). See Figure 2-1 in Chapter 2, Installation and Configuration,
for its location. This +5 V supply is often required to operate I/O
module mounting racks. Pins 50 and 100 are connected to ground. See
the Optional Equipment section in Chapter 1, Introduction, as well as
Chapter 2, Installation and Configuration, and Chapter 3, Signal
Connections, for additional information.

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Summary of Contents for PC-DIO-96/PnP

Page 1: ...PC DIO 96 PnP User Manual Digital I O Board for ISA September 1996 Edition Part Number 320289C 01 Copyright 1990 1996 National Instruments Corporation All Rights Reserved ...

Page 2: ...ralia 03 9879 5166 Austria 0662 45 79 90 0 Belgium 02 757 00 20 Canada Ontario 905 785 0085 Canada Québec 514 694 8521 Denmark 45 76 26 00 Finland 90 527 2321 France 01 48 14 24 24 Germany 089 741 31 30 Hong Kong 2645 3186 Israel 03 5734815 Italy 02 413091 Japan 03 5472 2970 Korea 02 596 7456 Mexico 95 800 010 0793 Netherlands 0348 433466 Norway 32 84 84 00 Singapore 2265886 Spain 91 640 0085 Swed...

Page 3: ...SE OF PRODUCTS OR INCIDENTAL OR CONSEQUENTIAL DAMAGES EVEN IF ADVISED OF THE POSSIBILITY THEREOF This limitation of the liability of National Instruments will apply regardless of the form of action whether in contract or tort including negligence Any action against National Instruments must be brought within one year after the cause of action accrues National Instruments shall not be liable for an...

Page 4: ... 2 Software Programming Choices 1 3 LabVIEW and LabWindows CVI Application Software 1 3 NI DAQ Driver Software 1 3 Register Level Programming 1 5 Optional Equipment 1 5 Custom Cabling 1 5 Unpacking 1 7 Chapter 2 Installation and Configuration Installation 2 1 Hardware Configuration 2 3 Plug and Play 2 3 Base I O Address and Interrupt Selection 2 3 Non Plug and Play 2 3 Chapter 3 Signal Connections...

Page 5: ...g 3 15 Mode 2 Bidirectional Timing 3 16 Chapter 4 Theory of Operation Data Transceivers 4 2 PC I O Channel Control Circuitry 4 2 Plug and Play Circuitry 4 2 Interrupt Control Circuitry 4 2 82C55A Programmable Peripheral Interface 4 3 82C53 Programmable Interval Timer 4 3 Digital I O Connector 4 4 Appendix A Specifications Appendix B OKI 82C55A Data Sheet Appendix C OKI 82C53 Data Sheet Appendix D ...

Page 6: ...nections 3 8 Figure 3 5 DIO Channel Configured for High DIO Power up State with External Load 3 10 Figure 3 6 DIO Channel Configured for Low DIO Power up State with External Load 3 11 Figure 4 1 PC DIO 96PnP Block Diagram 4 1 Figure D 1 Control Word Formats for the 82C55A D 5 Figure D 2 Control Word Format for the 82C53 D 7 Figure D 3 Port C Pin Assignments Mode 1 Input D 16 Figure D 4 Port C Pin ...

Page 7: ...ignal Descriptions 3 13 Table D 1 PC DIO 96 PnP Address Map D 2 Table D 2 Port C Set Reset Control Words D 6 Table D 3 Mode 0 I O Configurations D 12 Table E 1 Comparison of Characteristics E 1 Table E 2 PC DIO 96 Factory Set Switch and Jumper Settings E 4 Table E 3 Switch Settings with Corresponding Base I O Address and Base I O Address Space E 7 ...

Page 8: ...6 Non PnP Board Organization of This Manual The PC DIO 96 PnP User Manual is organized as follows Chapter 1 Introduction describes the PC DIO 96 PnP lists what you need to get started describes software programming choices optional equipment and custom cables and explains how to unpack the PC DIO 96 PnP Chapter 2 Installation and Configuration describes how to install and configure the PC DIO 96Pn...

Page 9: ...ter Appendix F Customer Communication contains forms you can use to request help from National Instruments or to comment on our products The Glossary contains an alphabetical list and description of terms used in this manual including abbreviations acronyms metric prefixes mnemonics and symbols The Index alphabetically lists the topics in this manual including the page where you can find each one ...

Page 10: ...d Play refers to a device that is fully compatible with the industry standard Plug and Play ISA Specification All bus related configuration is performed through software freeing the user from manually configuring jumpers or switches to set the product s base address and interrupt level Plug and Play systems automatically arbitrate and assign system resources to a PnP product non PnP Non PnP non Pl...

Page 11: ...about the DAQ hardware that plugs into or is connected to your computer Use these manuals for hardware installation and configuration instructions specification information about your DAQ hardware and application hints Software documentation Examples of software documentation you may have are the LabVIEW LabWindows CVI and NI DAQ documentation sets After you set up your hardware system use either ...

Page 12: ... reference manual Plug and Play ISA Specification Customer Communication National Instruments wants to receive your comments on our products and manuals We are interested in the applications you develop with our products and we want to help if you have problems with them To make it easy for you to contact us this manual contains comment and configuration forms for you to complete These forms are i...

Page 13: ...tal I O The 82C55A can operate in either a unidirectional or bidirectional mode and can generate interrupt requests to the host computer You can program the 82C55A for almost any 8 bit or 16 bit digital I O application All digital I O communication is through a standard 100 pin male connector The PC DIO 96 PnP also includes an 82C53 counter timer that can send periodic interrupts to the host syste...

Page 14: ...ailable from National Instruments If you need to drive an SSR OAC 5 or SSR OAC 5A you can either use a non inverting digital buffer chip between the PC DIO 96 PnP and the SSR backplane or you can use a DIO 23F or MIO Series board with appropriate connections for example SC 205X and cables With the PC DIO 96 PnP a PC can serve as a digital I O system controller for laboratory testing production tes...

Page 15: ...ith National Instruments DAQ hardware is included with LabVIEW The LabVIEW Data Acquisition VI Library is functionally equivalent to the NI DAQ software LabWindows CVI features interactive graphics a state of the art user interface and uses the ANSI standard C programming language The LabWindows CVI Data Acquisition Library a series of functions for using LabWindows CVI with National Instruments D...

Page 16: ...ltiple devices operate at their peak performance NI DAQ also internally addresses many of the complex issues between the computer and the DAQ hardware such as programming interrupts and DMA controllers NI DAQ maintains a consistent software interface among its different versions so that you can change platforms with minimal modifications to your code Whether you are using conventional programming ...

Page 17: ...terminals SCXI modules and accessories for isolating amplifying exciting and multiplexing signals for relays and analog output With SCXI you can condition and acquire up to 3 072 channels Low channel count signal conditioning modules boards and accessories including conditioning for strain gauges and RTDs simultaneous sample and hold and relays For more specific information about these products re...

Page 18: ...f custom cables The PC DIO 96 PnP I O connector is a 100 pin Centronics style male ribbon cable header connector The manufacturer and the appropriate part number for this connector is as follows Robinson Nugent part number P50E 100P1 RR1 TG The mating connector for the PC DIO 96 PnP is a 100 position polarized Centronics style female ribbon socket connector with strain relief National Instruments ...

Page 19: ...ge to prevent electrostatic damage to the board Electrostatic discharge can damage several components on the board To avoid such damage in handling the board take the following precautions Ground yourself via a grounding strap or by holding a grounded object Touch the antistatic package to a metal part of your computer chassis before removing the board from the package Remove the board from the pa...

Page 20: ...chapter describes how to install and configure the PC DIO 96PnP board Installation Note You should install your driver software before installing your hardware Refer to your NI DAQ release notes for software installation instructions Figure 2 1 PC DIO 96PnP Parts Locator Diagram 1 Serial Number 2 W1 3 F1 3 2 1 ...

Page 21: ...ansion slot in your computer The following are general installation instructions but consult your computer user manual or technical reference manual for specific instructions and warnings 1 Turn off and unplug your computer 2 Remove the top cover or access port to the I O channel 3 Remove the expansion slot cover on the back panel of the computer 4 Insert the PC DIO 96PnP board into any 8 bit or 1...

Page 22: ...d and assigns the available resources as efficiently as possible to the Plug and Play boards Application software can query the Configuration Manager to determine the resources assigned to each board without your involvement The Plug and Play software is installed as a device driver or as an integral component of the computer BIOS Base I O Address and Interrupt Selection To change base I O address...

Page 23: ...s that exceed any of the maximum ratings of input or output signals on the PC DIO 96 PnP can damage the board and the computer The description of each signal in this section includes information about maximum input ratings National Instruments is NOT liable for any damages resulting from any such signal connections I O Connector Pin Description Figure 3 1 shows the pin assignments for the PC DIO 9...

Page 24: ... 13 63 12 62 11 61 10 60 9 59 8 58 7 57 6 56 5 55 4 54 3 53 2 52 1 51 GND GND 5 V 5 V BPA0 DPA0 APA0 CPA0 BPA1 DPA1 APA1 CPA1 BPA2 DPA2 APA2 CPA2 BPA3 DPA3 APA3 CPA3 BPA4 DPA4 APA4 CPA4 BPA5 DPA5 APA5 CPA5 BPA6 DPA6 APA6 CPA6 BPA7 DPA7 APA7 CPA7 BPB0 DPB0 APB0 CPB0 BPB1 DPB1 APB1 CPB1 BPB2 DPB2 APB2 CPB2 BPB3 DPB3 APB3 CPB3 BPB4 DPB4 APB4 CPB4 BPB5 DPB5 APB5 CPB5 BPB6 DPB6 APB6 CPB6 BPB7 DPB7 APB7...

Page 25: ...es for Port A of PPI B BPA7 is the MSB BPA0 the LSB 51 53 55 57 59 61 63 65 CPC 7 0 Bidirectional Data Lines for Port C of PPI C CPC7 is the MSB CPC0 the LSB 67 69 71 73 75 77 79 81 CPB 7 0 Bidirectional Data Lines for Port B of PPI C CPB7 is the MSB CPB0 the LSB 83 85 87 89 91 93 95 97 CPA 7 0 Bidirectional Data Lines for Port A of PPI C CPA7 is the MSB CPA0 the LSB 52 54 56 58 60 62 64 66 DPC 7 ...

Page 26: ...Equipment in Chapter 1 Introduction is an assembly of two 50 pin cables and three connectors Both cables are joined to a single connector on one end and to individual connectors on the free ends The 100 pin connector that joins the two cables plugs into the I O connector of the PC DIO 96 PnP The other two connectors are 50 pin connectors one of which is connected to pins 1 through 50 and the other...

Page 27: ...nector 5 V APA0 APA1 APA2 APA3 APA4 APA5 APA6 APA7 APB0 APB1 APB2 APB3 APB4 APB5 APB6 APB7 APC0 APC1 APC2 APC3 APC4 APC5 APC6 APC7 GND BPA1 BPA2 BPA4 BPA5 BPA6 BPA7 BPA0 BPA3 BPB0 BPB1 BPB2 BPB3 BPB4 BPB5 BPB6 BPB7 BPC0 BPC1 BPC2 BPC3 BPC4 BPC5 BPC6 BPC7 49 50 47 48 45 46 43 44 41 42 39 40 37 38 35 36 33 34 31 32 29 30 27 28 25 26 23 24 21 22 19 20 17 18 15 16 13 14 11 12 9 10 7 8 5 6 3 4 1 2 ...

Page 28: ...nnector 5 V CPA0 CPA1 CPA2 CPA3 CPA4 CPA5 CPA6 CPA7 CPB0 CPB1 CPB2 CPB3 CPB4 CPB5 CPB6 CPB7 CPC0 CPC1 CPC2 CPC3 CPC4 CPC5 CPC6 CPC7 GND DPA1 DPA2 DPA4 DPA5 DPA6 DPA7 DPA0 DPA3 DPB0 DPB1 DPB2 DPB3 DPB4 DPB5 DPB6 DPB7 DPC0 DPC1 DPC2 DPC3 DPC4 DPC5 DPC6 DPC7 49 50 47 48 45 46 43 44 41 42 39 40 37 38 35 36 33 34 31 32 29 30 27 28 25 26 23 24 21 22 19 20 17 18 15 16 13 14 11 12 9 10 7 8 5 6 3 4 1 2 ...

Page 29: ...h respect to GND Digital input specifications referenced to GND Input logic high voltage 2 2 V min 5 3 V max Input logic low voltage 0 3 V min 0 8 V max Maximum input current 0 Vin 5 V 1 0 µA min 1 0 µA max Digital output specifications referenced to GND Output logic high voltage 3 7 V min 5 0 V max at Iout 2 5 mA Output logic low voltage 0 0 V min 0 4 V max at Iout 2 5 mA Output current 2 5 mA mi...

Page 30: ...als and sensing external device states such as the state of the switch in Figure 3 4 Digital output applications include sending TTL signals and driving external devices such as the LED shown in Figure 3 4 Complex switch circuitry is not shown in order to simplify the figure PC DIO 96 PnP Switch I O Connector 5 V 5 V LED TTL Signal 41 43 45 47 67 71 73 69 50 100 5 V Jumper Selectable W1 100 kΩ 100...

Page 31: ...p the PC DIO 96 PnP s digital I O lines in a user defined state The PC DIO 96 PnP facilitates user configurable pull up or pull down Each DIO channel is connected to a 100 kΩ resistor and can be pulled high or low using jumper W1 You can use W1 to pull all 96 DIO lines high or low However if all lines are high you may want to pull some lines low To do this properly you must understand the nature o...

Page 32: ...alculate the largest possible load to maintain a logic low level of 0 4 V and supply the maximum driving current I V I RL RL V I where V 0 4 V Voltage across RL I 46 µA 10 µA 4 6 V across the 100 kΩ pull up resistor and 10 µA from 82C55 leakage current Therefore RL 7 1 kΩ 0 4 V 56 µA This resistor value 7 1 kΩ provides a maximum of 0 4 V on the DIO line at power up You can substitute smaller resis...

Page 33: ...ble of sinking a maximum of 2 5 mA at 0 4 V in the low state Use the largest possible resistance value so that you do not to use more current than necessary to perform the pull up task Also make sure the pull up resistor value is not so large that leakage current from the DIO line along with the current from the 100 kΩ pull down resistor brings the voltage at the resistor below a TTL high level of...

Page 34: ... 2 2 V voltage across RL I 28 µA 10 µA 2 8 V across the 100 kΩ pull up resistor and 10 µA from 82C55 leakage current Therefore RL 5 7 kΩ 2 2 V 38 µA This resistor value 5 7 kΩ provides a minimum of 2 8 V on the DIO line at power up You can substitute smaller resistor values but they will draw more current leaving less sink current for other circuitry connected to this line The 5 7 kΩ resistor will...

Page 35: ...from the PC DIO 96 PnP OBF Output Output Buffer Full A low signal on this handshaking line indicates that data has been written to the port INTR Output Interrupt Request This signal becomes high when the 82C55A requests service during a data transfer The appropriate interrupt enable bits must be set to generate this signal RD Internal Read Signal This signal is the read signal generated from the c...

Page 36: ...lustrates the timing specifications for an input transfer in mode 1 Name Description Minimum Maximum T1 STB pulse width 100 T2 STB 0 to IBF 1 150 T3 Data before STB 1 20 T4 STB 1 to INTR 1 150 T5 Data after STB 1 50 T6 RD 0 to INTR 0 200 T7 RD 1 to IBF 0 150 All timing values are in nanoseconds T3 T5 T6 T7 T4 T1 T2 STB IBF INTR RD DATA ...

Page 37: ...wing figure illustrates the timing specifications for an output transfer in mode 1 Name Description Minimum Maximum T1 WR 0 to INTR 0 250 T2 WR 1 to output 200 T3 WR 1 to OBF 0 150 T4 ACK 0 to OBF 1 150 T5 ACK pulse width 100 T6 ACK 1 to INTR 1 150 All timing values are in nanoseconds T2 T3 WR OBF INTR DATA T4 T6 T5 ACK T1 ...

Page 38: ...ional transfers in mode 2 Name Description Minimum Maximum T1 WR 1 to OBF 0 150 T2 Data before STB 1 20 T3 STB pulse width 100 T4 STB 0 to IBF 1 150 T5 Data after STB 1 50 T6 ACK 0 to OBF 1 150 T7 ACK pulse width 100 T8 ACK 0 to output 150 T9 ACK 1 to output float 20 250 T10 RD 1 to IBF 0 150 All timing values are in nanoseconds T2 T1 WR OBF INTR ACK DATA T6 T7 T3 T4 T10 STB T9 T8 T5 IBF RD ...

Page 39: ...e 4 1 illustrates the key functional components of the PC DIO 96PnP board Figure 4 1 PC DIO 96PnP Block Diagram 8 8 8 16 6 5 VDC 8 8 8 8 8 8 8 8 8 8 8 8 Data Transceivers PC I O Channel Control Circuitry Interrupt Control Circuitry Plug and Play Port A Port B Port C Digital I O Connector PC I O Channel 82C55A PPI 82C55A PPI 82C55A PPI 82C55A PPI 82C53 Timer 1 A Fuse Port A Port A Port A Port B Por...

Page 40: ...ls identify transfers as read or write memory or I O and 8 bit 16 bit or 32 bit transfers The PC DIO 96PnP uses only 8 bit transfers Plug and Play Circuitry The board s Plug and Play circuitry automatically arbitrates and assigns system resources All bus related configuration such as setting the board s base address and interrupt level is performed through software Interrupt Control Circuitry The ...

Page 41: ...nP Each of these chips has 24 programmable I O pins that represent three 8 bit ports PA PB and PC Each port can be programmed as an input or an output port The 82C55A has three modes of operation simple I O mode 0 strobed I O mode 1 and bidirectional I O mode 2 In modes 1 and 2 the three ports are divided into two groups group A and group B Each group has eight data bits and four control and statu...

Page 42: ...e connected to 5 V through a protection fuse F1 See Figure 2 1 in Chapter 2 Installation and Configuration for its location This 5 V supply is often required to operate I O module mounting racks Pins 50 and 100 are connected to ground See the Optional Equipment section in Chapter 1 Introduction as well as Chapter 2 Installation and Configuration and Chapter 3 Signal Connections for additional info...

Page 43: ...O Compatibility TTL Absolute max voltage rating 0 5 to 5 5 V with respect to GND Handshaking Requires 1 port Power on state Configured as inputs high jumper selectable Data transfers Interrupts programmed I O Digital logic levels Level Min Max Input low voltage Input high voltage Input low current Vin 0 8 V Input high current Vin 2 4 V 0 3 V 2 2 V 0 8 V 5 3 V 1 0 µA 1 0 µA Output low voltage Iout ...

Page 44: ...as shown previously If your external circuitry requires 0 5 to 1 A of current connect pins 49 and 99 in parallel to distribute the current Transfer rates Up to 780 kbytes s Note The upper limit on maximum transfer rates is constrained primarily by the software and operating system rather than hardware interface for non DMA boards such as the PC DIO 96 PnP The maximum transfer rate listed here was ...

Page 45: ...the manufacturer data sheet for the OKI 82C55A OKI Semiconductor CMOS programmable peripheral interface This interface is used on the PC DIO 96 PnP board Copyright OKI Semiconductor 1993 Reprinted with permission of copyright owner All rights reserved OKI Semiconductor Data Book Microprocessor Seventh Edition March 1993 ...

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Page 62: ...x contains the manufacturer data sheet for the OKI 82C53 integrated circuit OKI Semiconductor This circuit is used on the PC DIO 96 PnP board Copyright OKI Semiconductor 1995 Reprinted with permission of copyright owner All rights reserved OKI Semiconductor Data Book Microprocessor Eighth Edition January 1995 ...

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Page 74: ... is software configured and does not require you to manually change any settings on the board For more information on configuring the PC DIO 96PnP see Chapter 2 Installation and Configuration The three 8 bit ports of the 82C55A are divided into two groups of 12 signals each group A and group B One 8 bit control word selects the mode of operation for each group The group A control bits configure po...

Page 75: ... interrupts Also a master enable signal determines whether the board can actually send a request to the host computer The configuration bits for these registers are defined in the Register Description for the Interrupt Control Registers section later in this appendix Register Map The following table lists the address map for the PC DIO 96 PnP Table D 1 PC DIO 96 PnP Address Map Register Name Offse...

Page 76: ...bit Read and write PORTB Register 0D 8 bit Read and write PORTC Register 0E 8 bit Read and write CNFG Register 0F 8 bit Write only 82C53 Register Group PORTA Register 10 8 bit Read and write PORTB Register 11 8 bit Read and write PORTC Register 12 8 bit Read and write CNFG Register 13 8 bit Write only Interrupt Control Register Group Register 1 14 8 bit Write only Register 2 15 8 bit Write only Ta...

Page 77: ...ollow Register Description for the 82C55A Figure D 1 shows the two control word formats used to completely program the 82C55A The control word flag determines which control word format is being programmed When the control word flag is 1 bits 6 through 0 select the I O characteristics of the 82C55A ports These bits also select the mode in which the ports are operating that is mode 0 mode 1 or mode ...

Page 78: ...put port B is undefined D2 D1 D0 D5 D4 D3 D7 D6 high nibble 1 input 0 output Control Word Flag 1 mode set 00 mode 0 01 mode 1 1X mode 2 Mode Selection 1 input 0 output Port A Port C low nibble 1 input 0 output Port C 0 mode 0 1 mode 1 Mode Selection Group A Group B Port B 1 input 0 output Flag D2 D1 D0 D3 D7 0 bit set reset 1 set 0 reset 000 001 010 111 Control Word Bit Select Bit Set Reset a Mode...

Page 79: ...trol word select the counter to be programmed Bits 5 and 4 select the mode by which the count data is written to and read from the selected counter Bits 3 2 and 1 select the mode for the selected counter Bit 0 selects whether the counter counts in binary or BCD format Table D 2 Port C Set Reset Control Words Bit Number Bit Set Control Word Bit Reset Control Word The Bit Set or Reset in Port C 0 0x...

Page 80: ... other register has a master interrupt enable bit and two bits for the timed interrupt circuitry Of the latter two bits one bit enables counter interrupts while the other selects counter 0 or counter 1 The bit maps and signal definitions are listed as follows BCD D2 D1 D0 D3 D7 D6 D5 D4 1 count in BCD 0 count in binary Mode Select 000 mode 0 001 mode 1 010 mode 2 011 mode 3 100 mode 4 101 mode 5 1...

Page 81: ...RQ1 PPI C Interrupt Request for Port B If this bit and the INTEN bit in Interrupt Control Register 2 are both set PPI C sends an interrupt INTRB to the host computer If this bit is cleared PPI C does not send the interrupt INTRB to the host computer regardless of the setting of INTEN 4 CIRQ0 PPI C Interrupt Request for Port A If this bit and the INTEN bit in Interrupt Control Register 2 are both s...

Page 82: ...f the setting of INTEN 1 AIRQ1 PPI A Interrupt Request for Port B If this bit and the INTEN bit in Interrupt Control Register 2 are both set PPI A sends an interrupt INTRB to the host computer If this bit is cleared PPI A does not send the interrupt INTRB to the host computer regardless of the setting of INTEN 0 AIRQ0 PPI A Interrupt Request for Port A If this bit and the INTEN bit in Interrupt Co...

Page 83: ...TRIRQ Counter Interrupt Enable Bit If this bit is set the 82C53 counter outputs can interrupt the host computer If this bit is cleared the counter outputs have no effect 0 CTR1 Counter 1 Enable Bit If this bit is set the output from counter 1 of the 82C53 is connected to the interrupt request circuitry In this mode counter 0 of the 82C53 acts as a frequency scaler for counter 1 which generates the...

Page 84: ...to or read from a specified port Mode 0 has the following features Two 8 bit ports A and B and two 4 bit ports upper and lower nibbles of port C Any port can be input or output Outputs are latched but inputs are not latched Mode 1 This mode transfers data that is synchronized by handshaking signals Ports A and B use the eight lines of port C to generate or receive the handshake signals This mode d...

Page 85: ...trol signals for port A and port B when these ports are operating in mode 1 or mode 2 Mode 0 Basic I O Mode 0 can be used for simple I O functions no handshaking for each of the three ports Each port can be assigned as an input or an output port The 16 possible I O configurations are shown in Table D 3 Notice that bit 7 of the control word is set when programming the mode of operation for each por...

Page 86: ... PPI A port C define ACNFGoffset 0x03 Offset for PPI A CNFG unsigned int porta portb portc cnfg char valread Variable to store data read from a port Calculate register addresses porta BASE_ADDRESS APORTAoffset portb BASE_ADDRESS APORTBoffset portc BASE_ADDRESS APORTCoffset cnfg BASE_ADDRESS ACNFGoffset 9 10010001 Input Output Output Input 10 10010010 Input Output Input Output 11 10010011 Input Out...

Page 87: ...s A and C are outputs port B is an input EXAMPLE 4 outp cnfg 0x89 Ports A and B are outputs port C is an input Mode 1 Strobed Input In mode 1 the digital I O bits are divided into two groups group A and group B Each of these groups contains one 8 bit port and one 4 bit control data port The 8 bit port can be either an input or an output port and the 4 bit port is used for control and status inform...

Page 88: ...utput These bits can be used for general purpose I O when port A is in mode 1 input If these bits are configured for output the port C bit set reset function must be used to manipulate them 5 IBFA Input Buffer for Port A A high setting indicates that data has been loaded into the input latch for port A 4 INTEA Interrupt Enable Bit for Port A Setting this bit enables interrupts from port A of the 8...

Page 89: ...rt C has the following pin assignments when in mode 1 input Notice that the status of STBA and the status of STBB are not included in the port C status word Figure D 3 Port C Pin Assignments Mode 1 Input Mode 1 Input Programming Example The following example shows how to configure PPI A for various combinations of mode 1 input This code is strictly an example and is not intended to be used without...

Page 90: ...d in port A valread inp porta Read the data from port A EXAMPLE 2 Port B input outp cnfg 0x86 Port B is an input in mode 1 while inp portc 0x02 Wait until IBFB is set indicating that data has been loaded in port B valread inp portb Mode 1 Strobed Output The control word written to the CNFG Register to configure port A for output in mode 1 is shown as follows Bits PC4 and PC5 of port C can be used ...

Page 91: ... Input Output These bits can be used for general purpose I O when port A is in mode 1 output If these bits are configured for output the port C bit set reset function must be used to manipulate them 3 INTRA Interrupt Request Status for Port A When INTEA and OBFA are high this bit is high indicating that an interrupt request is pending for port A 2 INTEB Interrupt Enable Bit for Port B Setting this...

Page 92: ...ictly an example and is not intended to be used without modification in a practical situation Main define BASE_ADDRESS 0x180 Board located at address 180 define APORTAoffset 0x00 Offset for PPI A port A define APORTBoffset 0x01 Offset for PPI A port B define APORTCoffset 0x02 Offset for PPI A port C define ACNFGoffset 0x03 Offset for PPI A CNFG unsigned int porta portb portc cnfg char valread Vari...

Page 93: ...mode 1 while inp portc 0x80 Wait until OBFA is set indicating that the data last written to port A has been read outp porta 0x12 Write data to port A EXAMPLE 2 port B output outp cnfg 0x84 Port B is an output in mode 1 while inp portc 0x02 Wait until OBFB is set indicating that the data last written to port B has been read outp portb 0x34 Write the data to port B ...

Page 94: ...rol word written to the CNFG Register to configure port A as a bidirectional data bus in mode 2 is shown as follows If port B is configured for mode 0 then PC2 PC1 and PC0 of port C can be used as extra input or output lines Figure D 5 Port A Configured as a Bidirectional Data Bus in Mode 2 During a mode 2 data transfer the status of the handshaking lines and interrupt signals can be obtained by r...

Page 95: ...put latch of port A 4 INTE2 Interrupt Enable Bit for Port A Input Interrupts Setting this bit enables input interrupts from port A of the 82C55A This bit is controlled by setting resetting PC4 3 INTRA Interrupt Request Status for Port A If INTE1 and IBFA are high then this bit is high indicating that an interrupt request is pending for port A input transfers If INTE2 and OBFA are high then this bi...

Page 96: ...tion in a practical situation Main define BASE_ADDRESS 0x180 Board located at address 180 define APORTAoffset 0x00 Offset for PPI A port A define APORTBoffset 0x01 Offset for PPI A port B define APORTCoffset 0x02 Offset for PPI A port C define ACNFGoffset 0x03 Offset for PPI A CNFG unsigned int porta portb portc cnfg char valread Variable to store data read from a port The three port C lines assoc...

Page 97: ...e routines for the 82C53 are included later in the appendix These routines can be modified to function for the 82C55A Consult your computer s technical reference manual for additional information Also if you generate interrupts with the PC3 or PC0 lines of the 82C55A devices you must maintain the active high level until the interrupt service routine is entered Otherwise the host computer considers...

Page 98: ...m 82C55A outp ireg1 0x01 Set AIRQ0 to enable PPI A port A interrupts outp ireg2 0x04 Set INTEN bit EXAMPLE 2 Set up interrupts for mode 1 input for port B Enable the appropriate interrupt bits outp cnfg 0x86 Port B is an input in mode 1 outp cnfg 0x05 Set PC2 to enable interrupts from 82C55A outp ireg1 0x02 Set AIRQ1 to enable PPI A port B interrupts outp ireg2 0x04 Set INTEN bit EXAMPLE 3 Set up ...

Page 99: ...General Information The 82C53 contains three counter timers each of which can operate in one of six different modes As the PC DIO 96 PnP is designed however only counter 0 and counter 1 are configured for operation counter 2 is not connected nor is it available on the external I O connector In addition counter 0 and counter 1 are wired to the interrupt circuitry in such a way that only four of the...

Page 100: ...ctr1 define ctr0_data 10000 Pulse every 5 msec define ctr1_data 1000 Pulse every 5 sec unsigned int ctr0 ctr1 cnfg ireg1 ireg2 Calculate register addresses ctr0 BASE_ADDRESS CTR0offset ctr1 BASE_ADDRESS CTR1offset cnfg BASE_ADDRESS CTRCNFGoffset ireg1 BASE_ADDRESS IREG1offset ireg2 BASE_ADDRESS IREG2offset Disable interrupts outp ireg1 0x00 Disable all 82C55A interrupts outp ireg2 0x00 Disable cou...

Page 101: ...nterrupts as shown below if use_ctr1 outp cnfg 0x70 Turn off counter 1 outp cnfg 0x30 Turn off counter 0 outp ireg2 0x00 Disable PC DIO 96 PnP interrupts After you have deactivated interrupts you must remove your interrupt service routine before exiting your program do this now remove_isr Sample code for the functions install_isr and remove_isr is presented as follows Be sure to pass a 32 bit stru...

Page 102: ..._isr int level isr_block_type far isr_block on input level indicates the interrupt level that is to be modified on input isr_block points to the data structure that will be used by the isr_handler function void isr_handler void the isr_handler function will never be called from C void remove_isr void public _install_isr _isr_handler _remove_isr _DATA segment word public DATA declarations ackm equ ...

Page 103: ...x push cx push dx push ds push es mov ax seg _DATA mov ds ax save the pointer for the isr_block structure used in isr_handler mov ax bp 8 Get ofs into ax mov word ptr isrb_addr 0 ax Save address in variable mov ax bp 10 Get seg into ax mov word ptr isrb_addr 2 ax Save address in variable set interrupt vector save the current vector before writing out new one mov ax bp 6 Get interrupt level cmp al ...

Page 104: ... word ptr int_addr 2 es push ds Save the data segment mov ds cx Copy cx cs into ds mov dx offset _isr_handler ds dx points to new handler mov ah 25h int 21h Install the handler in the system pop ds mask interrupt level in the interrupt controller register and store the original setting of the mask bit for the selected interrupt level mov cx bp 6 Get interrupt level mov bx 1 Generate some masks shl...

Page 105: ...level out masks al mov int_mask cx Save the previous value of the mask restore saved registers ii_exit pop es pop ds pop dx pop cx pop bx pop ax pop bp sti ret _install_isr endp remove_isr bp reg at bp 0 ret addr ofs at bp 2 ret addr seg at bp 4 _remove_isr proc far cli push ax push bx push cx push dx push ds push es mov ax seg _DATA mov ds ax ...

Page 106: ...there jne short ri_exit Different vector segment exit cmp bx offset _isr_handler jne short ri_exit Different vector offset exit restore old mask and vector values mov cx int_mask Get the old mask value in al maskm Get current master mask jmp 2 Delay wait for data transfer or al cl OR in old mask value out maskm al Send out new setting jmp 2 Delay wait for data transfer in al masks Get current slav...

Page 107: ...ndler _isr_handler proc far cli push ax push ds service interrupt Your code here if this was not your interrupt jump to ih_0 if this was your interrupt service it as appropriate the pointer for the data structure isr_block is stored at _DATA isrb_addr to access the structure use the following steps mov ax seg _DATA mov ds ax lds si isrb_addr you need not use ds si but be sure to save any registers...

Page 108: ...t must first be cleared to disable unwanted interrupts After all sources of interrupts have been disabled or placed in an inactive state you can set INTEN To interrupt the host computer using one of the 82C55A devices program the selected 82C55A for the I O mode desired In mode 1 set either the INTEA or the INTEB bit to enable interrupts from port A or port B respectively In mode 2 set either INTE...

Page 109: ...t B is in mode 0 use PC0 to generate an interrupt Once you have configured the selected 82C55A you must set the corresponding interrupt enable bit in Interrupt Register 1 If you are using PC3 set xIRQ0 if you are using PC0 set xIRQ1 When the external signal becomes logic high an interrupt request occurs Although the host computer s interrupt monitoring circuitry is triggered by the positive going ...

Page 110: ...th a backwards compatible revised PC DIO 96 that has the same functionality as the Plug and Play version except for the base address and interrupt selection but differs somewhat from the original board The following list compares the specifications and functionality of the newer boards with the obsolete legacy board Table E 1 Comparison of Characteristics Functional Changes Legacy PC DIO 96 Revise...

Page 111: ...ontains one jumper and one DIP switch to configure the PC bus interface settings The DIP switch U16 sets the base I O address Jumper W2 selects the interrupt level The DIP switch and jumper are shown in the parts locator diagram in Figure E 2 PC I O Channel I O Connector PC I O Channel Control 21 Interrupt Control Circuitry 6 Data Transceiver 8 82C55A PPI 82C55A PPI 82C53 Timer 82C55A PPI 82C55A P...

Page 112: ...pendix E Using Your PC DIO 96 Non PnP Board National Instruments Corporation E 3 PC DIO 96 PnP User Manual Figure E 2 PC DIO 96 Parts Locator Diagram 1 W2 2 U16 3 Serial Number 4 W1 5 J1 6 F1 1 6 2 4 3 5 ...

Page 113: ...6 PnP Hardware and Software Configuration Form in Appendix F Customer Communication Base I O Address Selection An onboard switch setting determines the board base address The address on the PC I O channel bus is monitored by the address decoder which is part of the I O channel control circuitry If the address on the bus matches the selected I O base address of the board the board is enabled and th...

Page 114: ...ess for the PC DIO 96 or for the other device Each switch in U16 corresponds to one of the address lines A9 through A5 Thus the range for possible base I O address settings is hex 000 through 3E0 Base I O address values hex 000 through 0FF are reserved for system use Base I O values hex 100 through 3FF are available on the I O channel A4 A3 A2 A1 and A0 are used by the PC DIO 96 to decode accesses...

Page 115: ...ation Figure E 3 Example Base I O Address Switch Settings Table E 3 shows all possible switch settings and their corresponding address ranges Switches Set to Default Setting Base I O Address Hex 180 Switches Set to Base I O Address Hex 2A0 U16 OFF 5 4 3 2 1 A9 A8 A7 A6 A5 U16 OFF 5 4 3 2 1 A9 A8 A7 A6 A5 ...

Page 116: ...20 020 03F 0 0 0 1 0 040 040 05F 0 0 0 1 1 060 060 07F 0 0 1 0 0 080 080 09F 0 0 1 0 1 0A0 0A0 0BF 0 0 1 1 0 0C0 0C0 0DF 0 0 1 1 1 0E0 0E0 0FF 0 1 0 0 0 100 100 11F 0 1 0 0 1 120 120 13F 0 1 0 1 0 140 140 15F 0 1 0 1 1 160 160 17F 0 1 1 0 0 180 180 19F 0 1 1 0 1 1A0 1A0 1BF 0 1 1 1 0 1C0 1C0 1DF 0 1 1 1 1 1E0 1E0 1FF 1 0 0 0 0 200 200 21F 1 0 0 0 1 220 220 23F 1 0 0 1 0 240 240 25F 1 0 0 1 1 260 2...

Page 117: ...fault interrupt line is IRQ5 To change to another line remove the jumper from IRQ5 and place it on the pins for another request line Figure E 4 shows the default factory setting for IRQ5 1 1 0 0 1 320 320 33F 1 1 0 1 0 340 340 35F 1 1 0 1 1 360 360 37F 1 1 1 0 0 380 380 39F 1 1 1 0 1 3A0 3A0 3BF 1 1 1 1 0 3C0 3C0 3DF 1 1 1 1 1 3E0 3E0 3FF Note Base I O address values 000 through 0FF hex are reserv...

Page 118: ... verify the switch and jumper settings record them using the PC DIO 96 PnP Hardware and Software Configuration Form in Appendix F Customer Communication You are now ready to install the PC DIO 96 The following are general installation instructions but consult your computer s user manual or technical reference manual for specific instructions and warnings If you want to install this board in an EIS...

Page 119: ...ing a configurable software package such as NI DAQ you may need to reconfigure your software to reflect any changes in jumper or switch settings If you have an EISA class computer you need to update the computer s resource allocation or configuration table by reconfiguring your computer See your computer s user manual for information about updating the configuration table The PC DIO 96 board is no...

Page 120: ...not answer your questions we offer fax and telephone support through our technical support centers which are staffed by applications engineers Electronic Services National Instruments has BBS and FTP sites dedicated for 24 hour support with a collection of files and documents to answer most common customer questions From these sites you can also download the latest instrument drivers updates and e...

Page 121: ...technical support number for your country If there is no National Instruments office in your country contact the source from which you purchased your software to obtain support Telephone Fax Australia 03 9879 5166 03 9879 6277 Austria 0662 45 79 90 0 0662 45 79 90 19 Belgium 02 757 00 20 02 757 03 11 Canada Ontario 905 785 0085 905 785 0086 Canada Quebec 514 694 8521 514 694 4399 Denmark 45 76 26 ...

Page 122: ...________________________________________________ _______________________________________________________________________________ National Instruments hardware product model________________ Revision__________________ Configuration ___________________________________________________________________ National Instruments software product__________________________ Version_______________ Configuration _...

Page 123: ...____________________________________ DMA channels of other boards __________________________________________________ Interrupt level of other boards ___________________________________________________ Other Products Computer make and model ______________________________________________________ Microprocessor _______________________________________________________________ Clock frequency or speed _...

Page 124: ...________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________...

Page 125: ...ort A AIRQ1 PPI A interrupt request bit for Port B APA bidirectional data lines for Port A of PPI A APB bidirectional data lines for Port B of PPI A APC bidirectional data lines for Port B of PPI A BCD binary coded decimal BIRQ0 PPI B interrupt request bit for Port A BIRQ1 PPI B interrupt request bit for Port B Prefix Meaning Value n nano 10 9 µ micro 10 6 m milli 10 3 k kilo 103 M mega 106 ...

Page 126: ...ctional data lines for Port B of PPI C CPC bidirectional data lines for Port C of PPI C CTR1 counter 1 enable bit CTRIRQ counter interrupt enable bit DATA data lines at the specified port signal DIO digital input output DIRQ0 PPI D interrupt request bit for Port A DIRQ1 PPI D interrupt request bit for Port B DMA direct memory access DPA bidirectional data lines for Port A of PPI D DPB bidirectiona...

Page 127: ... bit INTR interrupt request signal INTRA interrupt request status bit for Port A INTRB interrupt request status bit for Port B I O input output or input output bit Iout output current ISA Industry Standard Architecture kbytes 1 024 bytes LSB least significant bit m meters MB megabytes of memory MSB most significant bit OBF output buffer full signal OBFA output buffer bit for Port A OBFB output buf...

Page 128: ... Real Time System Integration s seconds SCXI Signal Conditioning eXtensions for Instrumentation STB strobe input signal TTL transistor to transistor logic V volts VDC volts direct current VEXT external volt Vin volts in VOH volts output high VOL volts output low WR write signal ...

Page 129: ...programming example D 13 to D 14 purpose and use D 11 mode 1 operation D 11 mode 1 strobed input D 14 to D 17 control words written to CNFG Register figure D 15 Port C pin assignments figure D 16 Port C status word bit definitions for input D 15 to D 16 programming example D 16 to D 17 mode 1 strobed output D 17 to D 20 control word written to CNFG Register figure D 17 to D 18 Port C pin assignmen...

Page 130: ...5 INTEA D 15 D 18 D 35 INTEB D 16 D 18 D 35 INTEN D 10 D 35 INTRA D 15 D 18 D 22 INTRB D 16 D 18 I O D 15 D 18 D 22 OBFA D 18 D 22 OBFB D 18 block diagram PC DIO 96 E 2 PC DIO 96 PnP 4 1 board configuration See configuration BPA 7 0 signal table 3 3 BPB 7 0 signal table 3 3 BPC 7 0 signal table 3 3 bulletin board support F 1 C cable assembly connectors 3 4 to 3 6 pins 1 50 figure 3 5 pins 51 100 f...

Page 131: ...l connections pin assignments figure 3 2 theory of operation 4 4 digital I O power up state selection 3 9 to 3 12 high DIO power up state 3 9 to 3 10 low DIO power up state 3 11 to 3 12 digital I O specifications A 1 to A 2 digital logic level specifications A 1 digital power up state selection See digital I O power up state selection DIRQ0 bit D 8 DIRQ1 bit D 8 documentation conventions used in m...

Page 132: ... word definitions mode 1 strobed input D 16 mode 1 strobed output D 18 INTEN bit description D 10 interrupt handling D 35 Interrupt Control Register Group D 7 to D 10 Interrupt Control Register 1 D 8 to D 9 Interrupt Control Register 2 D 10 overview D 7 register map D 3 interrupt handling D 35 to D 36 interrupt level selection PC DIO 96 E 8 to E 9 factory settings table E 4 IRQ5 default setting fi...

Page 133: ... D 16 programming example D 16 to D 17 purpose and use D 11 mode 1 strobed output 82C55A Programmable Peripheral Interface D 17 to D 20 control word written to CNFG Register figure D 17 to D 18 Port C pin assignments figure D 19 Port C status word bit definitions for output D 18 programming example D 19 to D 20 purpose and use D 11 mode 2 bidirectional timing figure 3 16 mode 2 operation 82C55A Pr...

Page 134: ...eset control words table D 6 signal assignments programmable mode signal assignments table 3 4 programming modes 3 4 status word bit definitions mode 1 strobed input D 15 to D 16 mode 1 strobed output D 18 mode 2 operation D 22 power connections 3 9 power requirements A 2 programming See register level programming R RD signal description table 3 13 mode 1 input timing figure 3 14 mode 2 bidirectio...

Page 135: ...terrupt Control Register 2 D 10 overview D 7 register map D 2 to D 3 reset Port C set reset control words table D 6 single bit reset feature D 12 S signal connections 3 1 to 3 16 cable assembly connectors 3 4 to 3 6 pins 1 50 figure 3 5 pins 51 100 figure 3 6 digital I O power up state selection high DIO power up state 3 9 to 3 10 low DIO power up state 3 11 to 3 12 digital I O signal connections ...

Page 136: ...heory of operation 4 1 to 4 4 82C53 Programmable Interval Timer 4 3 82C55A Programmable Peripheral Interface 4 3 data transceivers 4 2 digital I O connector 4 4 interrupt control circuitry 4 2 PC I O channel control circuitry 4 2 PC DIO 96 PnP block diagram 4 1 Plug and Play circuitry 4 2 timing specifications 3 12 to 3 16 mode 1 input timing 3 14 mode 1 output timing 3 15 mode 2 bidirectional tim...

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