Appendix C
Register-Level Programming
PC-DIO-24/PnP User Manual
C-18
©
National Instruments Corporation
During a mode 2 data transfer, the status of the handshaking lines and
interrupt signals can be obtained by reading port C. The port C status-
word bit definitions for a mode 2 transfer are shown as follows.
Port C status-word bit definitions for bidirectional data path (port A
only):
Bit
Name
Description
7
OBFA*
Output Buffer for Port A—A low setting indicates that
the CPU has written data to port A.
6
INTE1
Interrupt Enable Bit for Port A Output Interrupts—
Setting this bit enables output interrupts from port A
of the 82C55A. This bit is controlled by
setting/resetting PC6.
5
IBFA
Input Buffer for Port A—A high setting indicates that
data has been loaded into the input latch of port A.
4
INTE2
Interrupt Enable Bit for Port A Input Interrupts—
Setting this bit enables input interrupts from port A of
the 82C55A. This bit is controlled by setting/resetting
PC4.
3
INTRA
Interrupt Request Status for Port A—If INTE1 and
IBFA are high, then this bit is high, indicating that an
interrupt request is pending for port A input transfers.
If INTE2 and OBFA* are high, then this bit is high,
indicating that an interrupt request is pending for
port A output transfers.
2–0
I/O
Input/Output—These bits can be used for general-
purpose I/O lines if group B is configured for mode 0.
If group B is configured for mode 1, refer to the bit
explanations shown in the preceding mode 1 sections.
D7
D6
D5
D4
D3
D2
D1
D0
OBFA*
INTE1
IBFA
INTE2
INTRA
I/O
I/O
I/O
