Chapter 2
Hardware Overview of the NI PXI-7831R
©
National Instruments Corporation
2-19
Caution
Do
not
drive the same PXI trigger bus line on the same PXI bus segment with the
NI PXI-7831R and another device simultaneously. Such signal driving can damage both
devices. NI is
not
liable for any damage resulting from such signal driving.
Refer to the
PXI Hardware Specification Revision 2.1
and
PXI Software
Specification Revision 2.1
at
www.pxisa.org
for more information about
PXI triggers.
PXI Local Bus
The NI PXI-7831R can communicate with other PXI devices using the PXI
local bus. The PXI local bus is a daisy-chained bus that connects each PXI
peripheral slot with its adjacent peripheral slot on either side. For example,
the right local bus lines from a given PXI peripheral slot connect to the left
local bus lines of the adjacent slot. Each local bus is 13 lines wide. All of
these lines connect to the FPGA on the NI PXI-7831R and can be used like
any of the other NI PXI-7831R DIO lines. The PXI local bus right lines on
the NI PXI-7831R are PXI/LBR<0..12>. The PXI local bus left lines on the
NI PXI-7831R are PXI/LBLSTAR<0..12>.
The NI PXI-7831R can configure each PXI local bus line either as an input
or an output signal. Only one device can drive the same physical local bus
line at a given time. For example, if an NI PXI-7831R is configured to drive
a signal on PXI/LBR<0>, the device in the slot immediately to the right
must have its PXI/LBLSTAR<0> line configured as an input.
Caution
Do
not
drive the same PXI local bus line with the NI PXI-7831R and another
device simultaneously. Such signal driving can damage both devices. NI is
not
liable for
any damage resulting from such signal driving.
The NI PXI-7831R local bus lines are only compatible with 3.3 V signaling
LVTTL and LVCMOS levels.
Caution
Do
not
enable the local bus lines on an adjacent device if the device drives
anything other than 0–3.3V LVTTL signal levels on the NI PXI-7831R. Enabling the lines
in this way can damage the NI PXI-7831R. NI is
not
liable for any damage resulting from
enabling such lines.
The left local bus lines from the left peripheral slot of a PXI backplane
(slot 2) are routed to the star trigger lines of up to 13 other peripheral slots
in a two-segment PXI system. This configuration provides a dedicated,
delay-matched trigger signal between the first peripheral slot and the
