Chapter 3
Hardware Overview
©
National Instruments Corporation
3-15
NI PXI-6682 Series User Manual
Using the PXI Triggers
The PXI trigger bus is a set of 8 electrical lines that go to every slot in a
segment of a PXI chassis (multi-drop up to 8 slots). Only one PXI module
should drive a particular PXI_Trigger line at a given time. The signal is
then received by modules in all other PXI slots. This feature makes the
PXI triggers convenient in situations where you want, for instance, to
trigger several devices at the same time, because all modules will receive
the same trigger.
Given the architecture of the PXI trigger bus, triggering signals do not reach
each slot at precisely the same time. A difference of several nanoseconds
can occur between slots, especially in larger PXI chassis (which can
have buffers between segments). This delay is not a problem for many
applications. However, if your application requires tighter synchronization,
use the PXI_STAR triggers (see next section), or use the PXI trigger bus
synchronous to PXI_CLK10.
The multi-drop nature of the PXI trigger bus can introduce signal integrity
issues. Therefore, National Instruments does not recommend the use of
PXI_Trigger lines for clock distribution, especially for clocks above
20 MHz. The preferred method for clock distribution is the use of the
PXI_STAR triggers. However, the NI PXI-6682 Series does support
routing of clocks to the PXI_Trigger lines, in case you must use them.
For each PXI_Trigger line configured as an output in the
NI PXI-6682 Series, the signal source can be independently selected from
the following options:
•
PFI<0..2>
•
Another PXI trigger line (PXI_TRIG<0..7>)
•
PXI_STAR<0..12>
•
Future time events
•
PXI_CLK10
•
Ground
The PXI trigger outputs may be synchronized to CLK10 except when
routing future time events. Refer to the
section for more information about the synchronization clock.
