Appendix B
Timing Diagrams
B-24
ni.com
If the Sample Clock is being generated by dividing down the Sample Clock
Timebase, the analog output generation is timed from the output of the
UI counter. The signal Sample Clock Timebase can be an external signal.
When the analog output timing engine operates in this mode, it is assumed
that the source signal for the Sample Clock timebase is a free-running
clock, so the Sync Sample Clock Timebase is the inverted version of
Sample Clock Timebase. Configuring the analog output timing engine for
rising edge operation will cause the external signals to be synchronized on
the falling edge of the Sample Clock Timebase, which corresponds to the
rising edge of Sync Sample Clock Timebase.
Figure B-25.
Sample Clock Timebase and the Sync Sample Clock Timebase
Timing Diagram
Table B-13.
External Update Source Clock Insertions Timing
Time
From
To
Min (ns)
Max (ns)
t
2
Signal_i
Sample Clock Timebase
11.6
30.0
t
3
Signal_i
Sync Sample Clock Timebase
1.5
7.0
Table B-14.
Sample Clock Timebase and the Sync Sample Clock Timebase Timing
Time
From
To
Min (ns)
Max (ns)
t
4
Signal_i
Sample Clock Timebase
2.4
9.3
t
5
Signal_i
Sync Sample Clock Timebase
2.4
9.3
S
ign
a
l_i
Sa
mple Clock Time
bas
e
S
ync
Sa
mple Clock Time
bas
e
t
5
t
4
