Chapter 9
Bus Interface
©
National Instruments Corporation
9-7
DAQ-STC Technical Reference Manual
The numbers in parentheses indicate a 100 pF load; all other numbers indicate 15 pF.
The DAQ-STC generates an internal read or write signal based upon the read, write, and
chip-select signals at the pins. The internal signal will be asserted only when both chip select
and the appropriate strobe are asserted, shown in these figures as CS-RD and CS-WR. The
timing parameters are all relative to the combined signal.
Figure 9-3.
Motorola Bus Interface Read Timing
Tds
Data setup time
25
—
Tdh
Data hold time
0
—
All timing values are in nanoseconds.
Table 9-2.
Intel Bus Interface Timing (Continued)
Name
Description
Minimum
Maximum
D<0..15>
A<1..7>
CS-DS
RD/WR
DS
CS
Tads
Trws
Tcs-ds
Trwh
Tadh
Tdi
Tdv
