Chapter 4
Theory of Operation
4-6
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serves as a buffer to the ADC and has two benefits. First, when an A/D
conversion is complete, the value is saved in the A/D FIFO for later reading,
and the ADC is free to start a new conversion. Secondly, the A/D FIFO can
collect up to 512 A/D conversion values before any information is lost, thus
giving the software some extra time (512 times the sample interval) to catch
up with the hardware. If more than 512 values are stored in the A/D FIFO
without the A/D FIFO being read from, an error condition called A/D FIFO
overflow occurs and A/D conversion information is lost.
The A/D FIFO generates a signal that indicates when it contains A/D
conversion data. The state of this signal can be read from the Status
Register.
The output from the ADC is a two’s complement number ranging from
–2,048 to 2,047. The output from the 12-bit ADC is always sign-extended
to 16 bits by the card circuitry so that data values read from the FIFO are
16 bits wide.
Data Acquisition Timing Circuitry
A DAQ operation refers to the process of obtaining a series of successive
A/D conversions at a carefully timed interval called the
sample interval
.
The DAQ timing circuitry consists of various clocks and timing signals that
perform this timing. The DAQCard-700 can perform two types of data
acquisition: single-channel data acquisition and multichannel (scanned)
data acquisition. Scanned data acquisition uses a counter to automatically
switch between AI channels during data acquisition. The
scan interval
is
equal to the number of channels multiplied by the sample interval.
DAQ timing consists of signals that initiate a DAQ operation and generate
scanning clocks. Sources for these signals are supplied mainly by timers on
the DAQCard-700 card. One of the three counters of the MSM82C54 is
reserved for this purpose.
An A/D conversion can be initiated internally during data acquisition by a
low-to-high transition on the counter 0 output (OUT0) of the MSM82C54,
or externally by a low-to-high transition on EXTCONV* input.
The sample-interval timer is a 16-bit down counter that uses the onboard
1 MHz clock to generate sample intervals from 2
µ
s to 65,535
µ
s (Refer to
the
section). Each time the sample-interval timer
reaches zero, it generates a pulse and reloads with the programmed
sample-interval count. This operation continues until the counter is
reprogrammed.
