National Instruments DAQ AT-MIO-16X, User Manual, Page: 194 / 330

Chapter 5 Programming
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National Instruments Corporation 5-25 AT-MIO-16X User Manual
Programming the Analog Output Circuitry
The voltages at the analog output circuitry output pins (pins DAC0
OUT and DAC1 OUT on the AT-MIO-16X I/O connector) are
controlled by loading the DAC in the analog output channel with a
16-bit digital code. The DAC is loaded by writing the digital code to the
DAC0 and DAC1 Registers, and then the converted output is available
at the I/O connector. Writing to the DAC0 Register controls the voltage
at the DAC0 OUT pin, while writing to the DAC1 Register controls the
voltage at the DAC1 OUT pin. The analog output on pins DAC0 OUT
and DAC1 OUT can be updated in one of three ways: immediately when
DAC0 or DAC1 is written to, when an active low pulse is detected on
the TMRTRIG* signal, or when the DAC Update Register is strobed.
The TMRTRIG* signal is either the EXTTMRTRIG* signal from the
I/O connector or an internal signal from the output of Counters 1, 2, 3,
or 5, depending on the state of the A4RCV bit in Command Register 2.
The update method is selected through mode bits in the Command
Register 4.
In the waveform mode where a timer trigger generates an update for the
DACs and a request for new data, the DAC FIFO is used to buffer the
incoming data to both of the DAC channels. Because this FIFO is
2,048 values deep, the last value buffered by the DAC FIFO could lag
the output of the DAC channel by up to 2,048 times the update interval.
Requests can be programmed to be generated whenever the DAC FIFO
is not full or only when the FIFO is less than half-full. If the half-full
method is used, 1,024 values can be written at once without reading the
DAC FIFO flags after each subsequent transfer to keep from overfilling
the FIFO. This mode results in a significant performance increase in
polled I/O or interrupt servicing of the DACs.
The waveform circuitry is configured through mode bits in Command
Register 4 to perform one or two DAC writes per update pulse. If two
DAC channels are being used and single update mode (DACMODEB3
is clear) is enabled, only one value is read from the DAC FIFO and
written to the appropriate DAC channel per update pulse. The result is
that the channel updates are out of phase with respect to each other. If
the dual update mode is used (DACMODEB3 is set), the circuitry will
read up to two values from the DAC FIFO and write them to the
appropriate DAC channels. If the dual update mode is enabled, and only
one DAC is used, then the circuitry will perform only one FIFO read
and DAC write per update pulse. Notice that if two channels are used,
the DAC0 value must be written to the DAC FIFO before the DAC1
value.