© National Instruments
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4-15
PFI
You can configure channels of a parallel digital module as Programmable Function Interface
(PFI) terminals. The cDAQ chassis also provides two terminals for PFI. Up to two digital
modules can be used to access PFI terminals in a single chassis.
You can configure each PFI individually as the following:
•
Timing input signal for AI, AO, DI, DO, or counter/timer functions
•
Timing output signal from AI, AO, DI, DO, or counter/timer functions
PFI Filters
You can enable a programmable debouncing filter on each PFI signal. When the filter is enabled,
the chassis samples the inputs with a user-configured Filter Clock derived from the chassis
timebase. This is used to determine whether a pulse is propagated to the rest of the circuit.
However, the filter also introduces jitter onto the PFI signal.
The following is an example of low-to-high transitions of the input signal. High-to-low
transitions work similarly.
Assume that an input terminal has been low for a long time. The input terminal then changes
from low to high, but glitches several times. When the Filter Clock has sampled the signal high
on
N
consecutive edges, the low-to-high transition is propagated to the rest of the circuit. The
value of
N
depends on the filter setting, as shown in Table 4-1.
Table 4-1.
Selectable PFI Filter Settings
Filter Setting
Filter Clock
Jitter
Min Pulse
Width
*
to Pass
Max Pulse
Width
*
to Not Pass
112.5 ns
(short)
80 MHz
12.5 ns
112.5 ns
100 ns
6.4
μ
s
(medium)
80 MHz
12.5 ns
6.4
μ
s
6.3875
μ
s
2.56 ms (high)
100 kHz
10
μ
s
2.56 ms
2.55 ms
Custom
User-
configurable
1 Filter
Clock
period
T
user
T
user
- (1 Filter
Clock period)
*
Pulse widths are nominal values; the accuracy of the chassis timebase and I/O distortion will affect these
values.
