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Each Convert Clock signals the acquisition of a single channel from that module. The Convert
Clock rate depends on the module being used, the number of channels used on that module, and
the system Sample Clock rate.
The driver chooses the fastest conversion rate possible based on the speed of the A/D converter
for each module and adds 10 µs of padding between each channel to allow for adequate settling
time. This scheme enables the channels to approximate simultaneous sampling. If the AI Sample
Clock rate is too fast to allow for 10 µs of padding, NI-DAQmx selects a conversion rate that
spaces the AI Convert Clock pulses evenly throughout the sample. NI-DAQmx uses the same
amount of padding for all the modules in the task. To explicitly specify the conversion rate, use
the
ActiveDevs
and
AI Convert Clock Rate
properties using the
DAQmx Timing
property
node or functions.
Simultaneous Sample-and-Hold Modules
Simultaneous sample-and-hold (SSH) C Series analog input modules contain multiple A/D
converters or circuitry that allows all the input channels to be sampled at the same time. These
modules sample their inputs on every Sample Clock pulse.
Sigma-Delta Modules
Sigma-delta C Series analog input modules function much like SSH modules, but use A/D
converters that require a high-frequency oversample clock to produce accurate, synchronized
data. Some sigma-delta modules in the cDAQ chassis automatically share a single oversample
clock to synchronize data from all the modules that support an external oversample clock
timebase when they all share the same task. (DSA modules are an example). The cDAQ chassis
supports a maximum of two synchronization pulse signals configured for your system. This
limits the system to two tasks with different oversample clock timebases.
The oversample clock is used as the AI Sample Clock Timebase. While most modules supply a
common oversample clock frequency (12.8 MHz), some modules, such as the NI 9234, supply
a different frequency. When sigma-delta modules with different oversample clock frequencies
are used in an analog input task, the AI Sample Clock Timebase can use any of the available
frequencies; by default, the fastest available is used. The sampling rate of all modules in the
system is an integer divisor of the frequency of the AI Sample Clock Timebase.
When one or more sigma-delta modules are in an analog input task, the sigma-delta modules also
provide the signal used as the AI Sample Clock. This signal is used to cause A/D conversion for
other modules in the system, just as the AI Sample Clock does when a sigma-delta module is not
being used.
When sigma-delta modules are in an AI task, the chassis automatically issues a synchronization
pulse to each sigma-delta modules that resets their ADCs at the same time. Because of the
filtering used in sigma-delta A/D converters, these modules usually exhibit a fixed input delay
relative to non-sigma-delta modules in the system. This input delay is specified in the C Series
module documentation.
