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Chapter 1

Getting Started with the cDAQ Chassis

Removing Modules from the cDAQ Chassis

Complete the following steps to remove a C Series module from the cDAQ chassis.
1.

Make sure that no I/O-side power is connected to the module. If the system is in a 
nonhazardous location, the chassis power can be on when you remove modules.

2.

Squeeze the latches on both sides of the module and pull the module out of the chassis.

Using the cDAQ Chassis

The cDAQ system consists of three parts: C Series module(s), the cDAQ module interface, and 
the STC3, as shown in Figure 1-11. These components digitize signals, perform D/A 
conversions to generate analog output signals, measure and control digital I/O signals, and 
provide signal conditioning.

Figure 1-11.  

Block Diagram

C Series Module

National Instruments C Series modules provide built-in signal conditioning and screw terminal, 
spring terminal, BNC, D-SUB, or RJ-50 connectors. A wide variety of I/O types are available, 
allowing you to customize the cDAQ system to meet your application needs.

C Series modules are hot-swappable and automatically detected by the cDAQ chassis. 
I/O channels are accessible using the NI-DAQmx driver software.

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Summary of Contents for cDAQ-9188XT

Page 1: ...NI cDAQ TM 9188XT User Manual NI CompactDAQ Extended Temperature Rugged Eight Slot Ethernet Chassis NI cDAQ 9188XT User Manual March 2016 373929C 01...

Page 2: ...phone numbers email addresses and current events National Instruments Corporate Headquarters 11500 North Mopac Expressway Austin Texas 78759 3504 USA Tel 512 683 0100 For further support information...

Page 3: ...TLE OR NON INFRINGEMENT AND ANY WARRANTIES THAT MAY ARISE FROM USAGE OF TRADE OR COURSE OF DEALING NI DOES NOT WARRANT GUARANTEE OR MAKE ANY REPRESENTATIONS REGARDING THE USE OF OR THE RESULTS OF THE...

Page 4: ...ependent from NI and have no agency partnership or joint venture relationship with NI Patents For patents covering NI products technology refer to the appropriate location Help Patents in your softwar...

Page 5: ...el Mounting with a Panel Mount Kit 1 11 Panel Mounting without a Panel Mount Kit 1 13 Mounting the cDAQ Chassis on a DIN Rail 1 13 NI cDAQ Chassis Features 1 15 LEDs 1 15 Ethernet Port 1 15 Ethernet L...

Page 6: ...log Source 2 7 Getting Started with AI Applications in Software 2 7 Chapter 3 Analog Output Analog Output Data Generation Methods 3 1 Software Timed Generations 3 1 Hardware Timed Generations 3 2 Buff...

Page 7: ...r 4 13 Getting Started with DO Applications in Software 4 14 Digital Input Output Configuration for NI 9401 4 14 PFI 4 15 PFI Filters 4 15 Chapter 5 Counters Counter Timing Engine 5 2 Counter Input Ap...

Page 8: ...tion 5 23 Single Pulse Generation 5 24 Single Pulse Generation with Start Trigger 5 24 Pulse Train Generation 5 25 Finite Pulse Train Generation 5 25 Retriggerable Pulse or Pulse Train Generation 5 25...

Page 9: ...utput Terminal 5 37 Counter n Internal Output and Counter n TC Signals 5 37 Routing Counter n Internal Output to an Output Terminal 5 37 Frequency Output Signal 5 37 Routing Frequency Output to a Term...

Page 10: ...ation included with your C Series module s or go to ni com manuals Figure 1 1 shows the cDAQ chassis Figure 1 1 NI cDAQ 9188XT Chassis Safety Guidelines Caution Do not operate the NI cDAQ 9188XT in a...

Page 11: ...interference with radio and television reception and prevent unacceptable performance degradation install and use this product in strict accordance with the instructions in the product documentation...

Page 12: ...ot in use Hardware Symbol Definitions The following symbols are marked on your cDAQ chassis Caution When this symbol is marked on a product refer to the Safety Guidelines section for information about...

Page 13: ...disk shipped with your kit and is available for download at ni com support The documentation for NI DAQmx is available after installation from Start All Programs National Instruments NI DAQmx Other N...

Page 14: ...documentation Refer to the LEDs section for more information about making this connection 9 Connect one end of the Ethernet cable to the Ethernet port on the chassis and the other end directly to you...

Page 15: ...either connection is on your local subnet right click Network Devices and select Find Network NI DAQmx Devices If you know the chassis IP address such as 192 168 0 2 enter it into the Add Device Manua...

Page 16: ...es right clicking NI cDAQ 9188XT and selecting Self Test Self test performs a brief test to determine successful chassis installation When the self test finishes a message indicates successful verific...

Page 17: ...tive lead of the power source to the C terminal of the power screw terminal connector plug and tighten the terminal screw 5 Install the power connector plug on the front panel of the cDAQ chassis and...

Page 18: ...is in MAX When the cDAQ chassis is connected to a network multiple users can access the chassis To perform any DAQ functionality on the C Series modules including reset chassis and self test you must...

Page 19: ...you must mount the chassis horizontally to a metal panel or surface using the screw holes or the panel mount kit DIN mounting limits the device to 60 C maximum ambient operating temperature Measure th...

Page 20: ...mount kit to mount the cDAQ chassis on a panel or mount directly to the panel with your own screws For kit accessory ordering information refer to the pricing section of the NI cDAQ 9188XT product pag...

Page 21: ...e these screws with the chassis Refer to the documentation included with the panel mount kit for more detailed dimensions Figure 1 7 cDAQ 9188XT Panel Mount Dimensions and Installation 8 7 6 5 4 3 2 1...

Page 22: ...en the ambient temperature is between 60 C and 70 C you must mount the chassis horizontally to a metal panel or surface using the screw holes or the panel mount kit DIN mounting limits the device to 6...

Page 23: ...chassis onto the DIN rail with the larger lip of the DIN rail clip positioned up as shown in Figure 1 10 Figure 1 10 DIN Rail Clip Parts Locator Diagram When the DIN rail kit is properly installed th...

Page 24: ...5 Ethernet port on the chassis and the other end directly to your computer or any network connection on the same subnet as your computer 1 Table 1 1 LED State Chassis Status LED Color LED State Chassi...

Page 25: ...and LINK ACT described in Table 1 2 Table 1 2 Ethernet LED Indications LED Color LED State Chassis Status 10 100 1000 Yellow On Connected at 1000 Mbps Green On Connected at 100 Mbps Off No Ethernet co...

Page 26: ...ables Table 1 3 Ethernet Cable Wiring Connections Pin Connector 1 Connector 2 Normal Crossover 1 white orange white orange white green 2 orange orange green 3 white green white green white orange 4 bl...

Page 27: ...is ships with a 2 position power screw terminal connector plug for use with an external power source Refer to the NI cDAQ 9188XT Specifications for information about the power connector on the cDAQ ch...

Page 28: ...shorter wire for better EMC performance Cables and Accessories Table 1 5 contains information about cables and accessories available for the cDAQ chassis For a complete list of cDAQ chassis accessori...

Page 29: ...the STC3 as shown in Figure 1 11 These components digitize signals perform D A conversions to generate analog output signals measure and control digital I O signals and provide signal conditioning Fig...

Page 30: ...eads and writes For more information about digital I O modules refer to Chapter 4 Digital Input Output and PFI cDAQ Module Interface The cDAQ module interface manages data transfers between the STC3 a...

Page 31: ...signals provide access to advanced features such as triggering synchronization and counter timers You can also enable a programmable debouncing filter on each PFI signal that when enabled samples the...

Page 32: ...es an action such as starting or stopping the acquisition of data When you configure a trigger you must decide how you want to produce the trigger and the action you want the trigger to cause The cDAQ...

Page 33: ...k Timebase signal is divided down to provide a source for Sample Clock AI Sample Clock Timebase can be generated from external or internal sources AI Sample Clock Timebase is not available as an outpu...

Page 34: ...dules in the cDAQ chassis automatically share a single oversample clock to synchronize data from all the modules that support an external oversample clock timebase when they all share the same task DS...

Page 35: ...ask will return 1 000 new data points per second which is normal When performing a single point acquisition no points are repeated To avoid this behavior use multiple AI timing engines and assign slow...

Page 36: ...Start Trigger signal to any output PFI terminal The output is an active high pulse AI Reference Trigger Signal Use Reference Trigger to stop a measurement acquisition To use a reference trigger speci...

Page 37: ...sing or falling edge of the Analog Comparison Event signal depending on the trigger properties Note Depending on the C Series module capabilities you may need two modules to utilize analog triggering...

Page 38: ...s high or vice versa Note Depending on the C Series module capabilities you may need two modules to utilize analog triggering Note Pause triggers are only sensitive to the level of the source not the...

Page 39: ...ods When performing an analog output operation you either can perform software timed or hardware timed generations Hardware timed generations must be buffered Software Timed Generations With a softwar...

Page 40: ...continuous generation continues until you stop the operation There are three different continuous generation modes that control how the data is written These modes are regeneration onboard regenerati...

Page 41: ...ng signals AO Sample Clock Signal AO Sample Clock Timebase Signal AO Start Trigger Signal AO Pause Trigger Signal Signals with an support digital filtering Refer to the PFI Filters section of Chapter...

Page 42: ...AX topic in the NI DAQmx Help or the LabVIEW Help for more information You also can specify whether the waveform generation begins on the rising edge or falling edge of AO Start Trigger Using an Analo...

Page 43: ...polarity The source can be a PFI signal or one of several other internal signals on the cDAQ chassis You also can specify whether the samples are paused when AO Pause Trigger is at a logic high or lo...

Page 44: ...ot perform any operation until the cDAQ chassis is reset You can set the watchdog timer timeout period to specify the amount of time that must elapse before the watchdog timer expires The counter on t...

Page 45: ...ou can use the cDAQ chassis in the following analog output applications Single point on demand generation Finite generation Continuous generation Waveform generation For more information about program...

Page 46: ...is slot and can perform the following tasks Software timed and hardware timed digital input output tasks Parallel digital I O modules can be used in any chassis slot and can perform the following task...

Page 47: ...es of digital triggering internal software digital triggering external digital triggering and internal digital triggering Three triggers are available Start Trigger Reference Trigger and Pause Trigger...

Page 48: ...Sample Clock Timebase Signal The DI Sample Clock Timebase di SampleClockTimebase signal is divided down to provide a source for DI Sample Clock DI Sample Clock Timebase can be generated from external...

Page 49: ...tware command in continuous mode An acquisition that uses a start trigger but not a reference trigger is sometimes referred to as a posttriggered acquisition That is samples are measured only after th...

Page 50: ...ecified number of pretrigger samples the chassis ignores the condition If the buffer becomes full the cDAQ chassis continuously discards the oldest samples in the buffer to make space for the next sam...

Page 51: ...internal sample clock pauses while the external trigger signal is active and resumes when the signal is inactive You can program the active level of the pause trigger to be high or low Using a Digita...

Page 52: ...2 Tp and 1 Tp are not defined because they depend on the phase of the Filter Clock relative to the input signal Figure 4 3 shows an example of low to high transitions of the input signal High to low t...

Page 53: ...assis onboard FIFO then transferred to a PC buffer Buffered acquisitions typically allow for much faster transfer rates than nonbuffered acquisitions because data accumulates and is transferred in blo...

Page 54: ...een samples can be much shorter The timing between samples is deterministic Hardware timed acquisitions can use hardware triggering Hardware timed DO operations on the cDAQ chassis must be buffered Bu...

Page 55: ...e written to the buffer If the program does not write new data to the buffer at a fast enough rate to keep up with the generation the buffer underflows and causes an error Digital Output Triggering Si...

Page 56: ...Trigger Signal Use the DO Start Trigger do StartTrigger signal to initiate a waveform generation If you do not use triggers you can begin a generation with a software command If you are using an inter...

Page 57: ...es module capabilities you may need two modules to utilize analog triggering Routing DO Start Trigger Signal to an Output Terminal You can route DO Start Trigger to any output PFI terminal The output...

Page 58: ...epending on the trigger properties When you use an analog trigger source the samples are paused when the Analog Comparison Event signal is at a high or low level depending on the trigger properties Th...

Page 59: ...cDAQ chassis while the watchdog timer task is being started this includes all DAQmx tasks calibration of modules and routing and configuration of signals on the chassis After the watchdog timer task...

Page 60: ...However the filter also introduces jitter onto the PFI signal The following is an example of low to high transitions of the input signal High to low transitions work similarly Assume that an input te...

Page 61: ...d Figure 4 7 shows an example of a low to high transition on an input that has a custom filter set to N 5 Figure 4 7 PFI Filter Example 1 2 3 1 4 1 2 3 4 5 PFI Terminal Filtered input goes high when t...

Page 62: ...unter signals refer to the Default Counter Timer Routing section Each counter has a FIFO that can be used for buffered acquisition and generation Each counter also contains an embedded counter Embedde...

Page 63: ...erations require a sample clock For example a simple buffered pulse width measurement latches in data on each edge of a pulse For this measurement the measured signal determines when data is latched i...

Page 64: ...es can be read on demand or with a sample clock Refer to the following sections for more information about edge counting options Single Point On Demand Edge Counting Buffered Sample Clock Edge Countin...

Page 65: ...cumulative counts since the counter armed event That is the sample clock does not reset the counter You can configure the counter to sample on the rising or falling edge of the sample clock Figure 5 4...

Page 66: ...er is armed while a pulse train is in progress If a counter is armed while the pulse is in the active state it will wait for the next transition to the active state to begin the measurement Refer to t...

Page 67: ...locked buffered pulse width measurement is similar to single pulse width measurement but buffered pulse width measurement takes measurements over multiple pulses correlated to a sample clock The count...

Page 68: ...the following sections for more information about cDAQ chassis pulse measurement options Single Pulse Measurement Implicit Buffered Pulse Measurement Sample Clocked Buffered Pulse Measurement Single P...

Page 69: ...edge the counter stores the high and low ticks in the FIFO of the last pulse to complete The STC3 transfers the sampled values to host memory using a high speed data stream Figure 5 10 shows an exampl...

Page 70: ...Semi Period Measurement Refer to the Pulse versus Semi Period Measurements section for information about the differences between semi period measurement and pulse measurement Single Semi Period Measu...

Page 71: ...high times and five low times When you read 10 points in a pulse measurement you get an array of 10 pairs of high and low times Also pulse measurements support sample clock timing while semi period me...

Page 72: ...s always paired with Counter 1 Counter 2 is always paired with Counter 3 In this method you route a pulse of known duration T to the Gate of a counter You can generate the pulse using a second counter...

Page 73: ...ncy This technique is called reciprocal frequency measurement When measuring a large range of frequencies with two counters you generate a long pulse using the signal to measure You then measure the l...

Page 74: ...fx fk N J Sample Clocked Buffered Frequency Measurement Sample clocked buffered point frequency measurements can either be a single frequency measurement or an average between sample clocks Use CI Fr...

Page 75: ...fast as the sample clock to prevent a measurement overflow Choosing a Method for Measuring Frequency The best method to measure frequency depends on several factors including the expected frequency of...

Page 76: ...e counter measurement but now the user has an integer divide down of the signal An internal timebase is still used for the source frequency fk but the divide down means that the measurement time is th...

Page 77: ...est in the sample clocked and two counter large range measurements For another example Table 5 4 shows the results for 5 MHz Table 5 3 50 kHz Frequency Measurement Methods Variable Sample Clocked One...

Page 78: ...en sample clocks Low frequency measurements with one counter is a good method for many applications However the accuracy of the measurement decreases as the frequency increases High frequency measurem...

Page 79: ...multiplying the period of the Source signal by the number of edges returned by the counter Period measurements return the inverse results of frequency measurements Refer to the Frequency Measurement s...

Page 80: ...behavior holds for X2 encoding except the counter increments or decrements on each edge of channel A depending on which channel leads the other Each cycle results in two increments or decrements as sh...

Page 81: ...ter the reload occurs the counter continues to count as before The figure illustrates channel Z reload with X4 decoding Figure 5 20 Channel Z Reload with X4 Decoding Measurements Using Two Pulse Encod...

Page 82: ...he Aux input the counter counts the number of rising or falling edges on the Source The counter ignores additional edges on the Aux input The counter stops counting upon receiving an active edge on th...

Page 83: ...ing edges on the Source input occurring between an active edge of the Gate signal and an active edge of the Aux signal The counter then stores the count in the FIFO On the next active edge of the Gate...

Page 84: ...easurement Note If an active edge on the Gate and an active edge on the Aux does not occur between sample clocks an overrun error occurs For information about connecting counter signals refer to the D...

Page 85: ...Single Pulse Generation Single Pulse Generation with Start Trigger The counter can output a single pulse in response to one pulse on a hardware Start Trigger signal The pulse appears on the Counter n...

Page 86: ...enerated by the primary counter When the embedded counter reaches the specified tick count it generates a trigger that stops the primary counter generation Figure 5 28 Finite Pulse Train Generation Fo...

Page 87: ...with CO EnableInitalDelayOnRetrigger set to the default False Figure 5 30 Retriggerable Single Pulse Generation False Note The minimum time between the trigger and the first active edge is two ticks...

Page 88: ...put signal is equal to the frequency of the Source input divided by M N For information about connecting counter signals refer to the Default Counter Timer Routing section Buffered Pulse Train Generat...

Page 89: ...s Instead of generating a set number of data samples and stopping a continuous generation continues until you stop the operation Each point you write generates a single pulse All points are generated...

Page 90: ...utput With FIFO regeneration the entire buffer is downloaded to the FIFO and regenerated from there Once the data is downloaded new data cannot be written to the FIFO To use FIFO regeneration the enti...

Page 91: ...cy generator is independent of the four general purpose 32 bit counter timer modules on the cDAQ chassis Figure 5 34 shows a block diagram of the frequency generator Figure 5 34 Frequency Generator Bl...

Page 92: ...es not receive a watchdog reset software command within the time specified for the watchdog timer the outputs go to a user defined expiration state and remain in that state until the watchdog timer is...

Page 93: ...se on the output increases by 10 every time a new pulse is generated Suppose you program your counter to generate pulses with a delay of 100 and pulse width of 200 each time it receives a trigger Furt...

Page 94: ...ounter 1 Source the source input to Counter 1 Counter 2 Source the source input to Counter 2 or Counter 3 Source the source input to Counter 3 Note All counter timing signals can be filtered Refer to...

Page 95: ...available routing options Routing Counter n Source to an Output Terminal You can route Counter n Source out to any PFI terminal Counter n Gate Signal The Counter n Gate signal can perform many differe...

Page 96: ...be routed to the Counter n Aux input Any PFI terminal AI Reference Trigger AI Start Trigger Analog Comparison Event Change Detection Event In addition a counter s Internal Output Gate or Source can be...

Page 97: ...er Internally software routes the Arm Start Trigger to the Counter n HW Arm input of the counter Routing Signals to Counter n HW Arm Input Any of the following signals can be routed to the Counter n H...

Page 98: ...mple Clock Routing Counter n Sample Clock to an Output Terminal You can route Counter n Sample Clock out to any PFI terminal The PFI circuitry inverts the polarity of Counter n Sample Clock before dri...

Page 99: ...erations you can use the arm start trigger to have start trigger like behavior The arm start trigger can be used for synchronizing multiple counter input and output tasks When using an arm start trigg...

Page 100: ...caler acts as a frequency divider on the Source and puts out a frequency that is one eighth or one half of what it is accepting as shown in Figure 5 37 Figure 5 37 Prescaling Prescaling is intended to...

Page 101: ...External or Internal Source Less than 20 MHz With an external or internal source less than 20 MHz the module generates a delayed Source signal by delaying the Source signal by several nanoseconds The...

Page 102: ...ient data movement Routes timing and control signals The acquisition generation sub systems use these signals to manage acquisitions and generations These signals can come from the following sources Y...

Page 103: ...y of the AI and AO timing signals It can function as the Source input to the 32 bit general purpose counter timers The 20 MHz Timebase is generated by dividing down the 80 MHz Timebase as shown in Fig...

Page 104: ...plication software package and driver includes information about writing applications for taking measurements and controlling measurement devices The following references to documents assume you have...

Page 105: ...ctions palettes menus and tools Refer to the following locations on the Contents tab of the LabVIEW Help for information about NI DAQmx VI and Function Reference Measurement I O VIs and Functions DAQm...

Page 106: ...help with NI DAQmx methods and properties refer to the NationalInstruments DAQmx namespace and the NationalInstruments DAQmx ComponentModel namespace For conceptual help with NI DAQmx refer to Using t...

Page 107: ...ning courses To enroll in a course or obtain a detailed course outline refer to ni com training Technical Support on the Web For additional support refer to ni com support or ni com examples Note You...

Page 108: ...fy your systems accuracy and reliability requirements and provides warranty sparing and calibration services to help you maintain accuracy and minimize downtime over the life of your system Visit ni c...

Page 109: ...tions Engineers make sure every question submitted online receives an answer Software Support Service Membership The Standard Service Program SSP is a renewable one year subscription included with alm...

Page 110: ...C documentation A 3 applications counter input 5 3 counter output 5 23 edge counting 5 3 arm start trigger 5 38 B buffered edge counting 5 4 hardware timed generations analog output 3 2 digital output...

Page 111: ...O modules 4 1 static DIO 4 2 waveform acquisition 4 2 digital input filters parallel DIO modules only 4 7 getting started with applications in software 4 7 timing signals 4 2 triggering 4 2 digital in...

Page 112: ...pplications in software 4 14 H hardware timed generations analog output 3 1 digital output 4 9 I implicit buffered pulse width measurement 5 6 semi period measurement 5 9 installation 1 4 internal sou...

Page 113: ...1 9 reset button 1 17 retriggerable single pulse generation 5 25 S sample clock edge counting 5 4 measurement 5 20 semi period measurement 5 9 implicit buffered 5 9 single 5 9 simple pulse generation...

Page 114: ...NI cDAQ 9188XT User Manual National Instruments I 5 U unpacking 1 3 using the cDAQ chassis 1 20 W watchdog timer 3 6 4 13 5 31 X X1 encoding 5 19 X2 encoding 5 19 X4 encoding 5 19...

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