Contents
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Chapter 4
Generating Code for Real-Time Operating Systems
Processors Table ............................................................................... 4-3
Scheduler Priority Table ................................................................... 4-4
Subsystem Table............................................................................... 4-4
Interrupt Procedure SuperBlock Table ............................................. 4-5
Background Procedure SuperBlock Table........................................ 4-6
Startup Procedure SuperBlock Table ............................................... 4-7
Processor IP Name Table ................................................................. 4-7
Version Table ................................................................................... 4-8
Chapter 5
Generated Code Architecture
Default Names................................................................................................. 5-1
Signal Naming................................................................................................. 5-2
Duplicate Names ............................................................................................. 5-2
Selection of a Signal Name ............................................................................. 5-2
Subsystem and Procedure Boundaries.............................................. 5-2
Sequencing Variable Blocks............................................................. 5-3
Global Variable Block and %var Equivalence ................................. 5-4
Optimization for Read-From Variable Blocks ................................. 5-4
Discrete and Continuous SuperBlocks Versus Subsystems............................ 5-5
Top-Level SuperBlock ..................................................................... 5-6
Block Ordering................................................................................................ 5-6
Interface Layers............................................................................................... 5-6
Scheduler External Interface Layer................................................................. 5-7