National Instruments AT-MIO-64F-5, User Manual

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Theory of Operation Chapter 3
AT-MIO-64F-5 User Manual 3-20 © National Instruments Corporation
Reading the Digital Input Register returns the state of the digital I/O lines. Digital I/O lines
ADIO<3..0> are connected to bits <3..0> of the Digital Input Register. Digital I/O lines
BDIO<3..0> are connected to bits <7..4> of the Digital Input Register. When a port is enabled,
the Digital Input Register serves as a read-back register, returning the digital output value of the
port. When a port is not enabled, reading the Digital Input Register returns the state of the digital
I/O lines driven by an external device.
Both the digital input and output registers are TTL-compatible. The digital output ports, when
enabled, are capable of sinking 24 mA of current and sourcing 2.6 mA of current on each digital
I/O line. When the ports are not enabled, the digital I/O lines act as high-impedance inputs.
The external strobe signal EXTSTROBE*, shown in Figure 3-16, is a general-purpose strobe
signal. Writing to an address location on the AT-MIO-64F-5 board generates an active low
500-nsec pulse on this output pin. EXTSTROBE* is not necessarily part of the digital I/O
circuitry but is shown here because it can be used to latch digital output from the AT-MIO-64F-5
into an external device.
Timing I/O Circuitry
The AT-MIO-64F-5 uses an Am9513A Counter/Timer for data acquisition timing and for
general-purpose timing I/O functions. An onboard oscillator is used to generate the 10 MHz
clock. Figure 3-17 shows a block diagram of the timing I/O circuitry.
GATE4
RTSI Bus
/
2
/
16
1 MHz
DATA<15..0>
Am9513A RD/WR
CONVERT
SCANCLK
CONFIGCLK
Data
Acquisition
Timing
SOURCE4
SOURCE3
OUT1
OUT2
OUT3
OUT4
OUT5
GATE3
Am9513A
Five-Channel
Counter/
Timer
GATE5
SOURCE5
OUT5
GATE2
OUT2
GATE1
SOURCE1
OUT1
FOUT
I/O Connector
EXTTRIG*
Flip
Flop
GATE4
PC I/O Channel
BRDCLK
(10 MHz)
÷
5
÷
2
SOURCE2
5 MHz
Figure 3-17. Timing I/O Circuitry Block Diagram