National Instruments AT-MIO-64F-5, User Manual

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Theory of Operation Chapter 3
AT-MIO-64F-5 User Manual 3-16 © National Instruments Corporation
DAC Waveform Timing Circuitry
Waveform timing implies precise updating of the analog output DACs to create a pure waveform
without any jitter or uncertainty. This timing is accomplished by posting updates to the DACs.
Posted update mode configures the DACs to buffer values written to them and update the output
voltage only after a trigger signal. This trigger signal can come in the form of an internal counter
pulse from Counters 1, 2, 3, or 5 of the Am9513A Counter/Timer, it can be supplied from the
EXTTMRTRIG* signal at the I/O connector, or it can be obtained by accessing a register in the
AT-MIO-64F-5 register set.
In the posted update mode, requests for writes to the DAC are generated from the TMRREQ
signal and can be acknowledged in one of three waysÐeither polled I/O through monitoring the
TMRREQ signal in Status Register 1, interrupts, or DMA. All three response mechanisms will
have a delay associated with them in how fast they can respond to the requesting signal. DMA
will have the fastest response, followed by polled I/O, and finally interrupts. The advantage of
using interrupts is that the CPU is not solely dedicated to monitoring Status Register 1 and can
simultaneously perform other tasks. If writes generated from these requests updated the DAC
immediately, there could be significant jitter in the resulting output waveform, so values are
written to a buffer where they are updated later with a precisely timed update signal. Figure 3-11
depicts the timing for the posted DAC update mode.
Update Trigger
TMRREQ
DAC Write*
X Y
Z
X-1 X Y DAC Output
Figure 3-11. Posted DAC Update Timing
In Figure 3-11, the update trigger signal serves to update the previously written value to the
DAC. In the posted update mode, the DAC FIFO is used to buffer the data. Requests are
generated either when the FIFO is not full or when the FIFO is less than half full. One of these
two signals generates the TMRREQ signal. In the example above, requesting is generated when
the FIFO is not full. Because each update removes a value from the DAC FIFO, each update
also results in the TMRREQ signal being asserted. This sequence of events continues until the
output buffer data is exhausted.
There are effectively two different modes in which to operate the DAC FIFOs in posted update
mode. Data flows in and out at equal rates, or data is initialized in the FIFO and, once updating
begins, the data is cycled through when the end of the FIFO buffer is encountered. If waveform
cycles involving more than 2,048 values are required, data must continuously flow into and out
of the FIFO buffer to be replenished. If waveform cycles of less than 2,048 points are required,
the data can be transferred to the DAC FIFO only once where it can be cycled through to
generate a continuous waveform. This mode removes the burden on the PC to continuously
transfer new data to the DAC FIFO buffer, allowing it to perform other operations. In both
cases, waveforms like the one shown in Figure 3-12 can be realized.