National Instruments AT-MIO-64F-5, User Manual

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Configuration and Installation Chapter 2
AT-MIO-64F-5 User Manual 2-32 © National Instruments Corporation
tw 50 nsec minimum V
IL
V
IH
tw
tw
First A/D conversion starts within 1 sample interval from this point
Figure 2-15. EXTTRIG* Signal Timing
The EXTTRIG* pin is also used to initiate AT-MIO-64F-5 pretriggered data acquisition
operations. In pretriggered mode, data is acquired after the first falling edge trigger is received,
but no sample counting occurs until after a second falling edge trigger is applied to the
EXTTRIG* pin. The acquisition then completes when the sample counter decrements to zero.
This mode acquires data both before and after a hardware trigger is received.
The minimum pulse width allowed is 50 nsec. The first A/D conversion starts within one sample
interval from the high-to-low edge. The sample interval is controlled by Counter 3 or
EXTCONV*. There is no maximum pulse width limitation; however, EXTTRIG* should be
high for at least 50Ênsec before going low. The EXTTRIG* signal is one HCT load and is pulled
up to +5 V through a 10 k
W
resistor.
The EXTTRIG* signal is logically ANDed with the internal DAQSTART signal. If a data
acquisition sequence is to be initiated with an internal trigger, EXTTRIG* must be high at both
the I/O connector and the RTSI switch. If EXTTRIG* is low, the sequence will not be triggered.
In addition, triggers from the EXTTRIG* signal can be inhibited through programming of a
register in the AT-MIO-64F-5 register set.
EXTGATE* Signal
EXTGATE* is an input signal used for hardware gating. EXTGATE* controls A/D conversion
pulses. If EXTGATE* is low, no A/D conversion pulses occur from EXTCONV* or the
sample-interval counter. If EXTGATE* is high, conversions take place if programmed and
otherwise enabled.
EXTTMRTRIG* Signal
The analog output DACs on the AT-MIO-64F-5 can be updated using either internal or external
signals in posted update mode. The DACs can be updated externally by using the
EXTTMRTRIG* signal from the I/O connector. This signal updates the DACs when A4RCV is
disabled and the appropriate DAC waveform mode is programmed through one of the registers in
the AT-MIO-64F-5 register set.
The analog output DACs are updated by the high-to-low edge of the applied pulse. Figure 2-16
shows the timing requirements for the EXTTMRTRIG* signal.