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Programming

Chapter 4

AT-MIO-16D User Manual

4-62

© National Instruments Corporation

data. This condition occurs if the software loop reading the A/D FIFO Register is not fast
enough to keep up with the A/D conversion rate. When an overflow occurs, at least one A/D
conversion result is lost. An overflow condition has occurred if the OVERFLOW bit in the
Status Register is set.

An overrun condition occurs if a second A/D conversion is initiated before the previous
conversion is finished. This condition may result in one or more missing A/D conversions. This
condition occurs if the sample interval is too small (the sample rate is too high). An overrun
condition has occurred if the OVERRUN bit in the Status Register is set.

Scanned data acquisition requires slower data acquisition rates than single-channel data
acquisition because signals must settle each time channels are switched. See Table 4-4 for the
maximum recommended multiple-channel data acquisition rates.

Both the OVERFLOW and OVERRUN bits in the Status Register are cleared by writing to the
A/D Clear Register.

Multiple A/D Conversions with Interval Channel Scanning (Pseudo-Simultaneous)

Programming scanned multiple A/D conversions with a scan interval involves the following
programming steps:

1. Set up the analog channel and gain selection sequence.

2. Program the sample-interval counter.

3. Program the sample counter.

4. Program the scan-interval counter.

5. Clear the A/D circuitry and reset the multiplexer counter.

6. Enable the scanning data acquisition operation.

7. Apply a trigger.

8. Service the data acquisition operation.

Setting the SCANEN bit in Command Register 1 enables scanning during multiple A/D
conversions. You must set this bit regardless of the type of scanning used; otherwise, only a
single channel is scanned. In addition, a channel and gain scan sequence must be stored in the
mux-gain memory.

Setting the SCN2 bit in Command Register 2 enables the use of a scan interval during multiple
A/D conversions. The scan-interval counter gives each cycle through the scan sequence a time
interval. The scan-interval counter begins counting at the start of the scan sequence programmed
into the mux-gain memory. When the scan sequence completes, the next cycle through the scan
sequence does not begin until the scan-interval counter has reached its terminal count. Be sure
that the scan-interval counter allows enough time for all conversions in a scan sequence to occur
so that conversions are not missed.

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Summary of Contents for AT-MIO-16D

Page 1: ... Copyright 1992 1995 National Instruments Corporation All Rights Reserved AT MIO 16D User Manual Multifunction I O Board for the PC AT March 1995 Edition Part Number 320489 01 ...

Page 2: ...tria 0662 435986 Belgium 02 757 00 20 Canada Ontario 519 622 9310 Canada Québec 514 694 8521 Denmark 45 76 26 00 Finland 90 527 2321 France 1 48 14 24 24 Germany 089 741 31 30 Italy 02 48301892 Japan 03 3788 1921 Mexico 95 800 010 0793 Netherlands 03480 33466 Norway 32 84 84 00 Singapore 2265886 Spain 91 640 0085 Sweden 08 730 49 70 Switzerland 056 20 51 51 Taiwan 02 377 1200 U K 0635 523545 ...

Page 3: ... for any damages arising out of or related to this document or the information contained in it EXCEPT AS SPECIFIED HEREIN NATIONAL INSTRUMENTS MAKES NO WARRANTIES EXPRESS OR IMPLIED AND SPECIFICALLY DISCLAIMS ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE CUSTOMER S RIGHT TO RECOVER DAMAGES CAUSED BY FAULT OR NEGLIGENCE ON THE PART OF NATIONAL INSTRUMENTS SHALL BE LIMITED TO T...

Page 4: ...r or application designer Any use or application of National Instruments products for or involving medical or clinical treatment must be performed by properly trained and qualified medical personnel and all traditional medical safeguards equipment and procedures that are appropriate in the particular situation to prevent serious injury or death should always continue to be used when National Instr...

Page 5: ...troduction describes the AT MIO 16D lists the contents of your AT MIO 16D kit the optional software and optional equipment and explains how to unpack the AT MIO 16D Chapter 2 Configuration and Installation describes the AT MIO 16D jumper configuration installation of the AT MIO 16D board into the PC signal connections to the AT MIO 16D board cable wiring and handshake timing diagrams for the DIO 2...

Page 6: ...ur products The Index alphabetically lists topics covered in this manual including the page where the topic can be found Conventions Used in This Manual The following conventions are used to distinguish elements of text throughout this manual italic Italic text denotes emphasis a cross reference or an introduction to a key concept PC PC refers to the IBM PC AT and compatible computers Abbreviation...

Page 7: ...stor logic VDC volts direct current Related Documentation The following document contains information that you may find helpful as you read this manual IBM Personal Computer AT Technical Reference manual You may also want to consult the following Advanced Micro Devices manual if you plan to program the Am9513A Counter Timer used on the AT MIO 16D Am9513A Am9513 System Timing Controller technical m...

Page 8: ...Output Configuration 2 15 Analog Output Reference Selection 2 15 External Reference Selection 2 15 Internal Reference Selection Factory Setting 2 15 Analog Output Polarity Selection 2 16 Bipolar Output Selection Factory Setting 2 16 Straight Binary Mode 2 17 Two s Complement Mode Factory Setting 2 17 Unipolar Output Selection 2 18 RTSI Bus Clock Selection 2 18 Hardware Installation 2 20 Signal Con...

Page 9: ... Wiring 2 50 Field Wiring Considerations 2 50 MIO 16 Cabling Considerations 2 50 DIO 24 Cabling Considerations 2 51 Chapter 3 Theory of Operation 3 1 MIO 16 Functional Overview 3 1 PC AT I O Channel Interface Circuitry 3 2 Analog Input and Data Acquisition Circuitry 3 4 Analog Input Circuitry 3 6 Analog Input Multiplexers 3 6 Analog Input Mode Selection 3 6 The Instrumentation Amplifier 3 6 Channe...

Page 10: ... 4 18 INT2CLR Register 4 19 Analog Input Register Group 4 20 Mux Counter Register 4 21 Mux Gain Register 4 22 A D FIFO Register 4 24 DMA TC INT Clear Register 4 25 Am9513A Counter Timer Register Group 4 26 Am9513A Data Register 4 27 Am9513A Command Register 4 28 Am9513A Status Register 4 29 MIO 16 Digital I O Register Group 4 30 MIO 16 Digital Input Register 4 31 MIO 16 Digital Output Register 4 3...

Page 11: ...gramming the MIO 16 Digital I O Circuitry 4 72 Programming the Am9513A Counter Timer 4 73 RTSI Bus Trigger Line Programming Considerations 4 73 AT MIO 16D RTSI Signal Connection Considerations 4 74 Programming the RTSI Switch 4 75 Programming DMA Operations 4 76 Interrupt Programming 4 77 DIO 24 Circuitry Programming Considerations 4 78 DIO 24 Circuitry Register Descriptions 4 78 82C55A Modes of O...

Page 12: ...Connector only A 5 Timing I O A 5 DIO 24 Circuitry Specifications A 5 I O Signals Rating A 5 Input Signal Specifications A 5 Output Signal Specifications A 6 Transfer Rates A 6 Power Requirement from PC AT I O Channel A 6 Physical A 6 Operating Environment A 6 Storage Environment A 6 Appendix B MIO 16 I O Connector B 1 MIO 16 Signal Connection Descriptions B 2 Appendix C DIO 24 I O Connector C 1 D...

Page 13: ...isconnect from RTSI Bus Clock Use Onboard Oscillator Factory Setting 2 19 Figure 2 22 Receive RTSI Bus Clock Signal 2 19 Figure 2 23 Drive RTSI Bus Clock Signal with Onboard Oscillator 2 20 Figure 2 24 AT MIO 16D I O Connector Pin Assignments 2 21 Figure 2 25 MIO 16 I O Connector Pin Assignments 2 22 Figure 2 26 AT MIO 16D Instrumentation Amplifier 2 26 Figure 2 27 Differential Input Connections f...

Page 14: ...tions Available for the AT MIO 16D 2 10 Table 2 7 Configurations for Input Range and Input Polarity 2 13 Table 2 8 Actual Range and Measurement Precision Versus Input Range Selection and Gain 2 14 Table 2 9 Configurations for RTSI Bus Clock Selection 2 19 Table 2 10 Recommended Input Configurations for Ground Referenced and Floating Signal Sources 2 27 Table 2 11 Port C Signal Assignments 2 45 Tab...

Page 15: ...0 or 1 2 4 and 8 The AT MIO 16D has a 9 µsec converter guaranteed transfer rates of up to 100 ksamples sec and a 512 word A D FIFO buffer to obtain the highest possible data acquisition rate The AT MIO 16D has internal or external A D timing two double buffered multiplying 12 bit DACs unipolar or bipolar voltage output and an onboard DAC reference voltage of 10 V The AT MIO 16D also has onboard ti...

Page 16: ......

Page 17: ...e of data acquisition rates of up to 100 kbytes sec Detailed specifications for the AT MIO 16D are listed in Appendix A Specifications What Your Kit Should Contain Each version of the AT MIO 16D board has a different part number and kit part number listed as follows Kit Name Kit Part Number Kit Component Board Part Number AT MIO 16DL 9 776646 01 AT MIO 16DL 9 board 181965 01 AT MIO 16DH 9 776646 1...

Page 18: ...ttes Optional Software This manual contains complete instructions for directly programming the AT MIO 16D Normally however you should not need to read the low level programming details in the user manual because the NI DAQ software package for controlling the AT MIO 16D is included with the board Using NI DAQ is quicker and easier than and as flexible as using the low level programming described i...

Page 19: ...conditioning SC 2050 without cable SC 2051 without cable SC 2060 optically isolated digital input board with conductor cable 0 2 m 0 4 m SC 2061 optically isolated digital output board with 26 conductor cable 0 2 m 0 4 m SC 2062 electromechanical relay digital control board with 26 conductor cable 0 2 m 0 4 m General purpose termination breadboard SC 2070 without cable SC 2072 without cable SC 207...

Page 20: ...rd The recommended manufacturer part number for this mating connector is as follows Robinson Nugent part number P50E 100S TG Figure 1 2 shows the AT MIO 16D cable assembly MIO 16 50 pin I O Connector DIO 24 50 pin I O Connector AT MIO 16D 100 pin I O Connector AT MIO 16D Board Figure 1 2 AT MIO 16D Cable Assembly Recommended manufacturer part numbers for standard ribbon cable 50 conductor 28 AWG s...

Page 21: ...s Division 3M part number 3439 2 T B Ansley Corporation part number 609 0005 Unpacking Your AT MIO 16D board is shipped in an antistatic plastic bag to prevent electrostatic damage to the board Several components on the board can be damaged by electrostatic discharge To avoid such damage in handling the board take the following precautions Touch the plastic bag to a metal part of your PC chassis b...

Page 22: ...Am9513A Counter Timer and the clock pin on the Real Time System Integration RTSI bus Jumpers W12 and W13 select the DMA channel and the interrupt level respectively Jumper W14 selects the DIO 24 circuitry interrupt enable line AT Bus Interface The AT MIO 16D is configured at the factory to a base I O address of hex 220 to use DMA channels 6 and 7 to use interrupt level 10 for the MIO 16 circuitry ...

Page 23: ......

Page 24: ...er to the technical reference manual for your computer Table 2 2 Default Settings of Other National Instruments Products for the PC Board DMA Channel Interrupt Level Base I O Address AT A2150 None None 120 hex AT AO 6 10 Channel 5 Lines 11 12 1C0 hex AT DIO 32F Channels 5 6 Lines 11 12 240 hex AT DSP2200 None None 120 hex AT GPIB Channel 5 Line 11 2C0 hex AT MIO 16 Channels 6 7 Line 10 220 hex AT ...

Page 25: ...ive least significant bits LSBs of the address A4 through A0 are decoded by the AT MIO 16D to select the appropriate AT MIO 16D register To change the base I O address remove the plastic cover on U61 press each switch to the desired position check each switch to make sure the switch is pressed down all the way and replace the plastic cover Make a note of the new AT MIO 16D base I O address for use...

Page 26: ...1 0 0 380 380 39F 1 1 1 0 1 3A0 3A0 3BF 1 1 1 1 0 3C0 3C0 3DF 1 1 1 1 1 3E0 3E0 3FF This setting is the factory default setting DMA Channel Selection The DMA channel used by the AT MIO 16D is selected by jumpers on W12 as shown in Figure 2 1 The AT MIO 16D is set at the factory to use DMA channels 6 and 7 for dual DMA mode These are the default DMA channels used by the AT MIO 16D software handler ...

Page 27: ...x for proper operation When you use dual DMA mode the left two rows of W12 are used for DMA 1 and the right two rows of W12 are used for DMA 2 Figure 2 3 displays the jumper positions for selecting DMA channels 6 and 7 In this setting DMA 1 uses DMA channel 6 and DMA 2 uses DMA channel 7 W12 R7 A7 R6 A6 R5 A5 Figure 2 3 DMA Jumper Settings for DMA Channels 6 and 7 Factory Setting If you want to us...

Page 28: ...cted interrupt line The interrupt lines supported by the AT MIO 16D hardware for the MIO 16 circuitry are IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ9 IRQ10 IRQ11 IRQ12 IRQ14 and IRQ15 The interrupt lines supported by the AT MIO 16D hardware for the DIO 24 circuitry are IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ9 Note Do not use interrupt line 6 or interrupt line 14 Interrupt line 6 is used by the diskette drive controller an...

Page 29: ...gic low interrupts are enabled from the DIO 24 circuitry of the AT MIO 16D board Refer to Chapter 4 Programming for the suggested interrupt enable line setting for each digital I O mode of operation If W14 is set to N C all interrupt requests from the DIO 24 circuitry are disabled Figure 2 8 shows the possible jumper settings for W14 The board is shipped with this jumper set to PC4 therefore inter...

Page 30: ...Differential DIFF factory setting W6 A C B D E F W9 A B Mode Nonreferenced single ended NRSE W6 A B C E G H W9 B C Referenced single ended RSE W6 A B C D G H W9 B C Am9513A AT MIO 16D clock signal W5 C D E F RTSI Bus 10 MHz factory setting Clock Select AT MIO 16D clock signal W5 A B E F RTSI clock signal AT MIO 16D RTSI clock W5 A B C D signals both 10 MHz DAC0 Internal factory setting W3 B C Refe...

Page 31: ... 16 single ended inputs with the negative input of the instrumentation amplifier referenced to analog ground NRSE Nonreferenced Single Ended configuration Provides 16 single ended inputs with the negative input of the instrumentation amplifier tied to AI SENSE and not connected to ground While reading the following paragraphs you may find it helpful to refer to the Analog Input Signal Connections ...

Page 32: ...negative input of the differential input amplifier is tied to the analog ground This configuration is useful when measuring floating signal sources See the Types of Signal Sources section later in this chapter for more information With this input configuration the AT MIO 16D can monitor 16 different analog input signals You select the RSE analog input configuration by setting jumpers W6 and W9 as ...

Page 33: ...mpers W6 and W9 as follows W6 A B AI SENSE is tied into the negative input of the instrumentation amplifier C E Jumper is placed in standby position Jumper can be discarded G H Multiplexer outputs are tied together into the positive input of the instrumentation amplifier W9 B C Multiplexer control is configured for 16 input channels This configuration is shown in Figure 2 11 H F D B A C E G A B C ...

Page 34: ... to 10 V 20 V range Bipolar A B B C factory setting Figures 2 12 2 13 and 2 14 show the jumper positions for the 0 to 10 V 5 to 5 V and 10 to 10 V input polarity range configurations respectively A B C W4 A B C W1 20 V 10 V ADC Range U B ADC Mode Figure 2 12 0 to 10 V Input Configuration A B C W4 A B C W1 20 V 10 V ADC Range U B ADC Mode Figure 2 13 5 to 5 V Input Configuration A B C W4 A B C W1 2...

Page 35: ...f 1 2 4 and 8 and is suited for high level signals near the range of the ADC The AT MIO 16DL board is designed to measure low level signals and has gains of 1 10 100 and 500 With the proper gain setting the full resolution of the ADC can be used to measure the input signal Table 2 8 shows the overall input range and precision according to the input range configuration and gain used Table 2 8 Actua...

Page 36: ... Reference Selection You select the external reference signal for each analog output channel by setting the following jumpers Analog Output Channel 0 W3 A B External reference signal connected to DAC 0 reference input Analog Output Channel 1 W2 A B External reference signal connected to DAC 1 reference input This configuration is shown in Figure 2 15 W3 A B C W2 A B C EXT INT EXT INT DAC DAC Chann...

Page 37: ... output Vref is the voltage reference used by the DACs in the analog output circuitry and can either be the 10 V onboard reference or an externally supplied reference between 10 V and 10 V Both channels need not be configured the same way however at the factory both channels are configured for bipolar output Bipolar Output Selection Factory Setting You select the bipolar output configuration for e...

Page 38: ...preted as a straight binary number when the following jumpers are set Analog Output Straight Binary for Channel 0 W10 B C Analog Output Straight Binary for Channel 1 W11 B C This configuration is shown in Figure 2 18 A B C W10 2SC BIN DAC 0 A B C W11 2SC BIN DAC 1 Channel 0 Channel 1 Figure 2 18 Straight Binary Mode Two s Complement Mode Factory Setting The data value written to each analog output...

Page 39: ...DAC 0 DAC 1 Channel 0 Channel 1 A B C W10 2SC BIN DAC 0 A B C W11 2SC BIN DAC 1 Channel 0 Channel 1 Figure 2 20 Unipolar Output Configuration Note If you are using a software package such as LabWindows or NI DAQ you may need to reconfigure your software to reflect any changes in jumper or switch settings RTSI Bus Clock Selection When multiple AT Series boards are connected via the RTSI bus you may...

Page 40: ...cy source The jumper selections are listed in Table 2 9 Table 2 9 Configurations for RTSI Bus Clock Selection Configuration W5 Disconnect board from RTSI bus clock use local oscillator C D E F factory setting Receive RTSI bus clock signal A B E F Drive RTSI bus clock signal with local oscillator A B C D Figures 2 21 2 22 and 2 23 show the jumper positions for each of the configurations described a...

Page 41: ... port to the I O channel 3 Remove the expansion slot cover on the back panel of the computer 4 Insert the AT MIO 16D into a 16 bit slot It may be a tight fit but do not force the board into place 5 Screw the mounting bracket of the AT MIO 16D to the back panel rail of the computer 6 Check the installation 7 Replace the cover The AT MIO 16D board is installed and ready for operation Signal Connecti...

Page 42: ...of the AT MIO 16D signal connections AI GND AI GND ACH0 ACH8 ACH1 ACH9 ACH2 ACH10 ACH3 ACH11 ACH4 ACH12 ACH5 ACH13 ACH6 ACH14 ACH7 ACH15 AI SENSE DAC0 OUT DAC1 OUT EXTREF AO GND DIG GND ADIO0 BDIO0 ADIO1 BDIO1 ADIO2 BDIO2 ADIO3 BDIO3 DIG GND 5 V 5 V SCANCLK EXTSTROBE START TRIG STOP TRIG EXTCONV SOURCE1 GATE1 OUT1 SOURCE2 GATE2 OUT2 SOURCE5 GATE5 OUT5 FOUT PC7 GND PC6 GND PC5 GND PC4 GND PC3 GND P...

Page 43: ... 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 FOUT GATE5 OUT2 SOURCE2 GATE1 EXTCONV START TRIG SCANCLK 5 V BDIO3 BDIO2 BDIO1 BDIO0 DIG GND EXTREF DAC0 OUT ACH15 ACH14 ACH13 ACH12 ACH11 ACH10 ACH9 ACH8 AI GND EXTSTROBE AI GND ACH0 ACH1 ACH2 ACH3 ACH4 ACH5 ACH6 ACH7 AI SENSE DAC1 OUT AO GND ADIO0 ADIO1 ADIO2 ADIO3 DIG GND 5 V STOP TRIG SOURCE1 OUT1...

Page 44: ...he voltage output of analog output channel 0 21 DAC1 OUT AOGND Analog Channel 1 Output This pin supplies the voltage output of analog output channel 1 22 EXTREF AOGND External Reference This is the external reference input for the analog output circuitry 23 AO GND N A Analog Output Ground The analog output voltages are referenced to this node 24 33 DIG GND N A Digital Ground This pin supplies the ...

Page 45: ...OURCE1 DIGGND SOURCE1 This pin is from the Am9513A Counter 1 signal 42 GATE1 DIGGND GATE1 This pin is from the Am9513A Counter 1 signal 43 OUT1 DIGGND OUTPUT1 This pin is from the Am9513A Counter 1 signal 44 SOURCE2 DIGGND SOURCE2 SOURCE5 This pin is from the Am9513A Counter 2 signal 45 GATE2 DIGGND GATE2 This pin is from the Am9513A Counter 2 signal 46 OUT2 DIGGND OUTPUT2 This pin is from the Am9...

Page 46: ...nnected to ACH 7 0 are routed to the positive input of the AT MIO 16D instrumentation amplifier and signals connected to ACH 15 8 are routed to the negative input of the AT MIO 16D instrumentation amplifier The following input ranges and maximum ratings apply to inputs ACH 15 0 Differential input range 10 V Common mode input range 7 V with respect to AT MIO 16D AGND Input range 12 V with respect t...

Page 47: ...ce or at the AT MIO 16D If you have a floating source you must use a ground referenced input connection at the AT MIO 16D If you have a grounded source you must use a nonreferenced input connection at the AT MIO 16D Types of Signal Sources When configuring the input mode of the AT MIO 16D and making signal connections you must first determine whether the signal source is floating or ground referen...

Page 48: ...s discuss the use of single ended and differential measurements and considerations for measuring both floating and ground referenced signal sources Table 2 10 summarizes the recommended input configuration for both types of signal sources Table 2 10 Recommended Input Configurations for Ground Referenced and Floating Signal Sources Type of Signal Recommended Input Configuration Ground Referenced no...

Page 49: ...ls to float within the common mode limits of the input instrumentation amplifier Differential Connections for Grounded Signal Sources Figure 2 27 shows how to connect a ground referenced signal source to an AT MIO 16D board configured for DIFF input Configuration instructions are included under the Analog Input Configuration section earlier in this chapter Ground Referenced Signal Source Common Mo...

Page 50: ...d under the Analog Input Configuration section earlier in this chapter Floating Signal Source Input Multiplexers Instrumentation Amplifier V m Measured Voltage V S I O Connector AT MIO 16 Board in DIFF Configuration 3 5 7 17 4 6 8 18 AI GND 1 2 100 kΩ Bias Current Return Paths ACH 8 15 ACH 0 7 19 AI SENSE Figure 2 28 Differential Input Connections for Floating Sources The 100 kΩ resistors shown in...

Page 51: ...eir common ground point is tied to the negative input of the instrumentation amplifier When the AT MIO 16D is configured for single ended input NRSE or RSE 16 analog input channels are available You can use single ended input connections when the following criteria are met by all input signals 1 Input signals are high level greater than 1 V 2 Leads connecting the signals to the AT MIO 16D are less...

Page 52: ...on amplifier and connect the signal local ground reference to the negative input of the AT MIO 16D instrumentation amplifier The ground point of the signal should therefore be connected to the AI SENSE pin Any potential difference between the AT MIO 16D ground and the signal ground appears as a common mode signal at both the positive and negative inputs of the instrumentation amplifier and this di...

Page 53: ...umentation amplifier can reject any voltage due to ground potential differences between the signal source and the AT MIO 16D In addition with differential input connections the instrumentation amplifier can reject common mode noise pickup in the leads connecting the signal sources to the AT MIO 16D The common mode input range of the AT MIO 16D instrumentation amplifier is defined as the magnitude ...

Page 54: ...nalog output signal pins Pins 20 and 21 are the DAC0 OUT and DAC1 OUT signal pins DAC0 OUT is the voltage output signal for analog output channel 0 DAC1 OUT is the voltage output signal for analog output channel 1 Pin 22 EXTREF is the external reference input for both analog output channels You must configure each analog output channel individually for external reference selection in order for the...

Page 55: ...h the DACs set at their maximum full scale digital value Digital I O Signal Connections Pins 24 through 32 of the MIO 16 I O connector are digital I O signal pins associated with the MIO 16 circuitry of the AT MIO 16D board Pins 25 27 29 and 31 are connected to the digital lines ADIO 3 0 for digital I O port A Pins 26 28 30 and 32 are connected to the digital lines BDIO 3 0 for digital I O port B ...

Page 56: ... V maximum IOH output source current logic high 2 6 mA maximum IOH output sink current logic low 24 mA maximum With these specifications each digital output line can drive 11 standard TTL loads and over 50 LS TTL loads The MIO 16 circuitry digital I O lines are pulled up through 100 kΩ resistors to 5 V Figure 2 32 depicts signal connections for three typical digital I O applications LED 5 V TTL Si...

Page 57: ...spare fuse as well Timing Connections Pins 36 through 50 of the MIO 16 I O connector are connections for timing I O signals Pins 36 through 40 carry signals used for data acquisition timing These signals are explained under the Data Acquisition Timing Connections section later in this chapter Pins 41 through 50 carry general purpose timing signals provided by the onboard Am9513A Counter Timer Thes...

Page 58: ... before going low The EXTCONV signal is one LS TTL load and is pulled up to 5 V through a 4 7 kΩ resistor Note EXTCONV is also driven by the output of Counter 3 of the Am9513A Counter Timer This counter is also referred to as the sample interval counter The output of Counter 3 must be disabled to a high impedance state if A D conversions are to be controlled by pulses applied to the EXTCONV pin If...

Page 59: ...ata acquisition operations In pretriggered mode data is acquired but no sample counting occurs until a rising edge is applied to the STOP TRIG pin This causes the sample counter to then start counting conversions The acquisition then completes when the sample counter decrements to zero This mode acquires data both before and after a hardware trigger is received Figure 2 36 shows the timing require...

Page 60: ... pulse signal at its OUT output pin or to toggle the OUT signal each time the counter reaches the terminal count For event counting program one of the counters to count rising or falling edges applied to any of the Am9513A SOURCE inputs The counter value can then be read to determine the number of edges that have occurred You can gate counter operation on and off during event counting Figure 2 37 ...

Page 61: ...SOURCE input while the gate is applied The frequency of the input signal is then the count value divided by the known gate period Figure 2 38 shows the connections for a frequency measurement application You could use a second counter to generate the gate signal in this application Signal Source 33 DIG GND Counter OUT SOURCE GATE 5 V 4 7 kΩ MIO 16 I O Connector AT MIO 16D Board Gate Source Figure ...

Page 62: ...cations referenced to DIG GND VOH output logic high voltage 2 4 V minimum VOL output logic low voltage 0 4 V maximum IOH output source current at VOH 200 µA maximum IOL output sink current at VOL 3 2 mA maximum Output current high impedance state 25 µA maximum Figure 2 39 shows the timing requirements for the GATE and SOURCE input signals and the timing specifications for the OUT output signals of...

Page 63: ...mum skew of 75 nsec between them The SOURCE signal shown in Figure 2 38 represents any of the signals applied at the SOURCE inputs GATE inputs or internal timebase clocks See Appendix E Am9513A Data Sheet for further details Specifications for signals at the GATE input are referenced to the signal at the SOURCE input or one of the Am9513A internally generated signals Figure 2 39 shows the GATE sig...

Page 64: ... Connections that exceed any of the maximum ratings of input or output signals on the AT MIO 16D may result in damage to the AT MIO 16D board and to the PC Maximum ratings for each signal are given in this chapter under the discussion of that signal National Instruments is not liable for any damages resulting from any such signal connections 1 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 ...

Page 65: ...This pin is referenced to DIG GND and can be used to power external digital circuitry Power rating 1 A at 5 V 10 Warning This 5 V power pin should not be directly connected to analog or digital ground or to any other voltage source on the AT MIO 16D or any other device Doing so can damage the AT MIO 16D and the PC AT National Instruments is not liable for damages resulting from such a connection A...

Page 66: ...gnals are used in the timing diagrams that follow Name Type Description STB input Strobe Input A low signal on this handshaking line loads data into the input latch IBF output Input Buffer Full A high signal on this handshaking line indicates that data has been loaded into the input latch This is an input acknowledge signal ACK input Acknowledge Input A low signal on this handshaking line indicate...

Page 67: ...ernal Read Signal This signal is the read signal generated from the control lines of the PC WR internal Write Signal This signal is the write signal generated from the control lines of the PC DATA bidirectional Data Lines at the Selected Port This signal indicates when the data on the data lines at a selected port is or should be available ...

Page 68: ...lowing are the timing specifications for an input transfer in Mode 1 DATA RD INTR IBF STB T1 T2 T4 T7 T6 T3 T5 Name Description Minimum Maximum T1 STB Pulse Width 500 T2 STB 0 to IBF 1 300 T3 Data before STB 1 0 T4 STB 1 to INTR 1 300 T5 Data after STB 1 180 T6 RD 0 to INTR 0 400 T7 RD 1 to IBF 0 300 All timing values are in nanoseconds ...

Page 69: ...Timing The following are the timing specifications for an output transfer in Mode 1 WR OBF INTR ACK DATA T1 T2 T3 T4 T5 T6 Name Description Minimum Maximum T1 WR 0 to INTR 0 450 T2 WR 1 to Output 350 T3 WR 1 to OBF 0 650 T4 ACK 0 to OBF 1 350 T5 ACK Pulse Width 300 T6 ACK 1 to INTR 1 350 All timing values are in nanoseconds ...

Page 70: ...tional transfers in Mode 2 T1 T6 T7 T3 T4 T10 T2 T5 T8 T9 WR OBF INTR ACK STB IBF RD DATA Name Description Minimum Maximum T1 WR 1 to OBF 0 650 T2 Data before STB 1 0 T3 STB Pulse Width 500 T4 STB 0 to IBF 1 300 T5 Data after STB 1 180 T6 ACK 0 to OBF 1 350 T7 ACK Pulse Width 300 T8 ACK 0 to Output 300 T9 ACK 1 to Output Float 20 250 T10 RD 1 to IBF 0 300 All timing values are in nanoseconds ...

Page 71: ... The following recommendations apply for all signal connections to the AT MIO 16D Physically separate AT MIO 16D signal lines from high current or high voltage lines These lines are capable of inducing currents in or voltages on the AT MIO 16D signal lines if they run in parallel paths at a close distance Reduce the magnetic coupling between lines by separating them by a reasonable distance if the...

Page 72: ... reference at the source The analog lines pins 1 through 23 should be routed separately from the digital lines pins 24 through 50 When using a cable shield use separate shields for the analog and digital halves of the cable Failure to do so will result in noise from switching digital signals coupling into the analog signals DIO 24 Cabling Considerations The DIO 24 circuitry of the AT MIO 16D can b...

Page 73: ...rt number 609 5041CE The standard ribbon cable 50 conductor 28 AWG stranded that can be used with these connectors is as follows Electronic Products Division 3M part number 3365 50 T B Ansley Corporation part number 171 50 If you plan to use the DIO section of the AT MIO 16D for a communications application you may need shielded cables to meet FCC requirements The DIO section I O bracket has been ...

Page 74: ...ing up the AT MIO 16D MIO 16 Functional Overview The block diagram in Figure 3 1 is a functional overview of the MIO 16 circuitry of the AT MIO 16D board PC AT I O Channel PC A T I O Channel Interface Digital I O Analog Input Internal Data Bus Internal Control Bus Timing I O Data Acquisition Timing RTSI Bus Interface RTSI Bus Analog Output I O Connector Figure 3 1 AT MIO 16D MIO 16 Circuitry Block...

Page 75: ...circuitry The internal data and control buses interconnect the components The theory of operation of each of these components is explained in the remainder of this chapter PC AT I O Channel Interface Circuitry The AT MIO 16D board is a full size 16 bit PC AT I O channel adapter The PC AT I O channel consists of a 24 bit address bus a 16 bit data bus a direct memory access DMA arbitration bus inter...

Page 76: ...multiple function circuitry The PC AT I O channel has 24 address lines the AT MIO 16D uses 10 of these lines to decode the board address Therefore the board address range is hex 000 to 3FF SA5 through SA9 are used to generate the board enable signal SA0 through SA4 are used to select onboard registers These address lines are latched by the address latches at the beginning of an I O transfer The la...

Page 77: ... of the Am9513A Counter Timer When either an OVERFLOW or an OVERRUN error occurs Each one of these interrupts is individually enabled and cleared See Chapter 4 Programming for more information about programming with interrupts The DMA control circuitry generates DMA requests whenever an A D measurement is available from the A D FIFO if the DMA transfer is enabled The DMA circuitry supports full PC...

Page 78: ...0 Counter Timer Signals MUX CTR CLK 4 4 Data MUXCTR WR 6 Data MUXGAIN WR CONV AVAIL A D RD 12 Data 12 A D Data Sign Exten sion A D RD 4 Data Ð 10 V 20 V Selection W1 MUX0OUT MUX0EN MUX1OUT MUX1EN AI SENSE SCAN CLK STOP TRIG EXT CONV START TRIG S H Ampli fier Unipolar Bipolar Selection W4 PC AT I O Channel I O Connector Analog to Digital Converter A D FIFO Mux Counter Multi Plexer Gain Memory Data ...

Page 79: ...ifier The instrumentation amplifier fulfills two purposes on the AT MIO 16D board It converts a differential input signal into a single ended signal with respect to the AT MIO 16D ground for a minimum input common mode rejection ratio of 85 dB This conversion allows the input analog signal to be extracted from any common mode voltage or noise before being sampled and converted The instrumentation ...

Page 80: ...the sample interval to catch up with the hardware If more than 512 values are stored in the A D FIFO without the A D FIFO being read from an error condition called A D FIFO overflow occurs and A D conversion information is lost The A D FIFO generates a signal that indicates when it contains A D conversion data You can read the state of this signal from the AT MIO 16D Status Register You can use th...

Page 81: ...can also use any of the external clock inputs to the Am9513A as a timebase During data acquisition the sample interval counts down at the rate given by the internal timebase or external clock Each time the sample interval timer reaches zero it generates a pulse and reloads with the programmed sample interval count This operation continues until data acquisition halts Sample Counter The onboard sam...

Page 82: ...d with any 4 bit value to point to any mux gain memory location With this counter scanning can start at any location in the mux gain memory The SCAN CLK signal is generated from the sample interval counter This signal pulses once at the beginning of each A D conversion and is supplied at the I O connector During multiple channel scanning the multiplexer counter is incremented repeatedly thereby se...

Page 83: ...500 20 ksamples sec Analog Output Circuitry The AT MIO 16D provides two channels of 12 bit digital to analog D A output Each analog output channel provides options such as unipolar or bipolar output and internal or external reference voltage selection Figure 3 4 shows a block diagram of the analog output circuitry I O Connector REF Selection W3 10 V From A D REF Internal REF EXTREF W2 W7 REF DAC1 ...

Page 84: ...ord of zero One LSB is the voltage increment corresponding to an LSB change in the digital code word For unipolar output 1 LSB Vref 4 096 For bipolar output 1 LSB Vref 2 048 Analog Output Data Coding The voltage reference source for each DAC is jumper selectable and can be supplied either externally at the EXTREF input or internally The external reference can be either a DC or an AC signal If an A...

Page 85: ... digital output lines BDIO 3 0 Reading the Digital Input Register returns the state of the digital I O lines Digital I O lines ADIO 3 0 are connected to bits 3 0 of the Digital Input Register Digital I O lines BDIO 3 0 are connected to bits 7 4 of the Digital Input Register When a port is enabled the Digital Input Register serves as a read back register returning the digital output value of the po...

Page 86: ...E2 SOURCE2 OUT2 GATE1 SOURCE1 OUT1 FOUT I O Connector STOP TRIG Flip Flop GATE4 PC AT I O Channel 10 MHz MYCLK Figure 3 6 Timing I O Circuitry Block Diagram The Am9513A contains five independent 16 bit counter timers a 4 bit frequency output channel and five internally generated timebases The five counter timers can be programmed to operate in several useful timing modes The programming and operat...

Page 87: ...tes timing signals at its OUT output pin The OUT output pin can also be set to a high impedance state or a grounded output state The counters generate two types of output signals during counter operation terminal count pulse output and terminal count toggle output Terminal count is often referred to as TC A counter reaches TC when it counts up or down and rolls over In many counter applications th...

Page 88: ... provided to the data acquisition timing circuitry This allows Counter 1 to be used to divide the SCAN CLK signal for generating the MUX CTR CLK signal see the Data Acquisition Timing Circuitry section earlier in this chapter Counter 2 is sometimes used by the data acquisition timing circuitry to assign a time interval to each cycle through the scan sequence programmed in the mux gain memory This ...

Page 89: ...n the board The RTSI switch can drive any of the signals at pins A 6 0 onto any one or more of the seven RTSI bus trigger lines and can drive any of the seven trigger line signals onto any one or more of the pins A 6 0 This capability provides a completely flexible signal interconnection scheme for any AT Series board sharing the RTSI bus The RTSI switch is programmed via its select and data input...

Page 90: ...sed by the DIO 24 circuitry of the AT MIO 16D is selected by the onboard jumper W13 Another onboard jumper W14 is used to enable interrupts from the DIO 24 circuitry The setting for W14 selects PC2 PC4 or PC6 as the active low interrupt enable signal Selecting N C for W14 disables interrupts from the DIO 24 circuitry When the onboard jumpers are set to enable interrupts the 82C55A can be programme...

Page 91: ...it ports are divided into two groups Group A and Group B two groups of twelve signals One 8 bit configuration or control word determines the mode of operation for each group The Group A control bits configure Port A A0 through A7 and the upper 4 bits nibble of Port C C4 through C7 The Group B control bits configure Port B B0 through B7 and the lower nibble of Port C C0 through C3 Modes 1 and 2 use...

Page 92: ...it ports are used for control and status of the 8 bit data ports Interrupt generation and enable and or disable functions are available Mode 2 This mode can be used for communication over a bidirectional 8 bit bus Handshaking signals are used in a manner similar to Mode 1 Interrupt generation and enable and or disable functions are also available Other features of this mode include the following U...

Page 93: ...egister name the register offset address the size of the register in bits and the type of the register read only write only or read and write The actual register address is computed by adding the individual offset address to the board base address Table 4 1 AT MIO 16D Register Map Register Name OffSet Address Hex Type Size Configuration and Status Register Group Command Register 1 0 Write only 16 ...

Page 94: ...Switch Shift Register 1E Write only 8 bit RTSI Switch Strobe Register 1F Write only 8 bit DIO 24 Register Group DIO 24 PORTA Register 0x00 Read and write 8 bit DIO 24 PORTB Register 0x01 Read and write 8 bit DIO 24 PORTC Register 0x02 Read and write 8 bit DIO 24 CNFG Register 0x03 Write only 8 bit Register Sizes The IBM PC AT and compatibles support two different transfer sizes for read and write ...

Page 95: ...ach bit The register bit map shows a diagram of the register with the MSB bit 15 for a 16 bit register bit 7 for an 8 bit register shown on the left and the LSB bit 0 shown on the right A square is used to represent each bit Each bit is labeled with a name inside its square An asterisk after the bit name indicates that the bit is inverted negative logic In many of the registers several bits are la...

Page 96: ...writing to the A D Clear Register If DAQSTOPINTEN is cleared no data acquisition termination interrupts are generated 8 TCINTEN This bit enables and disables generation of an interrupt when a DMA terminal count pulse is received from the DMA controller in the PC AT If TCINTEN is set an interrupt request is generated when the DMA controller transfer count register decrements from 0 to FFFF hex The ...

Page 97: ...he mux counter clock controls sequencing of the mux gain memory If SCANDIV is set the mux counter clock is controlled by Counter 1 of the Am9513A Counter Timer If SCANDIV is cleared the mux counter clock generates one pulse per conversion 1 16 32CNT This bit selects the count resolution for the number of A D conversions to be performed in a data acquisition operation If 16 32CNT is cleared a 16 bi...

Page 98: ...acquisition termination interrupt If DAQSTOPINT is set and either OVERFLOW or OVERRUN is set the current interrupt is due to an error condition If DAQSTOPINT is set and neither OVERFLOW nor OVERRUN is set the current interrupt is due to the completion of the data acquisition operation DAQSTOPINT is cleared by writing to the A D Clear Register 13 CONVAVAIL This bit reflects the state of the A D FIF...

Page 99: ...may occur if the data acquisition sample interval is too small sample rate is too high If OVERRUN is set one or more conversions were skipped If OVERRUN is cleared no overrun condition has occurred If OVERRUN occurs during a data acquisition operation the data acquisition is terminated immediately This bit can be reset by writing to the A D Clear Register 7 6 GAIN 1 0 These two bits show the curre...

Page 100: ... DIFF mode multiplexer 0 is always enabled The output of multiplexer 0 is always connected to the positive input of the instrumentation amplifier 2 0 MA 2 0 MA 2 0 give the low order three bits of the analog input channel address MA stands for multiplexer address These three bits in conjunction with the MUX1EN and MUX0EN bits indicate which analog input channel is currently selected In single ende...

Page 101: ...ables and disables driving of the 4 bit MIO 16 digital output port 0 by the MIO 16 Digital Output Register If DOUTEN0 is set the MIO 16 Digital Output Register drives the digital lines If DOUTEN0 is cleared the MIO 16 Digital Output Register drivers are set to a high impedance state thereby allowing an external device to drive the digital lines 7 INTEN This bit enables and disables any interrupt g...

Page 102: ...eceived from one of the RTSI bus trigger lines and driven onto the STOP TRIG line If A4RCV is set pin A4 of the RTSI switch drives the STOP TRIG signal If A4RCV is cleared the STOP TRIG signal is not driven by the RTSI switch 2 A4 DRV This bit controls a driver that allows the OUT5 signal to drive pin A4 of the RTSI switch This driver allows the OUT5 signal to be driven onto one of the RTSI bus tr...

Page 103: ...Group The Event Strobe Register Group consists of four registers that when written to cause the occurrence of certain events on the AT MIO 16D board such as clearing flags and starting A D conversions Descriptions of the four registers making up the Event Strobe Register Group are given on the following pages ...

Page 104: ...active low signal on the EXTCONV signal The EXTCONV signal is connected to pin 40 on the MIO 16 I O connector to OUT3 of the Am9513A and to the A0 pin of the RTSI bus switch If EXTCONV is driven low by any one of these sources it prevents the Start Convert Register from initiating an A D conversion If the Start Convert Register is to initiate A D conversions the OUT3 signal should be initialized t...

Page 105: ... bits used Note Multiple A D conversion data acquisition operations can be initiated in one of two ways by writing to the Start DAQ Register or by detecting an active low signal on the START TRIG signal The START TRIG signal is connected to pin 38 on the MIO 16 I O connector and to the A6 pin of the RTSI bus switch If START TRIG is driven low by either of these sources it prevents the Start DAQ Re...

Page 106: ...fic events occur Any data acquisition operation in progress is canceled The A D FIFO is emptied The overrun flag is cleared The overflow flag is cleared Any pending CONV interrupt is cleared Any pending DAQSTOP interrupt is cleared Any pending DMATCINT interrupt is cleared Any pending DMA request is cleared Address Base address C hex Type Write only Word Size 16 bit Bit Map Not applicable no bits ...

Page 107: ...ve low approximately 200 nsec strobe pulse at the EXTSTROBE output at the MIO 16 I O connector This pulse may be useful for several applications including generating external general purpose triggers and latching data into external devices from the digital output port for example Address Base address E hex Type Write only Word Size 16 bit Bit Map Not applicable no bits used ...

Page 108: ...updated immediately or each time an active low pulse is detected on the OUT2 bit of the Am9513A Counter Timer The update method is selected with the LDAC bit in Command Register 2 The third register in the Analog Output Register Group is the INT2CLR Register The AT MIO 16D can be programmed to interrupt when it detects a rising edge signal on the OUT2 pin of the Am9513A Counter Timer This interrup...

Page 109: ...Command Register 2 Address Base address 10 hex Type Write only Word Size 16 bit Bit Map 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X D11 D10 D9 D6 D7 D6 D5 D4 D3 D2 D1 D0 MSB LSB Bit Name Description 15 12 X Don t care bits 11 0 D 11 0 These 12 bits are loaded into the DAC and update the voltage generated by the analog output channel in one of two ways immediately or upon an OUT2 pulse See the Pr...

Page 110: ...mmand Register 2 Address Base address 12 hex Type Write only Word Size 16 bit Bit Map 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X D11 D10 D9 D6 D7 D6 D5 D4 D3 D2 D1 D0 MSB LSB Bit Name Description 15 12 X Don t care bits 11 0 D 11 0 These twelve bits are loaded into the DAC and update the voltage generated by the analog output channel in one of two ways immediately or upon an OUT2 pulse See the ...

Page 111: ...s Corporation 4 19 AT MIO 16D User Manual INT2CLR Register Writing to INT2CLR clears the interrupt request asserted when an OUT2 pulse is detected Address Base address 14 hex Type Write only Word Size 16 bit Bit Map Not applicable no bits used ...

Page 112: ... Register generates addresses for the mux gain memory The Mux Gain Register controls the current multiplexer and gain settings and allows the mux gain memory to be written to Reading the A D FIFO Register returns stored A D conversion results Writing to the DMA TC INT Clear Register clears the interrupt request generated by a DMA terminal count pulse Bit descriptions for the registers making up th...

Page 113: ...lexer counter by writing to the Mux Counter Register The multiplexer counter generates addresses for the mux gain memory therefore writing to the Mux Counter Register allows a specific location in the mux gain memory to be addressed The mux gain memory contains a sequence of multiplexer addresses and gain settings For example writing 0004 hex to the Mux Counter Register loads the multiplexer count...

Page 114: ... bit Bit Map 15 14 13 12 11 10 9 8 X X X X X X X X 7 6 5 4 3 2 1 0 GAIN1 GAIN0 X LASTONE MA3 MA2 MA1 MA0 Bit Name Description 15 8 X Don t care bits 7 6 GAIN 1 0 This 2 bit field controls the gain setting of the input instrumentation amplifier The actual amplifier gains depend on the type of AT MIO 16D board The following gains can be selected on the AT MIO 16DH board GAIN 1 0 Actual Gain 00 1 01 ...

Page 115: ... selected for either mode is given below MA 3 0 Selected Analog Input Channels Single Ended DIFF 0000 0 0 8 0001 1 1 9 0010 2 2 10 0011 3 3 11 0100 4 4 12 0101 5 5 13 0110 6 6 14 0111 7 7 15 1000 8 0 8 1001 9 1 9 1010 10 2 10 1011 11 3 11 1100 12 4 12 1101 13 5 13 1110 14 6 14 1111 15 7 15 Writing to the Mux Gain Register updates the current analog input channel selection and the current gain sett...

Page 116: ...es both positive and negative numbers The binary format used is selected by the 2SCADC bit in Command Register 1 The bit pattern returned for either format is given below Address Base address 16 hex Type Read only Word Size 16 bit Bit Map Straight binary mode 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MSB LSB Bit Name Description 15 0 D 15 0 These bits are ...

Page 117: ...MIO 16D User Manual DMA TC INT Clear Register Writing to the DMA TC INT Clear Register clears the interrupt request asserted when a DMA terminal count pulse is detected Address Base address 16 hex Type Write only Word Size 16 bit Bit Map Not applicable no bits used ...

Page 118: ... general purpose timing for the user The Am9513A registers described here are the Am9513A Data Register the Am9513A Command Register and the Am9513A Status Register The Am9513A contains 18 additional internal registers These internal registers are accessed through the Am9513A Data Register A detailed register description of all Am9513A registers is included in Appendix E Am9513A Data Sheet Bit des...

Page 119: ...rs for Counters 1 2 3 4 and 5 Counter Hold Registers for Counters 1 2 3 4 and 5 The Master Mode Register The Compare Registers for Counters 1 and 2 All these registers are 16 bit registers Bit descriptions for each of these registers are included in Appendix E Am9513A Data Sheet Address Base address 18 hex Type Read and write Word Size 16 bit Bit Map 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 D15 D14 D...

Page 120: ... through the Am9513A Data Register Address Base address 1A hex Type Write only Word Size 16 bit Bit Map 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 C7 C6 C5 C4 C3 C2 C1 C0 Bit Name Description 15 8 1 These bits must always be set when writing to the Am9513A Command Register 7 0 C 7 0 These eight bits are loaded into the Am9513A Command Register See Appendix E Am9513A Data Sheet for the d...

Page 121: ... 8 X X X X X X X X 7 6 5 4 3 2 1 0 X X OUT5 OUT4 OUT3 OUT2 OUT1 BYTEPTR Bit Name Description 15 6 X Don t care bits 5 1 OUT 5 1 Each of these five bits returns the logic state of the associated counter output pin For example if OUT4 is set then the output pin of Counter 4 is at a logic high state 0 BYTEPTR This bit represents the state of the Am9513A Byte Pointer Flip Flop This bit has no signific...

Page 122: ...MIO 16D digital I O lines The MIO 16 Digital Input Register returns the digital state of the eight digital I O lines A pattern written to the MIO 16 Digital Output Register is driven onto the digital I O lines when the digital output drivers are enabled see the description for Command Register 2 Bit descriptions for the registers making up the MIO 16 Digital I O Register Group are given on the fol...

Page 123: ...ctor Address Base address 1C hex Type Read only Word Size 16 bit Bit Map 15 14 13 12 11 10 9 8 X X X X X X X X 7 6 5 4 3 2 1 0 BDIO3 BDIO2 BDIO1 BDIO0 ADIO3 ADIO2 ADIO1 ADIO0 Bit Name Description 15 8 X Don t care bits 7 4 BDIO 3 0 These four bits represent the logic state of the digital lines BDIO 3 0 from the MIO 16 I O connector 3 0 ADIO 3 0 These four bits represent the logic state of the digi...

Page 124: ...I O connector Address Base address 1C hex Type Write only Word Size 16 bit Bit Map 15 14 13 12 11 10 9 8 X X X X X X X X 7 6 5 4 3 2 1 0 BDIO3 BDIO2 BDIO1 BDIO0 ADIO3 ADIO2 ADIO1 ADIO0 Bit Name Description 15 8 X Don t care bits 7 4 BDIO 3 0 These four bits control the digital lines BDIO 3 0 at the MIO 16 I O connector The bit DOUT1EN in Command Register 2 must be set for BDO 3 0 to be driven onto...

Page 125: ...eral AT MIO 16D signal lines The RTSI switch is programmed by shifting a 56 bit routing pattern into the RTSI switch and then loading the internal RTSI Switch Control Register The routing pattern is shifted into the RTSI switch by writing one bit at a time to the RTSI Switch Shift Register The RTSI Switch Control Register is then loaded by writing to the RTSI Switch Strobe Register Bit description...

Page 126: ... bit register and must be written to 56 times to shift the 56 bits into the internal register Address Base address 1E hex Type Write only Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 X X X X X X X RSI Bit Name Description 7 1 X Don t care bits 0 RSI The name of this bit stands for RTSI switch serial input This bit is the serial input to the RTSI switch Each time the RTSI Switch Shift Register is writte...

Page 127: ...er to load the contents of the RTSI Switch Shift Register into the RTSI Switch Control Register thereby updating the RTSI switch routing pattern The RTSI Switch Strobe Register is written to after shifting the 56 bit routing pattern into the RTSI Switch Shift Register Address Base address 1F hex Type Write only Word Size 8 bit Bit Map Not applicable no bits used ...

Page 128: ...I O pins These pins represent the three 8 bit I O ports A B and C of the 82C55A These ports can be programmed as two groups of 12 signals or as three individual 8 bit ports The DIO 24 Register Group contains the following four registers DIO 24 PORTA Register DIO 24 PORTB Register DIO 24 PORTC Register and DIO 24 CNFG Register Bit descriptions for the registers in the DIO 24 Register Group are give...

Page 129: ...s configured for output the DIO 24 PORTA Register can be written to in order to control the eight digital I O lines constituting Port A See DIO 24 Circuitry Programming Considerations later in this chapter for information on how to configure Port A for input or output Address Base address 0x00 hex Type Read and write Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Bit Name Descript...

Page 130: ...t B is configured for output the DIO 24 PORTB Register can be written to in order to control the eight digital I O lines constituting Port B See 82C55A Programming Considerations later in this chapter for information on how to configure Port B for input or output Address Base address 0x01 hex Type Read and write Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Bit Name Description 7...

Page 131: ...aking latched mode If either Port A or Port B is configured for latched I O some of the bits in Port C are used for handshaking signals See DIO 24 Circuitry Programming Considerations later in this chapter for a description of the individual bits in the DIO 24 PORTC Register Address Base address 0x02 hex Type Read and write Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Bit Name D...

Page 132: ...selecting simple mode basic I O or handshaking mode strobed I O for transfers See DIO 24 Circuitry Programming Considerations later in this chapter for a description of the individual bits in the DIO 24 CNFG Register Address Base address 0x03 hex Type Write only Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 CW7 CW6 CW5 CW4 CW3 CW2 CW1 CW0 Bit Name Description 7 0 CW 7 0 These eight bits are written to o...

Page 133: ...riting to these registers simultaneously affects all register bits You cannot read these registers to determine which bits have been set or cleared in the past therefore you should maintain a software copy of the write only registers This software copy can then be read to determine the status of the write only registers To change the state of a single bit without disturbing the remaining bits set ...

Page 134: ...ta Register to store the counter mode value c Write FF08 ctr to the Am9513A Command Register to select the Counter Load Register d Write 3 to the Am9513A Data Register to store an inactive count value in the Counter Load Register 6 Load all counters with their Counter Load Register values by writing FF5F to the Am9513A Command Register After this sequence of writes the Am9513A Counter Timer is in ...

Page 135: ...g input channel and gain The analog input channel and gain are selected by writing to the Mux Gain Register Bits 7 and 6 control the gain and bits 3 through 0 select the analog input channel See the Mux Gain Register bit description earlier in this chapter for gain and analog input channel bit patterns Set up the bits as given in the Mux Gain Register bit description and write to the Mux Gain Regi...

Page 136: ...the A D FIFO before the A D FIFO Register is read If this condition occurs the OVERFLOW bit is set in the Status Register to alert you that one or more A D conversion results have been lost because of FIFO overflow Writing to the A D Clear Register clears this error flag and empties the A D FIFO A D FIFO Output Binary Formats The A D conversion result can be returned from the A D FIFO as a two s c...

Page 137: ... Conversion Values Input Voltage A D Conversion Result Gain 1 Range 5 to 5 V Range 10 to 10 V Decimal Hex Decimal Hex 10 0 2 048 F800 5 0 2 048 F800 1 024 FC00 2 5 1 024 FC00 512 FE00 0 0 0000 0 0000 2 5 1 024 0400 512 0200 4 9976 2 047 07FF 5 0 1 024 0400 9 9951 2 047 07FF To convert from the A D FIFO value to the input voltage measured use the appropriate formula as follows 5V Range A D Count 5 ...

Page 138: ...ro the conversion sequence terminates Thus all acquired data was received after the trigger or software start In pretrigger operation the sample counter does not decrement until a trigger signal is applied to the STOP TRIG input When the conversion sequence terminates some of the acquired data has been received before the trigger signal and some has been received after this signal The most commonl...

Page 139: ...is the time between successive A D conversions N can be between 2 and 65 536 One count is equal to the period of the timebase clock used by the counter The following clocks are available internal to the Am9513A 1 MHz 100 kHz 10 kHz 1 kHz and 100 Hz In addition the sample interval timer can use signals connected to any of the Am9513A SOURCE input pins To program the sample interval counter use the ...

Page 140: ... 2 through 65 536 To program the sample counter for sample counts up to 65 536 use the following programming sequence The minimum permitted sample count is two All writes are 16 bit operations All values given are hexadecimal a Write FF04 to the Am9513A Command Register to select the Counter 4 Mode Register b Write 1025 to the Am9513A Data Register to store the Counter 4 mode value c Write FF0C to...

Page 141: ...ct the Counter 5 Mode Register i Write 25 to the Am9513A Data Register to store the Counter 5 mode value j Write FF0D to the Am9513A Command Register to select the Counter 5 Load Register k Take the most significant 16 bits of the sample count and do the following If the least significant 16 bits of the sample count are all 0 or all 0 except for a 1 in the least significant bit write the most sign...

Page 142: ... Once the data acquisition operation is started by application of a trigger the operation must be serviced by reading the A D FIFO Register every time an A D conversion result becomes available To do this perform the following sequence until the desired number of conversion results have been read a Read the Status Register 16 bit read b If the CONVAVAIL bit is set bit 13 read the A D FIFO Register...

Page 143: ...interval counter starts counting when a rising edge signal is applied to the STOP TRIG input on the AT MIO 16D I O connector You program the sample counter for active high level gating on Gate 4 The data acquisition operation is initiated by writing to the Start DAQ Register or by a pulse on the START TRIG input The sample count register does not begin counting samples until a rising edge is appli...

Page 144: ...SOURCE5 input as clock counts the rising edge of the signal 6 MHz maximum c Write FF0B to the Am9513A Command Register to select the Counter 3 Load Register d Write 2 to the Am9513A Data Register to store the Counter 3 load value e Write FF44 to the Am9513A Command Register to load Counter 3 f Write FFF3 to the Am9513A Command Register to step Counter 3 down to one g Write the desired sample inter...

Page 145: ... the sample counter After you complete this programming sequence Counter 4 is configured to count A D conversion pulses generated by Counter 3 and turns off the data acquisition operation when Counter 4 decrements to zero Counter 4 begins counting A D conversion pulses when a rising edge signal is received on the STOP TRIG input A D conversion data stored before receipt of the STOP TRIG signal are...

Page 146: ...very time Counter 4 reaches zero The data acquisition operation is terminated when both Counters 4 and 5 reach zero Counters 4 and 5 begin counting A D conversion pulses when a rising edge signal is received on the STOP TRIG input A D conversion data stored before receipt of the STOP TRIG signal are pretrigger samples 4 Clear the A D circuitry Before you start the data acquisition operation the A ...

Page 147: ...ep up with the A D conversion rate When an overflow occurs at least one A D conversion result is lost An overflow condition has occurred if the OVERFLOW bit in the Status Register is set An overrun condition occurs if an A D conversion is initiated before the previous conversion is finished This condition may result in one or more missing A D conversions This condition occurs if the sample interva...

Page 148: ...equence until the desired number of conversion results have been read a Read the Status Register 16 bit read b If the CONVAVAIL bit is set bit 13 read the A D FIFO Register to obtain the result Interrupts or DMA can also be used to service the data acquisition operation These topics are discussed later in this chapter Two error conditions may occur during a data acquisition operation an overflow e...

Page 149: ...f the scan sequence Continuous channel scanning can be thought of as a round robin approach to scanning multiple channels Interval channel scanning gives each scan sequence a programmed time interval called a scan interval Each cycle of the scan sequence begins at the time interval specified by the scan interval If the sample interval counter is programmed for the minimum time required to complete...

Page 150: ...ory perform the following write operations where X is the number of entries in the scan sequence For i 0 to X 1 do the following a Write i to the Mux Counter Register to select the mux gain memory location b Write the desired analog channel selection and gain setting to the Mux Gain Register to load the mux gain memory at location i c If i X 1 also set the LASTONE bit when writing to the Mux Gain ...

Page 151: ...as a multiple of the number of entries in the mux gain memory If the desired sample count is 65 536 or less only Counter 4 needs to be used making Counter 5 available for general purpose timing applications If the desired sample count is greater than 65 536 both Counters 4 and 5 must be used Sample Counts 2 through 65 536 To program the sample counter for sample counts up to 65 536 use the followi...

Page 152: ...3A Data Register to store 0 into the Load Register for Counter 4 reloading g Write FF28 to the Am9513A Command Register to arm Counter 4 h Write FF05 to the Am9513A Command Register to select the Counter 5 Mode Register i Write 25 to the Am9513A Data Register to store the Counter 5 mode value j Write FF0D to the Am9513A Command Register to select the Counter 5 Load Register k Take the most signifi...

Page 153: ...AT MIO 16D I O connector See the Data Acquisition Timing Connections section in Chapter 2 Configuration and Installation for START TRIG signal specifications Once the trigger is applied Counter 3 generates pulses initiating A D conversions once every sample interval until the sample counter reaches zero 7 Service the data acquisition operation Once the data acquisition operation is started by appl...

Page 154: ...o Simultaneous Programming scanned multiple A D conversions with a scan interval involves the following programming steps 1 Set up the analog channel and gain selection sequence 2 Program the sample interval counter 3 Program the sample counter 4 Program the scan interval counter 5 Clear the A D circuitry and reset the multiplexer counter 6 Enable the scanning data acquisition operation 7 Apply a ...

Page 155: ...mory perform the following write operations where X is the number of entries in the scan sequence For i 0 to X 1 do the following a Write i to the Mux Counter Register to select the mux gain memory location b Write the desired analog channel selection and gain setting to the Mux Gain Register to load the mux gain memory at location i c If i X 1 also set the LASTONE bit when writing to the Mux Gain...

Page 156: ...s a multiple of the number of entries in the mux gain memory If the desired sample count is 65 536 or less only Counter 4 needs to be used making Counter 5 available for general purpose timing applications If the desired sample count is greater than 65 536 both Counters 4 and 5 must be used Sample Counts 2 through 65 536 To program the sample counter for sample counts up to 65 536 use the followin...

Page 157: ...ta Register to store 0 into the Load Register for Counter 4 reloading g Write FF28 to the Am9513A Command Register to arm Counter 4 h Write FF05 to the Am9513A Command Register to select the Counter 5 Mode Register i Write 25 to the Am9513A Data Register to store the Counter 5 mode value j Write FF0D to the Am9513A Command Register to select the Counter 5 Load Register k Take the most significant ...

Page 158: ...lects 1 MHz clock 8C25 Selects 100 kHz clock 8D25 Selects 10 kHz clock 8E25 Selects 1 kHz clock 8F25 Selects 100 Hz clock 8525 Selects signal at SOURCE5 input as clock counts the rising edge of the signal 6 MHz maximum c Write FF0A to the Am9513A Command Register to select the Counter 2 Load Register d Write 2 to the Am9513A Data Register to store the Counter 2 load value e Write FF42 to the Am951...

Page 159: ...ta acquisition operation through software write 0 to the Start DAQ Register To initiate the data acquisition operation through hardware apply an active low pulse to the START TRIG pin on the AT MIO 16D I O connector See the Data Acquisition Timing Connections section in Chapter 2 Configuration and Installation for START TRIG signal specifications Once the trigger is applied Counter 3 generates pul...

Page 160: ...on because signals must settle each time channels are switched See Table 4 4 for the maximum recommended multiple channel data acquisition rates The rates in Table 4 4 refer to typical settling accuracies of 0 5 LSBs of the final value Table 4 4 Multiple Channel Data Acquisition Rates Gain Data Acquisition Rate 1 2 4 8 100 ksamples sec 10 100 ksamples sec 100 70 ksamples sec 500 20 ksamples sec Bo...

Page 161: ... FF42 to the Am9513A Command Register to load Counter 2 7 Write FF42 to the Am9513A Command Register a second time to load Counter 2 again to guarantee that Counter 2 is not left in a terminal count state Resetting Counter 3 To reset Counter 3 use the following programming sequence All writes are 16 bit operations All values given are hexadecimal 1 Write FFC4 to the Am9513A Command Register to dis...

Page 162: ...4 7 Write FF48 to the Am9513A Command Register a second time to load Counter 4 again to guarantee that Counter 4 is not left in a terminal count state Resetting Counter 5 To reset Counter 5 use the following programming sequence All writes are 16 bit operations All values given are hexadecimal 1 Write FFD0 to the Am9513A Command Register to disarm Counter 5 2 Write FF05 to the Am9513A Command Regi...

Page 163: ...alog output channel This configuration is determined by configuration jumpers on the AT MIO 16D board In bipolar mode configuration jumpers also determine if the digital code written to the DACs is in straight binary form or in a two s complement form The factory default is the bipolar configuration in two s complement mode See the Analog Input Configuration section in Chapter 2 Configuration and ...

Page 164: ...put channel The digital code in the above formula is a decimal value ranging from 2 048 to 2 047 Table 4 6 Analog Output Voltage Versus Digital Code Bipolar Mode Digital Code Straight Binary Two s Complement Voltage Output Decimal Hex Decimal Hex Vref 10 V Vout 0 1 1 024 2 047 2 048 2 049 3 072 4 095 0 1 0400 07FF 0800 0801 0C00 0FFF 2 048 2 047 1 024 1 0 1 1 024 2 047 F800 F801 FC00 FFFF 0 1 0400...

Page 165: ...so available as a timing signal source These applications and a general description of the Am9513A Counter Timer are included in the Data Acquisition Timing Connections section in Chapter 2 Configuration and Installation The Timing I O Circuitry section in Chapter 3 Theory of Operation explains how the Am9513A is used on the AT MIO 16D board Initialization of the Am9513A as required by the AT MIO ...

Page 166: ... MIO 16D I O connector As shown in Table 4 8 two AT MIO 16D signals are connected to pin A2 and two signals are connected to pin A4 The routing of these signals is further controlled by the bits A4DRV A4RCV A2DRV and A2RCV in Command Register 2 To drive the RTSI switch pin A2 with the signal OUT2 set the A2DRV bit in Command Register 2 Otherwise clear the A2DRV bit To drive the signal GATE1 from p...

Page 167: ...ugh B0 are the 4 bit control fields for each RTSI switch pin of the same name The 4 bit control field for pin A0 is shown in Figure 4 1 The bits labeled S2 through S0 are the signal source selection bits for the pin One of seven source signals can be selected Pins A6 through A0 can select any of the pins B6 through B0 as signal sources Pins B6 through B0 select any of the pins A6 through A0 as sig...

Page 168: ...6D can be programmed so that the A D FIFO generates a DMA request signal every time one or more A D conversion values are stored in the A D FIFO There are two DMA modes single channel transfer and dual channel transfer In single channel mode one DMA channel is used The DMA channel is selected by the onboard jumper To program the single channel DMA operation perform the following steps after the ci...

Page 169: ...an interrupt occurs from the AT MIO 16D board and if the CONVAVAIL bit in the Status Register is set then a conversion interrupt has occurred Reading from the A D FIFO Register clears this interrupt condition Writing to the A D Clear Register also clears the conversion interrupt To use the DMA terminal count interrupt set the DMAEN and TCINTEN bits in Command Register 1 and the INTEN bit in Comman...

Page 170: ...roups of 12 signals or as three individual 8 bit ports This section includes programming information for the DIO 24 circuitry along with program examples written in C The three 8 bit ports of the 82C55A are divided into two groups Group A and Group B two groups of 12 signals One 8 bit configuration or control word determines the mode of operation for each group The Group A control bits configure P...

Page 171: ...rt B 1 input 0 output Mode Selection 0 Mode 0 1 Mode 1 Group A Group B Port C high nibble 1 input 0 output D7 X X X D3 D2 D1 D0 Control Word Flag 0 Bit Set Reset Unused Bit Set Reset 1 Set 0 Reset Bit Select 000 001 010 111 Figure 4 2 Control Word Formats Table 4 8 shows the control words for setting or resetting each bit in Port C Notice that bit 7 of the control word is cleared when programming ...

Page 172: ...trobed I O Mode 2 Bidirectional bus The 82C55A also has a single bit set reset feature for Port C The 8 bit control word also programs this function For additional information refer to Appendix F Oki MSM82C55A Data Sheet Mode 0 Basic I O Mode 0 can be used for simple input and output operations for each of the ports No handshaking is required data is simply written to or read from a selected port ...

Page 173: ... 10 10010010 Input Output Input Output 11 10010011 Input Output Input Input 12 10011000 Input Input Output Output 13 10011001 Input Input Output Input 14 10011010 Input Input Input Output 15 10011011 Input Input Input Input 1 Upper nibble of Port C 2 Lower nibble of Port C Mode 0 Programming Example Main define BASE_ADDRESS 0x220 Board located at address 220 define PORTAoffset 0x00 Offset for Port...

Page 174: ...aking signals Ports A and B use the eight lines of Port C to generate or receive the handshake signals This mode divides the ports into two groups Group A and Group B Each group contains one 8 bit data port Port A or Port B and one 4 bit control data port upper or lower nibble of Port C The 8 bit data ports can be either input or output both of which are latched The 4 bit ports are used for contro...

Page 175: ... IBFA Input buffer full for Port A High indicates that data has been loaded into the input latch for Port A 4 INTEA Interrupt enable bit for Port A Enables DIO interrupts from the 82C55A for Port A Controlled by bit set reset of PC4 3 INTRA Interrupt request status for Port A When INTEA is high and IBFA is high this bit is high indicating that a DIO interrupt request is asserted 2 INTEB Interrupt ...

Page 176: ... addresses porta BASE_ADDRESS PORTAoffset portb BASE_ADDRESS PORTBoffset portc BASE_ADDRESS PORTCoffset cnfg BASE_ADDRESS CNFGoffset EXAMPLE 1 Port A input outp cnfg 0xB0 Port A is an input in Mode 1 while inp portc 0x20 Wait until IBFA is set indicating that data has been loaded in Port A valread inp porta Read the data from Port A EXAMPLE 2 Port B input outp cnfg 0x86 Port B is an input in Mode ...

Page 177: ...EA I O I O INTRA INTEB OBFB INTRB Bit Name Description 7 OBFA Output buffer full for Port A Low indicates that the CPU has written data to Port A 6 INTEA Interrupt enable bit for Port A If this bit is high DIO interrupts are enabled from the 82C55A for Port A Controlled by bit set reset of PC6 5 4 I O Extra I O status line when Port A is in Mode 1 output 3 INTRA Interrupt request status for Port A...

Page 178: ...0x02 Offset for Port C define CNFGoffset 0x03 Offset for CNFG register unsigned int porta portb portc cnfg char valread Variable to store data read from a port Calculate register addresses porta BASE_ADDRESS PORTAoffset portb BASE_ADDRESS PORTBoffset portc BASE_ADDRESS PORTCoffset cnfg BASE_ADDRESS CNFGoffset EXAMPLE 1 Port A output outp cnfg 0xA0 Port A is an output in Mode 1 while inp portc 0x80...

Page 179: ...ol status port Port C Latched inputs and outputs The control word written to the DIO 24 CNFG Register to configure Port A as a bidirectional data bus in Mode 2 is shown as follows If Port B is configured for Mode 0 then PC2 PC1 and PC0 of Port C can be used as extra input or output lines Port C PC2 PC0 1 input 0 output Port B 1 input 0 output Group B Mode 0 Mode 0 1 Mode 1 1 X X 1 0 1 1 0 X 1 0 7 ...

Page 180: ...NTE2 is high and OBFA is high this bit is high indicating that a DIO interrupt request is asserted for output transfers 2 1 0 I O Extra I O status lines available if Port B is not configured for Mode 1 At the DIO 24 I O connector Port C has the following pin assignments when in Mode 2 OBFA PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 STBA INTRA I O IBFA Group A ACKA I O I O Mode 2 Programming Example Main defi...

Page 181: ...r several different operating modes The interrupt handling routines and interrupt installation routines are not included See the IBM Personal Computer AT Technical Reference manual for additional information Main define BASE_ADDRESS 0x210 Board located at address 210 define PORTAoffset 0x00 Offset for Port A define PORTBoffset 0x01 Offset for Port B define PORTCoffset 0x02 Offset for Port C define...

Page 182: ... to enable interrupts EXAMPLE 5 Set up interrupts for Mode 2 output transfers Select PC2 as the interrupt enable bit outp cnfg 0xC0 Mode 2 output outp cnfg 0x0D Set PC6 to enable interrupts from 82C55A outp cnfg 0x04 Clear PC2 to enable interrupts EXAMPLE 6 Set up interrupts for Mode 2 input transfers Select PC2 as the interrupt enable bit outp cnfg 0xD0 Mode 2 input outp cnfg 0x09 Set PC4 to enab...

Page 183: ...1 output PC2 If Port A is in Mode 2 Port B is not in Mode 1 To enable interrupts from the DIO 24 circuitry of the AT MIO 16D board select PC2 PC4 or PC6 as the active low interrupt enable signal Initially set the selected bit high to disable unwanted interrupts Program the DIO 24 circuitry for the I O mode you want To enable interrupts from the 82C55A set either the INTEA or the INTEB bit to enabl...

Page 184: ...ion Equipment Requirements For best measurement results the AT MIO 16D analog input circuitry needs to be calibrated so that its measurement accuracy is within 0 012 of its input range 1 2 LSB According to standard practice the equipment used to calibrate the AT MIO 16D should be 10 times as accurate that is have 0 001 rated accuracy Practically speaking calibration equipment with four times the a...

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Page 186: ...t circuitry and adjust a trimpot until the ADC returns readings that flicker between its most negative count and the most negative count plus one The voltages corresponding to V fs and 1 LSB are given in the following table All the stages up to and including the input of the ADC contribute to the gain error of the analog input circuitry With the instrumentation amplifier set to a gain of 1 the gai...

Page 187: ...ngle ended input apply your calibration voltages between the channel 0 positive input and whichever ground system you are using refer to Chapter 2 Configuration and Installation for instructions on using single ended input connections Bipolar Input Calibration Procedure If your board is configured for bipolar input which provides the ranges 5 to 5 V or 10 to 10 V then complete the following proced...

Page 188: ...n the input range selected Input Range Calibration Voltage 10 to 10 V 9 99268 V 5 to 5 V 4 99634 V a Connect the calibration voltage across ACH0 pin 3 on the I O connector and ACH8 pin 4 Connect the ground point on the calibration voltage source to AI SENSE pin 19 b Take analog input readings from channel 0 at a gain of 1 and adjust trimpot R1 until the ADC readings flicker evenly between 2 046 an...

Page 189: ...input gain Adjust the analog input gain by applying an input voltage across ACH0 and ACH8 This input voltage is 9 99634 V or V fs 3 2 LSB a Connect the calibration voltage 9 99634 V across ACH0 pin 3 on the I O connector and ACH8 pin 4 Connect the ground point on the calibration voltage source to AI SENSE pin 19 b Take analog input readings from Channel 0 at a gain of 1 and adjust trimpot R1 until...

Page 190: ...ence input DC only you must recalculate the desired output voltages to calibrate to For bipolar output 1 LSB Vextref 2 048 therefore 1 2 LSB Vextref 4 096 V fs Vextref V fs Vextref 1 LSB For unipolar output 1 LSB Vextref 4 096 therefore 1 2 LSB Vextref 8 192 V fs 0 V V fs Vextref 1 LSB In calibrating to your own external reference you should write your own procedures using the following procedures...

Page 191: ...eter between DAC0 OUT pin 20 on the I O connector and AOGND pin 23 b Set the analog output channel to 9 99512 V by writing 2 047 to the DAC c Adjust trimpot R5 until the output voltage read is 9 99512 V 2 44 mV that is between 9 99268 and 9 99756 V For analog output channel 1 a Connect the voltmeter between DAC1 OUT pin 21 on the I O connector and AOGND pin 23 b Set the analog output channel to 9 ...

Page 192: ...n Adjust the analog output gain by measuring the output voltage generated with the DAC set at positive full scale 4 095 This output voltage should be V fs 1 2 LSB For unipolar output V fs 9 99756 V and 1 2 LSB 1 22 mV For analog output channel 0 a Connect the voltmeter between DAC0 OUT pin 20 on the I O connector and AO GND pin 23 b Set the analog output channel to 9 99756 V by writing 4 095 to th...

Page 193: ...erature 0 5 LSB typical worst case codes Differential analog input ranges 10 V 5 V or 0 to 10 V jumper selectable Analog input range 12 V Common mode range 7 V for 10 V differential analog input range 9 5 V for 5 V differential analog input range 7 V for 0 to 10 V differential analog input range Instrumentation amplifier Common mode rejection ratio 75 dB minimum DC through 100 Hz Input bias curren...

Page 194: ...is ideally 1 2 LSB it can be different for each possible digital code and is actually the analog width of each code Thus it is more specific to use relative accuracy as a measure of linearity than it is to use what is normally called nonlinearity because relative accuracy ensures that the sum of quantization uncertainty and analog to digital A D conversion error does not exceed a given amount Inte...

Page 195: ...ttling time of the analog input front end When data acquisition is performed on a single analog input channel the time required for the input sample and hold amplifier to acquire the input signal and settle to 12 bit accuracy 0 01 is added to the conversion time of the ADC The sample and hold amplifier in the AT MIO 16D takes 1 µsec typical and 1 5 µsec maximum to settle to 0 01 for a 10 V step Th...

Page 196: ...V µsec Output noise 1 mV rms DC to 1 MHz Output impedance 0 2 Ω Explanation of Analog Output Specifications Relative accuracy in a digital to analog D A system is the same as nonlinearity because no uncertainty is added due to code width Unlike an ADC every digital code in a D A system represents a specific analog value rather than a range of values The relative accuracy of the system is therefore...

Page 197: ...equency output channel Base clock available 1 MHz 100 kHz 10 kHz 1 kHz 100 Hz Base clock accuracy 0 01 Compatibility TTL compatible inputs and outputs Counter gate and source inputs are pulled up with 4 7 kΩ resistors onboard Counter input frequency 6 9 MHz maximum 145 nsec period with a minimum pulse width of 70 nsec Current source capability 200 µA Current sink capability 3 2 mA DIO 24 Circuitry...

Page 198: ...hown previously is the result of running an assembly program which continuously writes a constant to an output port on an 8 MHz PC AT compatible The typical transfer rate is the result of running an assembly program which continuously reads data from memory and writes to an output port on an 8 MHz PC AT compatible Power Requirement from PC AT I O Channel Power consumption 1 6 A typical at 5 VDC Ph...

Page 199: ... 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 FOUT GATE5 OUT2 SOURCE2 GATE1 EXTCONV START TRIG SCANCLK 5 V BDIO3 BDIO2 BDIO1 BDIO0 DIG GND EXTREF DAC0 OUT ACH15 ACH14 ACH13 ACH12 ACH11 ACH10 ACH9 ACH8 AI GND EXTSTROBE AI GND ACH0 ACH1 ACH2 ACH3 ACH4 ACH5 ACH6 ACH7 AI SENSE DAC1 OUT AO GND ADIO0 ADIO1 ADIO2 ADIO3 DIG GND 5 V STOP TRIG SOURCE1 OUT1 GATE2 SO...

Page 200: ...log output channel 0 21 DAC1 OUT AOGND Analog Channel 1 Output This pin supplies the voltage output of analog output channel 1 22 EXTREF AOGND External Reference This is the external reference input for the analog output circuitry 23 AO GND N A Analog Output Ground The analog output voltages are referenced to this node 24 33 DIG GND N A Digital Ground This pin supplies the reference for the digita...

Page 201: ...low edge on EXTCONV causes an A D conversion to occur If EXTGATE or EXTCONV is low conversions are inhibited 41 SOURCE1 DIGGND SOURCE1 This pin is from the Am9513A Counter 1 signal 42 GATE1 DIGGND GATE1 This pin is from the Am9513A Counter 1 signal 43 OUT1 DIGGND OUTPUT1 This pin is from the Am9513A Counter 1 signal 44 SOURCE2 DIGGND SOURCE2 SOURCE5 This pin is from the Am9513A Counter 2 signal 45...

Page 202: ... MIO 16D 1 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND PA5 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PA7 PA6 PA4 PA3 PA2 PA1 PA0 5 V Figure C 1 AT MIO 16D DIO 24 I O Connector ...

Page 203: ...r Port C 7 9 11 PC7 is the MSB PC0 the LSB 13 15 17 19 21 PB7 through PB0 DIGGND Bidirectional data lines for Port B 23 25 27 PB7 is the MSB PB0 the LSB 29 31 33 35 37 PA7 through PA0 DIGGND Bidirectional data lines for Port A 39 41 43 PA7 is the MSB PA0 the LSB 45 47 49 5 V DIGGND This pin provides 5 VDC All even DIGGND These signals are connected to the PC ground numbered signal pins ...

Page 204: ... OUT1 SOURCE2 GATE2 OUT2 SOURCE5 GATE5 OUT5 FOUT PC7 GND PC6 GND PC5 GND PC4 GND PC3 GND PC2 GND PC1 GND PC0 GND PB7 GND PB6 GND PB5 GND PB4 GND PB3 GND PB2 GND PB1 GND PB0 GND PA7 GND PA6 GND PA5 GND PA4 GND PA3 GND PA2 GND PA1 GND PA0 GND 5 V GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 5...

Page 205: ...eet for the Am9513A System Controller integrated circuit Advanced Micro Devices Inc This device is used on the AT MIO 16D Copyright Advanced Micro Devices Inc 1989 Reprinted with permission of copyright owner All rights reserved Advanced Micro Devices Inc 1990 Data Book Personal Computer Products Processors Coprocessors Video and Mass Storage ...

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Page 245: ...endix contains the manufacturer data sheet for the MSM82C55A CMOS Programmable Peripheral Interface Oki Semiconductor This device is used on the AT MIO 16D Copyright Oki Semiconductor 1990 Reprinted with permission of copyright owner All rights reserved Oki Semiconductor Microprocessor Data Book 1990 1991 ...

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Page 262: ...iday from 8 00 a m to 6 00 p m central time In other countries contact the nearest branch office You may fax questions to us at any time Corporate Headquarters 512 795 8248 Technical support fax 800 328 2203 512 794 5678 Branch Offices Phone Number Fax Number Australia 03 879 9422 03 879 9179 Austria 0662 435986 0662 437010 19 Belgium 02 757 00 20 02 757 03 11 Denmark 45 76 26 00 45 76 71 11 Finla...

Page 263: ... any National Instruments hardware or software products related to this problem include the configuration forms from their user manuals Include additional pages if necessary Name Company Address Fax Phone Computer brand Model Processor Operating system Speed MHz RAM MB Display adapter Mouse yes no Other adapters installed Hard disk capacity MB Brand Instruments used National Instruments hardware p...

Page 264: ...______________________ Factory Setting 5 DMA Channels of AT MIO 16D ____________________________________ Factory Setting 6 and 7 Base I O Address of AT MIO 16D ____________________________________ Factory Setting hex 0220 NI DAQ Version ____________________________________ Other Products Computer Make and Model ____________________________________ Microprocessor ___________________________________...

Page 265: ... Part Number 320489 01 Please comment on the completeness clarity and organization of the manual If you find errors in the manual please record the page numbers and describe the errors Thank you for your help Name Title Company Address Phone Mail to Technical Publications Fax to Technical Publications National Instruments Corporation National Instruments Corporation 6504 Bridge Point Parkway MS 53...

Page 266: ...scription F 2 Group A different in mode from Group B F 16 interrupt control function F 11 Mode 0 basic input output operation F 11 Mode 1 strobe bidirectional operation F 14 to F 15 Mode 1 strobe input output operation F 12 to F 14 operating range F 4 operational description F 10 to F 17 output characteristics reference value F 8 pin configuration F 3 Port C status read F 16 reset F 16 strobe inpu...

Page 267: ... simultaneous 4 67 pretriggering with STOP TRIG signal 4 54 on single channel 4 49 to 4 50 A D Clear Register 4 14 A D conversion See analog input circuitry multiple A D conversions programming A D converter 3 7 A D FIFO output binary formats 4 44 to 4 45 straight binary mode A D conversion values 4 45 two s complement mode A D conversion values 4 45 A D FIFO Register description of 4 24 output bi...

Page 268: ... data pointer register E 9 data pointer sequencing E 10 E 13 data port registers E 11 design hints E 39 detailed description E 8 to E 11 FOUT divider E 12 FOUT gate E 12 FOUT source E 12 frequency scaler ratios E 13 GATE SRC configuration suggestion E 40 gating control E 13 E 29 gating modes 3 14 general description E 2 hardware retriggering E 29 hold register E 11 initialization 4 42 input circui...

Page 269: ...ntrolling with EXTCONV signal 4 56 interval channel scanning pseudo simultaneous 4 63 pretriggering with STOP TRIG signal 4 51 on single channel 4 47 analog input circuitry A D converter 3 7 A D FIFO buffer 3 7 block diagram 3 5 input multiplexers 3 6 instrumentation amplifier 3 6 mux gain memory 3 6 programming 4 43 to 4 46 A D FIFO output binary formats 4 44 to 4 45 clearing analog input circuit...

Page 270: ...cedure 5 7 to 5 8 board configuration 5 7 unipolar output calibration procedure 5 8 analog output circuitry block diagram 3 10 DAC operation 3 10 to 3 11 initializing 4 43 programming 4 71 to 4 72 analog output voltage versus digital code bipolar mode 4 72 unipolar mode 4 71 formulas for voltage output 4 71 theory of operation 3 10 to 3 11 unipolar and bipolar output 3 11 voltage reference source ...

Page 271: ...fault settings for National Instrument products 2 3 to 2 5 example switch settings 2 4 factory setting for 2 3 switch settings with base I O address and address space 2 5 verifying the address space 2 3 BDIO 0 3 signal 2 23 bipolar input calibration procedure 5 4 to 5 5 bipolar output analog output circuitry 3 11 calibration procedure 5 7 to 5 8 configuration jumper settings 2 16 to 2 17 straight ...

Page 272: ... IBFB 4 83 INT2EN 4 9 INTE1 4 88 INTE2 4 88 INTEA 4 83 4 85 INTEB 4 83 4 85 INTEN 4 9 INTRA 4 83 4 85 4 88 INTRB 4 83 4 85 I O 4 83 4 85 4 88 LASTONE 4 23 LDAC 4 10 MA 2 0 4 8 MA 3 0 4 23 MC 3 0 4 21 MUX0EN 4 8 MUX1EN 4 7 OBFA 4 85 4 87 OBFB 4 85 OUT 5 1 4 29 OUT2INT 4 6 OVERFLOW 4 7 OVERRUN 4 7 RSI 4 34 SCANDIV 4 5 SCANEN 4 5 SCN2 4 10 TCINTEN 4 4 board configuration See calibration procedures co...

Page 273: ...uitry See analog input circuitry Command Register 1 4 4 to 4 5 Command Register 2 4 9 to 4 10 common mode signal rejection considerations 2 32 to 2 33 configuration See also installation jumper settings signal connections analog input configuration 2 10 to 2 14 DIFF differential input 2 10 to 2 11 input mode 2 10 input polarity and range 2 12 to 2 14 NRSE input 16 channels 2 12 RSE input 16 channe...

Page 274: ...nter Timer Register Group See Am9513 Counter Timer Register Group custom cables 1 6 customer communication vii G 1 D DAC0 OUT signal 2 23 2 33 to 2 34 DAC0 Register 4 17 DAC1 OUT signal 2 23 2 33 to 2 34 DAC1 Register 4 18 data acquisition programming continuous channel scanning round robin enabling 4 61 overflow and overrun conditions 4 61 to 4 62 servicing 4 61 to 4 62 controlling with EXTCONV s...

Page 275: ...g input A 2 analog output A 4 DIG GND signal 2 23 digital I O circuitry See MIO 16 digital I O circuitry DIO 24 circuitry cabling considerations 2 51 to 2 52 interrupt handling 4 90 to 4 91 interrupt enable settings 2 8 interrupt enable signals for all modes 4 91 interrupt programming examples 4 89 to 4 90 jumper settings 4 91 theory of operation 3 17 specifications input signal A 5 I O signal rat...

Page 276: ...2 48 Mode 2 bidirectional timing 2 49 pin assignments 2 43 C 1 Port C pin assignments 2 44 to 2 45 power connections 2 44 signal descriptions 2 44 theory of operation 3 18 timing specifications 2 45 to 2 46 DIO 24 Register Group See also DIO 24 circuitry programming DIO 24 CNFG Register 4 40 DIO 24 PORTA Register 4 37 DIO 24 PORTB Register 4 38 DIO 24 PORTC Register 4 39 overview 4 36 to 4 40 regi...

Page 277: ...l reference selection 2 15 External Strobe Register 4 15 external timing considerations for multiple A D conversions programming See multiple A D conversions programming EXTREF signal 2 23 2 33 to 2 34 EXTSTROBE signal definition of 2 23 digital I O circuitry 3 12 to 3 13 timing connections 2 36 to 2 37 F fax technical support G 1 field wiring considerations 2 50 floating signal sources descriptio...

Page 278: ...ounter Timer 4 42 analog output circuitry 4 43 AT MIO 16 board 4 41 to 4 43 input configurations common mode signal rejection 2 32 to 2 33 differential input floating signal sources 2 29 to 2 30 general considerations 2 27 to 2 28 ground referenced signal sources 2 28 to 2 29 recommended configurations for ground referenced and floating signal sources 2 27 single ended connections floating signal ...

Page 279: ...g specifications DIO 24 circuitry A 5 J jumper settings analog I O jumper settings 2 8 to 2 9 bipolar output selection 2 16 to 2 17 AT bus interface factory settings 2 1 default settings for National Instrument products 2 3 DIFF differential input configuration 2 10 to 2 11 DIO 24 circuitry interrupt handling 2 8 4 91 DMA jumper settings 2 5 to 2 7 example base I O address switch settings 2 4 exte...

Page 280: ...erface See 82C55A Programmable Peripheral Interface multiple A D conversions programming continuous channel scanning round robin applying a trigger 4 61 clearing A D circuitry 4 61 enabling scanning data acquisition operation 4 61 overflow and overrun conditions 4 61 to 4 62 overview 4 57 resetting multiplexer counter 4 61 sample counter programming 4 59 to 4 60 sample interval counter programming...

Page 281: ...pplying a trigger 4 50 clearing A D circuitry 4 49 to 4 50 enabling data acquisition operation 4 50 overflow and overrun conditions 4 50 to 4 51 sample counter programming 4 48 to 4 49 sample interval counter programming 4 47 to 4 48 selecting input channel and gain 4 47 servicing data acquisition operation 4 50 to 4 51 steps for 4 46 to 4 47 multiple channel scanned data acquisition 3 9 multiplex...

Page 282: ...channel interface circuitry 3 2 to 3 4 address decoder circuitry 3 3 address latches 3 3 address lines 3 3 block diagram 3 3 data buffers 3 3 DMA control circuitry 3 4 interrupt control circuitry 3 4 timing signals 3 3 PC7 through PC0 signals 2 44 physical specifications A 6 pin assignments 82C55A Programmable Peripheral Interface F 3 Mode 1Ðstrobed input 4 84 Mode 1Ðstrobed output 4 86 Mode 2Ðbid...

Page 283: ... 4 81 programming example 4 81 to 4 82 Mode 1Ðstrobed input 4 82 to 4 84 pin assignments 4 84 Port C status word bit definitions 4 83 to 4 84 programming example 4 84 Mode 1Ðstrobed output 4 84 to 4 86 pin assignments 4 86 programming example 4 86 status word bit definitions 4 85 to 4 86 Mode 2Ðbidirectional bus 4 87 to 4 89 control word 4 87 pin assignments 4 87 to 4 88 status word bit definition...

Page 284: ...sions MIO 16 continuous channel scanning round robin 4 57 to 4 62 applying a trigger 4 61 clearing A D circuitry 4 61 enabling scanning data acquisition operation 4 61 overflow and overrun conditions 4 61 to 4 62 resetting multiplexer counter 4 61 sample counter programming 4 59 to 4 60 sample interval counter programming 4 58 to 4 59 servicing data acquisition operation 4 61 to 4 62 setting up an...

Page 285: ... overrun conditions 4 50 to 4 51 sample counter programming 4 48 to 4 49 sample interval counter programming 4 47 to 4 48 selecting input channel and gain 4 47 servicing data acquisition operation 4 50 to 4 51 steps for 4 46 to 4 47 pulse width measurement 2 39 pulses producing 2 39 R referenced single ended RSE input configuration 2 11 to 2 12 definition of 2 10 single ended connections for float...

Page 286: ...s 4 41 register map 4 1 to 4 2 register sizes 4 2 RTSI Switch Register Group 4 33 to 4 35 RTSI Switch Shift Register 4 34 RTSI Switch Strobe Register 4 35 relative accuracy specification analog input A 2 analog output A 4 resetting hardware after data acquisition Counter 2 4 69 Counter 3 4 69 Counter 4 4 70 Counter 5 4 70 round robin scanning See multiple A D conversions programming RSE input See ...

Page 287: ...on amplifier 2 26 pin descriptions 2 25 to 2 26 warning against exceeding input ranges 2 25 analog output signal connections 2 33 to 2 34 cabling considerations 2 50 to 2 52 DIO 24 cabling 2 51 to 2 52 field wiring 2 50 MIO 16 cabling 2 50 to 2 51 digital I O signal connections 2 34 to 2 36 DIO 24 I O connector pin 2 43 to 2 49 Mode 1 input timing 2 47 Mode 1 output timing 2 48 Mode 2 bidirectiona...

Page 288: ...sions See multiple A D conversions programming single ended connections floating signal RSE sources 2 30 to 2 31 general considerations 2 30 grounded signal NRSE sources 2 31 to 2 32 single ended input configuration NRSE input 16 channels 2 12 RSE input 16 channels 2 11 to 2 12 software optional 1 4 SOURCE OUT and GATE timing signals 2 38 to 2 42 3 14 to 3 15 3 16 SOURCE1 signal 2 24 SOURCE2 signa...

Page 289: ...51 servicing data acquisition operation 4 55 RTSI switch 3 16 storage environment specifications A 6 straight binary mode A D conversion values 4 45 output selection 2 17 system noise A 3 T technical support G 1 theory of operation 82C55A Programmable Peripheral Interface 3 18 to 3 19 Mode 0 3 18 Mode 1 3 19 Mode 2 3 19 modes of operation 3 18 single bit set reset feature 3 19 analog input circuit...

Page 290: ...timing connections 2 36 to 2 38 EXTCONV signal 2 37 EXTSTROBE signal 2 36 to 2 37 SCANCLK signal 2 36 START TRIG signal 2 37 to 2 38 STOP TRIG signal 2 38 general purpose connections 2 38 to 2 42 event counting application with external switch gating 2 39 frequency measurement 2 40 GATE SOURCE and OUT signals 2 38 to 2 42 input and output ratings 2 40 to 2 41 time lapse measurement 2 39 to 2 40 ti...

Page 291: ...ion single input channel 4 50 two s complement mode A D conversion values 4 45 factory settings 2 17 U unipolar input calibration procedure 5 5 to 5 6 unipolar output analog output circuitry 3 11 calibration procedure 5 8 configuration 2 18 unpacking the AT MIO 16 1 7 ...

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