National Instruments AT-DIO-32F, User Manual

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Chapter 4 Programming
© National Instruments Corporation 4-49 AT-DIO-32F User Manual
Pattern Generation Using Onboard Counters
There are three onboard counters on the AT-DIO-32F, each designated for a specific purpose.
The output of Counter 1 is connected to the Group 1 handshaking request line REQ1. The output
of Counter 2 is connected to the Group 2 handshaking request line REQ2. The output of Counter
3 can be used as the counting source for Counter 1 or 2. The counting source for Counter 3 is a
2-MHz square wave. The output of Counter 3 can also be used to generate interrupts.
Counters 1 and 2 have counting enable bits that connect to the gate input of the counter. The
output of Counter 3 is always enabled. The CNT1EN bit in the CFG3 Register enables Counter
1 for counting; the CNT2EN bit in the CFG3 Register enables Counter 2 for counting; and both
counters can be enabled or disabled by external signals IN1 and IN2, respectively. When IN1
and IN2 are used to control the counters, CNT1EN and CNT2EN must be set so that an active
high-level signal on IN1 can enable Counter 1 and an active high-level signal on IN2 can enable
Counter 2.
Counters 1 and 2 can be used for pattern generation. Counter 1 implements pattern generation
for Group 1, and Counter 2 implements pattern generation for Group 2. When the CNT1HSEN
bit in the CFG3 Register is set, the output of Counter 1 controls the REQ1 line. When the
CNT2HSEN bit in the CFG3 Register is set, the output of Counter 2 controls the REQ2 line. If a
counter is used for pattern generation, the corresponding REQ line on the digital I/O connector
should be disconnected or in a high-impedance state.
Table 4-4. Counter 3 Programmable Frequency Output
Data Written to CNTR3 (hex) Counter 3 Output Frequency
FFFF 30.0 Hz
8000 61.0 Hz
4000 122.0 Hz
2000 244.0 Hz
FFF 488.0 Hz
A00 780.0 Hz
800 976.0 Hz
400 1.95 kHz
FF 7.8 kHz
A0 12.5 kHz
80 15.62 kHz
60 20.83 kHz
40 31.25 kHz
20 62.5 kHz
10 125.0 kHz
8 250.0 kHz
4 500.0 kHz
2 1.0 MHz
The CNT1SRC and CNT2SRC bits in the CFG3 Register select the counting source for Counter
1 and Counter 2, respectively. If the CNT1SRC bit is cleared, the counting source for Counter 1