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National Instruments AT-DIO-32F, User Manual

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National Instruments AT-DIO-32F User Manual Download Page 69

Programming 

Chapter 4

AT-DIO-32F User Manual

4-22

© National Instruments Corporation

Port A Register

The Port A Register contains eight bits that connect to the digital I/O connector and can either be
read from or written to.

Address:

Base a 06 (hex)

Type:

Read-and-write

Word Size:

8-bit or 16-bit

Bit Map:

7

6

5

4

3

2

1

0

DIOA7

DIOA6

DIOA5

DIOA4

DIOA3

DIOA2

DIOA1

DIOA0

When Port A is configured as a write port, writing data to this register latches, or stores, the data
into Port A and sends the data out on Port A on the digital I/O connector.  Reading Port A when
it is in write mode returns the value that is currently driven on the port.  If the DBLBUFA bit in
the CFG1 Register is set, the data written to Port A is stored in the buffer.  However, this data is
not dumped to the I/O connector until the active REQ1 level or pulse is received.  During an
active REQ1 level or pulse, the data is dumped to the I/O connector.

When Port A is configured as a read port, reading Port A returns the current data at Port A.  If the
DBLBUFA bit in the CFG1 Register is set, data is latched into Port A on the active level or
active edge of REQ1.  In level mode, data is latched during the active level of REQ1 until REQ1
is inactive.  In pulse mode, data is latched on the active edge of REQ1 until the data is read from
the port.

Either 8-bit or 16-bit transfers can be performed on Port A.

16-Bit Write or Read from Port A

Port B

Port A

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

8-Bit Write or Read from Port A

Port A

7

6

5

4

3

2

1

0

Summary of Contents for AT-DIO-32F

Page 1: ...Copyright 1989 1995 National Instruments Corporation All Rights Reserved AT DIO 32F User Manual High Speed 32 Bit Parallel Digital I O Interface for the PC April 1995 Edition Part Number 320147 01...

Page 2: ...ria 0662 435986 Belgium 02 757 00 20 Canada Ontario 519 622 9310 Canada Qu bec 514 694 8521 Denmark 45 76 26 00 Finland 90 527 2321 France 1 48 14 24 24 Germany 089 741 31 30 Italy 02 48301892 Japan 0...

Page 3: ...for any damages arising out of or related to this document or the information contained in it EXCEPT AS SPECIFIED HEREIN NATIONAL INSTRUMENTS MAKES NO WARRANTIES EXPRESS OR IMPLIED AND SPECIFICALLY DI...

Page 4: ...or application designer Any use or application of National Instruments products for or involving medical or clinical treatment must be performed by properly trained and qualified medical personnel an...

Page 5: ...O Address Selection 2 4 DMA Channel Selection 2 7 Interrupt Selection 2 9 RTSI Bus Clock Selection 2 10 Installation 2 12 Signal Connections 2 13 I O Connector Pin Description 2 13 Signal Connection...

Page 6: ...19 DMACLR2 Register 4 20 Digital I O Port Register Group 4 21 Port A Register 4 22 Port B Register 4 23 Port C Register 4 24 Port D Register 4 25 RTSI Bus Register Group 4 26 RTSISHFT Register 4 27 R...

Page 7: ...r B 3 CNTINTCLR Register B 3 DMACLR1 Register B 3 DMACLR2 Register B 3 Port A Register B 3 Port B Register B 3 Port C Register B 4 Port D Register B 4 RTSISHFT Register B 4 RTSISTRB Register B 4 CNTR1...

Page 8: ...11 Drive RTSI Bus Clock Signal with Onboard Oscillator 2 11 Figure 2 12 Digital I O Connector Pin Assignments 2 13 Figure 3 1 AT DIO 32F Block Diagram 3 1 Figure 3 2 AT DIO 32F Clock Routing Scheme 3...

Page 9: ...7 Table 2 4 DMA Channels for the AT DIO 32F 2 8 Table 2 5 Configurations for RTSI Bus Clock Selection 2 11 Table 4 1 AT DIO 32F Register Map 4 2 Table 4 2 CFG1 Data Settling Time Settings 4 43 Table 4...

Page 10: ...tions to the AT DIO 32F board and cable wiring Chapter 3 Theory of Operation explains the basic operation of the AT DIO 32F circuitry Chapter 4 Programming describes in detail the address and function...

Page 11: ...tion that you may find helpful as you read this manual IBM Personal Computer AT Technical Reference manual You may also want to consult the following manual if you plan to program the Intel 8254 2 Cou...

Page 12: ...11J parallel interface and most standard 32 channel digital I O applications The AT DIO 32F can be used in a wide range of digital I O applications With the AT DIO 32F a digital pattern generator can...

Page 13: ...the NI DAQ software for DOS Windows LabWindows NI DAQ has a library of functions that can be called from your application programming environment These functions include routines for analog input A D...

Page 14: ...Programming You can use the AT DIO 32F with LabVIEW for Windows or LabWindows for DOS LabVIEW and LabWindows are innovative program development software packages for data acquisition and control appl...

Page 15: ...0 5 m 776358 02 1 0 m 776358 12 Digital Signal Conditioning Modules SSR Series mounting rack and 1 0 m cable 32 channel 776290 32 24 channel 776290 24 16 channel 776290 16 8 channel 776290 08 CB 50 I...

Page 16: ...ostatic damage to the board Several components on the board can be damaged by electrostatic discharge To avoid such damage in handling the board take the following precautions Touch the plastic packag...

Page 17: ...Jumper W1 selects the DMA channel and jumper W2 selects the interrupt enable lines The DIP switch is used to set the base I O address AT Bus Interface The AT DIO 32F is configured at the factory to us...

Page 18: ...ing U61 A9 A8 A7 A6 A5 1 2 3 4 5 The black side indicates the side that is pushed down DMA Channel Bank A Channel 5 Bank B Channel 6 factory setting W1 Upper right two rows W1 Lower middle two rows In...

Page 19: ......

Page 20: ...32F uses the base I O address space hex 240 through 25F with the factory setting Note Verify that this space is not already used by other equipment installed in your computer If any equipment in your...

Page 21: ...Address of Hex 000 This side down for 1 A9 A8 A7 A6 A5 OFF ON U61 1 2 3 4 5 1 2 3 4 A9 A8 A7 A6 A5 OFF ON 1 2 3 4 5 U61 This side down for 0 This side down for 1 Figure 2 2 Example Base I O Address Sw...

Page 22: ...CIII Lab PC PC DIO 24 PC DIO 96 PC LPM 16 PC TIO 10 None Channel 5 Channels 5 6 None Channel 5 Channels 6 7 Channels 6 7 Channels 6 7 None None Channel 1 Channel 1 Channel 1 Channel 3 None None None N...

Page 23: ...1 260 260 27F 1 0 1 0 0 280 280 29F 1 0 1 0 1 2A0 2A0 2BF 1 0 1 1 0 2C0 2C0 2DF 1 0 1 1 1 2E0 2E0 2FF 1 1 0 0 0 300 300 31F 1 1 0 0 1 320 320 33F 1 1 0 1 0 340 340 35F 1 1 0 1 1 360 360 37F 1 1 1 0 0...

Page 24: ...owledge Request 5 DACK5 DRQ5 6 DACK6 DRQ6 7 DACK7 DRQ7 Two jumpers must be installed to select a DMA channel The switch BANK A is used to select the DMA channel for Group 1 and the switch BANK B is us...

Page 25: ...two rows of jumper W2 The AT DIO 32F can share interrupt lines with other devices by using a tri state driver to drive its selected interrupt line The AT DIO 32F hardware can use the following interru...

Page 26: ...IRQ5 Only RTSI Bus Clock Selection When multiple AT Series boards are connected via the RTSI bus you may want to have all the boards use the same 10 MHz clock This arrangement is useful for applicati...

Page 27: ...signal STANDBY BRDCLK RTSICLK Drive RTSI bus clock signal with local oscillator BRDCLK OSC BRDCLK RTSICLK Figures 2 9 2 10 and 2 11 show the jumper positions for each of the preceding configurations S...

Page 28: ...ral installation instructions but consult the user manual or technical reference manual of your PC for specific instructions and warnings 1 Turn off your computer 2 Remove the top cover or access port...

Page 29: ...signal are given in this chapter under the discussion of that signal National Instruments is not liable for any damages resulting from any such signal connections 1 49 47 45 43 41 39 37 35 33 31 29 27...

Page 30: ...1 Extra input signal 1 This additional input signal is pulled up to 5 V by an onboard resistor The status of this signal can be obtained by reading the IN1 bit in the STAT Register This input signal c...

Page 31: ...s an extra input signal line or as an external enable signal of Counter 2 of the board 18 ACK2 Output handshaking acknowledge signal for Group 2 When the AT DIO 32F is in write mode this signal become...

Page 32: ...high current 30 mA Output logic low current 70 mA Timing Specifications This section lists the timing specifications for handshaking with the AT DIO 32F The REQ and ACK signals are available on the I...

Page 33: ...is high when the external device is ready to receive the data The status of this signal is available in the STAT register This signal is not available on the I O connector RD Internal Read signal This...

Page 34: ...um T0a REQ pulse width in level mode 125 T0bc REQ pulse width in leading or trailing edge 100 mode T1 REQ low duration 160 T2ab REQ to DRDY in level or leading edge mode 0 225 T2c REQ inactive to DRDY...

Page 35: ...nvalid after REQ 0 double buffered output T17 Output data valid after REQ 0 100 double buffered output All timing values are in nanoseconds Cabling The AT DIO 32F can be interfaced to a wide range of...

Page 36: ...041CE Recommended manufacturers and the appropriate part numbers for the standard ribbon cable 50 conductor 28 AWG stranded that can be used with these connectors are as follows Electronic Products Di...

Page 37: ...dshaking Group 2 Each group can be programmed as either an input or an output group and each group has its own independent handshaking signals for data transfers The key functional components of the h...

Page 38: ...e size of the current data transfer Configuration and Status Registers The AT DIO 32F has seven configuration registers and a status register Four 16 bit configuration registers CFG1 CFG2 CFG3 and CFG...

Page 39: ...ul for pattern generation and periodic data acquisition Counter 1 can be programmed to generate group 1 handshaking requests on the REQ1 line Likewise counter 2 can be programmed to generate group 2 h...

Page 40: ...or All digital I O is through a standard 50 pin male connector The pin assignments for this connector are compatible with the DEC DRV11 J parallel interface and most 32 channel I O module racks Refer...

Page 41: ...et once a REQ is received DRDY remains set until the data is read from the selected ports During a write transfer DRDY is set as soon as the group s WRITE bit is set indicating that the group is in wr...

Page 42: ...n Figure 3 4 shows a write transfer in level mode Send ACK Start TDELAY INIT State When REQ asserted When REQ unasserted After data written After TDELAY LRESET or Power On Continue sending ACK When WR...

Page 43: ...LAY begins After TDELAY ACK is sent to the digital I O connector When another leading edge of REQ is received DRDY is set and the AT DIO 32F is ready for another cycle Figure 3 5 shows a read transfer...

Page 44: ...fer in leading edge mode After TDELAY When REQ unasserted After data written LRESET or Power On Send ACK When REQ asserted Clear ACK pulse Start TDELAY INIT State When WRITE bit and DIOxEN bit for the...

Page 45: ...ELAY ACK is cleared which means that the pulse width of ACK is equivalent to TDELAY If TDELAY is programmed to 0 the pulse width of ACK is 100 nsec When another trailing edge of REQ is received DRDY i...

Page 46: ...the interrupt requests which are tri state output signals the AT DIO 32F board can share the interrupt lines with other devices Five different interrupts can be generated by the AT DIO 32F DRDY1 set D...

Page 47: ...that acts as a seven by seven crossbar switch Pins B 6 0 are connected to the seven RTSI bus trigger lines Pins A 6 0 are connected to seven signals on the board The RTSI switch can drive any of the s...

Page 48: ...be used for pattern generation for one or both handshaking groups A signal from another AT Series board can be sent across the RTSI bus to implement pattern generation as well This chapter contains t...

Page 49: ...0A Write only 16 bit DMACLR1 Register 0C Write only 16 bit DMACLR2 Register 0E Write only 16 bit Digital I O Port Register Group PORT A Register 06 Read and write 8 bit or 16 bit PORT B Register 07 Re...

Page 50: ...ndshaking interrupt requests and DMA requests The registers in the Digital I O Port Group access the four 8 bit digital I O ports The Counter Register Group selects the counting mode and initial count...

Page 51: ...F hardware The four configuration registers CFG1 CFG2 CFG3 and CFG4 control the digital I O modes handshaking modes interrupt and DMA operations The other three configuration registers CNTINTCLR DMACL...

Page 52: ...DMAEN1 Group 1 DMA Enable Bit When DMAEN1 is set DMA is enabled for Group 1 handshaking A DMA request is asserted when DRDY1 is set 14 INTEN1 Group 1 Interrupt Enable Bit When INTEN1 is set interrupts...

Page 53: ...output port a write operation to the port loads data into the first buffer of the port When a REQ1 is received the data is transferred to the second buffer of the port which dumps the data to the dig...

Page 54: ...l Group 1 sends ACK1 as a low signal to acknowledge the end of a data transfer When INVACK1 is cleared ACK1 is configured as an active high signal Group 1 sends ACK1 as a high signal to acknowledge th...

Page 55: ...2 DMA Enable Bit When DMAEN2 is set DMA is enabled for Group 2 handshaking A DMA request is asserted when DRDY2 is set 14 INTEN2 Group 2 Interrupt Enable Bit When INTEN2 is set interrupts are enabled...

Page 56: ...t a write operation to the port loads data into the first buffer of the port When a REQ2 is received the data is transferred to the second buffer of the port which dumps the data to the digital I O co...

Page 57: ...al Group 2 sends ACK2 as a low signal to acknowledge the end of a data transfer When INVACK2 is cleared ACK2 is configured as an active high signal Group 2 sends ACK2 as a high signal to acknowledge t...

Page 58: ...data written to the port is immediately dumped to the digital I O connector When Port B is configured as an input port and DBLBUFB is set an active level or edge of a REQ1 signal latches the data int...

Page 59: ...configured for a write operation after every LRESET1 this bit must first be cleared and then set again for reinitializing handshaking purposes or clear and set DIOAEN of the CFG1 Register 9 CNT2SRC C...

Page 60: ...Enable Bit If CNT1HSEN is set the output of Counter 1 generates the handshaking request for Group 1 3 CNT2EN Counter 2 Enable Bit If CNT2EN is set and the IN2 line is high Counter 2 is enabled for co...

Page 61: ...lay mode of the leading edge pulse handshaking mode for Group 2 If this bit is set the delay is added after the leading edge of the ACK pulse therefore the pulse width is lengthened The delay is 0 to...

Page 62: ...single buffer that is data written to the port is immediately dumped to the digital I O connector When Port D is configured as an input port and DBLBUFD is set an active level or edge of a REQ2 signa...

Page 63: ...ects the double DMA mode in which DMA transfers for Group 1 switch between the two DMA channels 14 CNTINT Counter 3 Interrupt Status Bit This bit reflects the status of the Counter 3 interrupt CNTINT...

Page 64: ...p 1 handshaking request line as seen at the digital I O connector 6 ACK1 Group 1 Handshaking Acknowledge Status Bit ACK1 reflects the status of the Group 1 handshaking acknowledge signal as seen at th...

Page 65: ...ruments Corporation CNTINTCLR Register Writing to the CNTINTCLR Register clears the interrupt request asserted when a rising edge on the Counter 3 output is detected Address Base address 0A hex Type W...

Page 66: ...DIO 32F User Manual DMACLR1 Register Writing to the DMACLR1 Register clears the interrupt request asserted when the DMA terminal count signal of Group 1 is detected Address Base address 0C hex Type W...

Page 67: ...truments Corporation DMACLR2 Register Writing to the DMACLR2 Register clears the interrupt request asserted when the DMA terminal count signal of Group 2 is detected Address Base address 0E hex Type W...

Page 68: ...aking up the Digital I O Register Group monitor and control the AT DIO 32F digital I O lines There are four 8 bit ports on the AT DIO 32F These ports are grouped so that either 8 bit or 16 bit operati...

Page 69: ...UFA bit in the CFG1 Register is set the data written to Port A is stored in the buffer However this data is not dumped to the I O connector until the active REQ1 level or pulse is received During an a...

Page 70: ...the port If the DBLBUFB bit in the CFG3 Register is set the data written to Port A is stored in the buffer However this data is not dumped to the I O connector until the active REQ1 level or pulse is...

Page 71: ...Register is set the data written to Port A is stored in the buffer However this data is not dumped to the I O connector until the active REQ2 level or pulse is received During an active REQ2 level or...

Page 72: ...the port If the DBLBUFD bit in the CFG4 Register is set the data written to Port A is stored in the buffer However this data is not dumped to the I O connector until the active REQ2 level or pulse is...

Page 73: ...registers making up the RTSI Bus Register Group program the AT DIO 32F RTSI switch for routing of signals on the RTSI bus trigger lines to and from AT DIO 32F request REQ and acknowledge ACK signal l...

Page 74: ...X X X X X RSI Bit Name Description 7 1 X Don t Care Bits 0 RSI RTSI Switch Serial Input This bit is the serial input to the RTSI switch Each time the RSI bit is written to the value written is shifte...

Page 75: ...loads the contents of the RTSI Shift Register into the RTSI Switch Control Register thereby updating the RTSI switch routing pattern The RTSISTRB Register is written to after shifting the 56 bit routi...

Page 76: ...g up the Counter Register Group access the onboard 8254 2 Counter Timer The 8254 2 contains three counters Counters 1 2 and 3 can be used for pattern generation and Counter 3 can also be used to gener...

Page 77: ...of Counter 1 or latched data for Counter 1 If the Counter Latch command or the Read Back command is used to latch the count or status of Counter 1 reading these bits returns the latched information Th...

Page 78: ...of Counter 2 or latched data for Counter 2 If the Counter Latch command or the Read Back command is used to latch the count or status of Counter 2 reading these bits returns the latched information T...

Page 79: ...nt of Counter 3 or latched data for Counter 3 If the Counter Latch command or the Read Back command is used to latch the count or status of Counter 3 reading these bits returns the latched information...

Page 80: ...it Name Description 7 6 CNTRSEL 1 0 Counter Select Bits These bits select the counter on which the command operates CNTRSEL1 CNTRSEL0 Operation 0 0 Select Counter 1 0 1 Select Counter 2 1 0 Select Cou...

Page 81: ...d counter The following table lists six available modes and the corresponding bit settings Refer to Appendix D Intel Data Sheet for additional information MODESEL2 MODESEL1 MODESEL0 Mode 0 0 0 Mode 0...

Page 82: ...6 CNTRSEL 1 0 Counter Select Bits Both bits must be one for the Read Back command to be used 5 COUNT Read Back Count Command If COUNT is cleared the current count in each of the selected counters is l...

Page 83: ...he last count written to the selected counter has been loaded into the counter If NULL is set the last count written to the counter has not been loaded 5 4 RW 1 0 RWSEL1 and RWSEL0 Status The RW1 and...

Page 84: ...e 0 Mode 1 and pattern generation Initializing the AT DIO 32F Board The AT DIO 32F hardware must be initialized in order for the AT DIO 32F circuitry to operate properly To initialize the AT DIO 32F h...

Page 85: ...d be enabled for handshaking in a group For 16 bit transfers both ports in a group should be enabled The direction of handshaking for each group is determined by the corresponding WRITE bit If data is...

Page 86: ...o the CFG3 Register to clear the WRITEC bit after the LRESET 6 Write hex 0800 to the CFG3 Register to set the WRITEC bit again after the LRESET Reading the STAT Register returns the status of REQ2 ACK...

Page 87: ...de Read Handshake Timing Leading Edge Mode In leading edge mode REQ and ACK are viewed as pulses that are active on the leading edge of the pulse A handshaking group is in leading edge mode when its P...

Page 88: ...DRDY WR TDELAY ACK Figure 4 3 Leading Edge Mode Write Handshake Timing LPULSEx cleared REQ DRDY RD TDELAY ACK Figure 4 4 Leading Edge Mode Read Handshake Timing LPULSEx cleared RD WR TDELAY ACK with L...

Page 89: ...the pulse A handshaking group is in trailing edge mode when its PULSE and EDGE bits are set Figures 4 6 and 4 7 show the timing diagrams for trailing edge mode For detailed timing information refer t...

Page 90: ...t the software can then write or read data to or from the digital I O port First configure the handshaking group to be used and enable the ports to be used for handshaking Be sure that the direction o...

Page 91: ...d the corresponding DBLBUF bit is cleared reading the port returns the current data on the I O lines whether or not handshaking is enabled When an I O port is configured as a double buffered input por...

Page 92: ...2 Example Interrupt Generation on DRDY1 Instead of polling the DRDY1 bit interrupts can be used to wait for the DRDY1 condition The interrupt service routine can then write or read the data to or fro...

Page 93: ...the interrupt service routine Example Interrupt Generation on Group 1 DMA Terminal Count The DMA terminal count signals the end of the current DMA transfer To use the Group 1 DMA terminal count interr...

Page 94: ...been serviced When another Group 2 DMA terminal count is received software control again jumps to the interrupt service routine Example Interrupt Generation on Counter 3 Counter 3 can be programmed t...

Page 95: ...ently in use If DMACH is cleared the DMA channel for Group 1 is currently in use if DMACH is set the DMA channel for Group 2 is currently in use If the DMA controller is programmed for auto reinitiali...

Page 96: ...nters CNT1EN and CNT2EN must be set so that an active high level signal on IN1 can enable Counter 1 and an active high level signal on IN2 can enable Counter 2 Counters 1 and 2 can be used for pattern...

Page 97: ...he counting source If the counting source is the 10 MHz square wave then the following equation is used to calculate the output frequency of the counter Counter 1 2 Output Frequency 10000000 data writ...

Page 98: ...e data pattern as soon as a REQ is received In the normal mode of operation the data pattern is not dumped to the digital I O connector until the DRDY bit is detected and the data is written to the po...

Page 99: ...le 4 5 If the count is a 16 bit value write the least significant byte first then the most significant 3 Write hex 20 to the CFG3 Register to enable Counter 2 for pattern generation set the CNT2HSEN b...

Page 100: ...connector 6 The received REQ1 sets the DRDY1 bit Write the next pattern to Port A 7 The next REQ1 received dumps the second pattern to the digital I O connector The sequence continues until an LRESET...

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Page 103: ...V 2 0 V 0 8 V 5 5 V 10 A Output low voltage Iout 48 mA Output high voltage Iout 15 mA 2 4 V 0 5 V Transfer rate 1 word 16 bits Absolute max Programmed I O 450 kwords s DMA 330 kwords s Handshaking 2 w...

Page 104: ...F User Manual A 2 National Instruments Corporation Environment Operating temperature 0 to 50 C Storage temperature 40 to 100 C Relative humidity 5 to 90 noncondensing Noise Emission FCC Class A verifi...

Page 105: ...49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 DIOD1 DIOD3 DIOD6 DIOD2 DIOC5 DIOC3 DIOC2 DIOC6 GND GND GND G...

Page 106: ...NVACK1 SETACK1 OUT1 CFG2 Register Base Address Offset 02 hex 16 bit write only 15 14 13 12 11 10 9 8 DMAEN2 INTEN2 T2S2 T2S1 T2S0 DIODEN DIOCEN LRESET2 7 6 5 4 3 2 1 0 X INVRQ2 DBLBUFC PULSE2 EDGE2 IN...

Page 107: ...t 0A hex 16 bit write only Bit map not applicable no bits used DMACLR1 Register Base Address Offset 0C hex 16 bit write only Bit map not applicable no bits used DMACLR2 Register Base Address Offset 0E...

Page 108: ...OD5 DIOD4 DIOD3 DIOD2 DIOD1 DIOD0 RTSISHFT Register Base Address Offset 10 hex 8 bit write only 7 6 5 4 3 2 1 0 X X X X X X X RSI RTSISTRB Register Base Address Offset 12 hex 8 bit write only Bit map...

Page 109: ...nd write 7 6 5 4 3 2 1 0 CNTR3B7 CNTR3B6 CNTR3B5 CNTR3B4 CNTR3B3 CNTR3B2 CNTR3B1 CNTR3B0 CNTRCMD Register Base Address Offset 1E hex 8 bit write only 7 6 5 4 3 2 1 0 CNTRSEL1 CNTRSEL0 RWSEL1 RWSEL0 MO...

Page 110: ...uction Communicating with a Printer The National Instruments AT DIO 32F can interface the PC to any Centronics or Centronics compatible printer In the following program Port A is configured for Group...

Page 111: ...the printer to recognize communication Send a file from the PC to a Centronics printer via the National Instruments AT DIO 32F include stdio h define CFG1offset 0x00 define CFG2offset 0x02 define CFG...

Page 112: ..._n_Write char ch while ch fgetc fp EOF print chars until EOF is reached Print_char ch Print_char 0x0D send linefeed to complete printing check whether given filename is valid Valid_file if fp NULL pri...

Page 113: ...or or BUSY if err printf nCan t get printer ready exit 1 while Read_Stat 0x0100 i 20000 wait for DRDY1 bit set i if i 20000 printf nCan t get DRDY1 set printf nStat x Read_Stat exit 1 outp porta ch pr...

Page 114: ...18 ACK2 REQ2 24 27 ACK1 ACK1 27 24 REQ2 ACK2 18 33 REQ1 GND 17 17 GND GND 28 28 GND GND 19 19 GND GND 30 30 GND GND 21 17 GND GND 32 32 GND GND 23 23 GND GND 34 34 GND Sending and Receiving files with...

Page 115: ...CFG1os base_addr CFG2 CFG2os base_addr CFG3 CFG3os base_addr CFG4 CFG4os base_addr STAT1 STATos base_addr PORTA PORTAos base_addr PORTC PORTCos base_addr lowEOF EOF 0x00ff Set so that EOF character is...

Page 116: ...ain Get the data choose_msg Give choice again break End case r End switch ch getch End while printf nExit requested User selected e for exit End choose_what Message for choose_what choose_msg printf n...

Page 117: ...putw wd stdout Echo characters to screen outpw PORTC wd Send a 16 bit word to the MC DIO 32F Return non zero value if the AT DIO 32F is ready to be written more data data_out_rdy return inpw STAT1 0x...

Page 118: ...tion getwd will return an int EOF 0xFFFF if either the first or second byte read was an EOF The function getwd however returns the following 0xFFFF int EOF if the high byte is an EOF char 0x FF a char...

Page 119: ...AT DIO 32F The AT DIO 32F can also be used with I O module racks that are not pin compatible if a special cable is built The AT DIO 32F is directly pin compatible with the following I O module racks...

Page 120: ...32F I O connector is a 50 pin male ribbon cable header Recommended manufacturer part numbers for this header are Electronic Products Division 3M part number 3596 5002 T B Ansley Corporation part numb...

Page 121: ...of this key varies from rack to rack Consult the specification for the rack you intend to use for the location of any polarizing key The recommended manufacturer part numbers for this polarizing key a...

Page 122: ...he 8254 Programmable Interval Timer Intel Corporation data sheet This counter timer device is used on the AT DIO 32F board Copyright Intel Corporation 1989 Reprinted with permission of copyright owner...

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Page 144: ...day from 8 00 a m to 6 00 p m central time In other countries contact the nearest branch office You may fax questions to us at any time Corporate Headquarters 512 795 8248 Technical support fax 800 32...

Page 145: ...iciently If you are using any National Instruments hardware or software products related to this problem include the configuration forms from their user manuals Include additional pages if necessary N...

Page 146: ...ng Factory Setting disconnect board from RTSI clock __________________________________________________ NI DAQ or LabWindows Version __________________________________________________ Handshaking Mode...

Page 147: ...l Edition Date April 1995 Part Number 320147 01 Please comment on the completeness clarity and organization of the manual If you find errors in the manual please record the page numbers and describe t...

Page 148: ...binary coded decimal C Celsius D A digital to analog dB decibels DC direct current DMA direct memory access F Farads hex hexadecimal Hz hertz in inches INTR Interrupt signal I O input output Iout out...

Page 149: ...11 AT DIO 32F to AT DIO 32F 16 bit communications cabling C 5 sending and receiving files C 5 to C 10 B base I O address avoiding device conflicts 2 4 configuration 2 4 to 2 5 default addresses 2 4 de...

Page 150: ...MACLR1 Register 4 19 B 3 DMACLR2 Register 4 20 B 3 overview 4 4 register map 4 2 STAT Register 4 16 to 4 17 B 3 theory of operation 3 2 COUNT bit 4 35 Counter 1 and Counter 2 pattern generation 4 50 t...

Page 151: ...G GND signal 2 15 GO signal 2 16 H handshaking data latches and drivers 3 2 to 3 3 data settling delay 4 43 input data latch 4 44 leading edge mode 3 5 to 3 6 4 40 to 4 41 level mode 3 5 4 39 overview...

Page 152: ...ngs 2 9 default settings chart 2 2 default settings for National Instruments products 2 6 INVACK1 bit 4 6 INVACK2 bit 4 9 INVRQ1 bit 4 6 INVRQ2 bit 4 9 I O channel control circuitry 3 2 I O connector...

Page 153: ...ions 4 37 data settling delay 4 43 DMA transfers 4 48 handshaking modes 4 39 to 4 42 input data latch 4 44 interrupt handling 4 44 to 4 47 I O transfers 4 43 to 4 44 Mode 0 4 37 Mode 1 4 38 to 4 39 pa...

Page 154: ...O connector electrical specifications 2 16 Intel 8254 programmable interval timer D 19 to D 20 I O connector electrical specifications input signal A 1 output signal A 1 operating environment A 2 phys...

Page 155: ...t 4 48 DMA 4 48 programmed I O transfers 4 43 to 4 44 rate specifications A 1 TS2 2 0 bit 4 8 U unpacking the AT DIO 32F 1 5 W WR signal 2 17 write handshake timing See handshaking write timing 2 19 t...

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