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Chapter 3
Theory of Operation
© National Instruments Corporation
3-9
AT-DIO-32F User Manual
Trailing Edge Mode
In trailing edge mode, REQ and ACK are treated as pulses that are active on the trailing edge of
the pulse. Once the data is read or written, ACK is asserted. At this time, TDELAY begins.
After TDELAY, ACK is cleared, which means that the pulse width of ACK is equivalent to
TDELAY. If TDELAY is programmed to 0, the pulse width of ACK is 100 nsec. When another
trailing edge of REQ is received, DRDY is set and the AT-DIO-32F is ready for another cycle.
Figure 3-7 shows a read transfer in trailing edge mode.
After TDELAY
DRDY
INIT
State
When REQ unasserted
When REQ
asserted
After data
read
Send ACK
Start TDELAY
LRESET
or
Power On
Clear
ACK
Wait
When REQ
asserted
Figure 3-7. Trailing Edge Mode – Read
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