NI 6584R User Guide and Specifications
8
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e.
Click
OK
in the
Configure Open FPGA VI Reference
window.
f.
Save the VI.
8.
On the front panel, complete the following steps to generate data.
a.
Enter data into the
Gen Data (Hex)
control. This displays the data to be generated in
hexadecimal format.
b.
Set the
Gen Data Width
control to a number between 1 and 32. The default is 8.
c.
Set the
Stop Bits
control to a number between 1 and 65,535. The default is 1.
d.
Set the
Gen Clock Divider
control. The default generation rate of the UART is 16 Mbit/s, but
it is capable of running at any integer division of this rate. For example, to generate at a rate
of 9,600 Kbit/s, set the
Gen Clock Divider
to 1,667. (16 Mbit/s divided by 1,667 clock cycles
produces a clock rate of 9,598 Kbit/s.)
e.
To generate data continuously, leave the
Write Data
control enabled. To stop generation, click
the
Write Data
button.
9.
On the front panel, complete the following steps to acquire data.
a.
Set the
Acq Data Width
control to a number between 1 and 32. The default is 8.
b.
Set the
Samples to Acquire
control to a number between 1 and 1,023. The default is 5.
c.
Set the
Acq Clock Divider
. The default acquisition rate of the UART is 16 Mbit/s, but it is
capable of running at any integer division of this rate. For example, to acquire at a rate of
9,600 Kbit/s, set the
Acq Clock Divider
to 1,667. (16 Mbit/s divided by 1,667 clock cycles
produces a clock rate of 9,598 Kbit/s.)
d.
To acquire data continuously, leave the
Read Data
control enabled. To stop acquisition, click
the
Read Data
button.
Note
If you are using the half duplex version of the NI 6584R, you cannot both acquire and generate
data at the same time. You must choose whether to enable the
Write Data
button or the
Read Data
button.
10. Click the
Run
button to run the VI. The NI 6584R generates and/or acquires data on Channel 0 of
Port 1. If a timeout error occurs, the number of samples acquired did not reach the value specified
in the
Samples to Acquire
control.