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National Instruments Corporation
13
NI 6584R User Guide and Specifications
Figure 8 shows the relationship between an FPGA VI and CLIP.
Figure 8.
CLIP Relationship
The NI 6584 ships with socketed CLIP that is used to add module I/O to the LabVIEW project.
The NI-developed NI 6584 CLIP are as follows:
•
NI 6584 Basic Channel
—Provides read/write access to all RS-485/422 channels using a simple
channel-based interface. Each output line has a write enable signal. Each input line is always
enabled. This CLIP provides a clock signal for import or export on the BNC CLOCK connector.
The clock input signals from the NI 6584 are passed to LabVIEW FPGA for use in the FPGA VI.
This CLIP also allows for individual clock output signal inversion.
•
NI 6584 Basic Connector
—Provides read/write access to all RS-485/422 channels on
Connector 0 (Ports 1-8). The individual data lines for each connector are accessed using a U16 data
type in LabVIEW FPGA. Each output line has a write enable signal. Each input line is always
enabled. This CLIP provides a clock signal for import or export on the BNC CLOCK connector.
This CLIP also allows for individual clock output signal inversion.
Refer to the
NI FlexRIO Adapter Module Support
topic of the
NI FlexRIO Help
for information
regarding NI FlexRIO CLIP, configuring the NI 6584 with a socketed CLIP, and a list of available
socketed CLIP and provided signals.
Ad
a
pter Module
CLIP Socket
L
ab
VIEW
FPGAVI
User-Defined
CLIP
NI FlexRIO FPGA Module
FPGA
Exter
n
a
l
I/O Connector
Ad
a
pter
Module
Socketed
CLIP
User-Defined
CLIP
Fixed I/O
DRAM 1
CLIP Socket
DRAM 1
CLIP Socket
Socketed
CLIP
Socketed
CLIP
DRAM0
DRAM1
Fix
ed I/O
Fix
ed I/O