Chapter 5
Register Map and Description
PCI-DIO-96 User Manual
5-8
©
National Instruments Corporation
Bit
Name
Description (Continued)
3
BIRQ1
PPI B Port B Interrupt Enable Bit—If this bit and the
INTEN bit in Interrupt Control Register 2 are both
set, PPI B sends an interrupt, INTRB, to the
computer. If this bit is cleared, PPI B does not send
the interrupt INTRB to the computer, regardless of
the setting of INTEN.
2
BIRQ0
PPI B Port A Interrupt Enable Bit—If this bit and the
INTEN bit in Interrupt Control Register 2 are both
set, PPI B sends an interrupt, INTRA, to the
computer. If this bit is cleared, PPI B does not send
the interrupt INTRA to the computer, regardless of
the setting of INTEN.
1
AIRQ1
PPI A Port B Interrupt Enable Bit—If this bit and the
INTEN bit in Interrupt Control Register 2 are both
set, PPI A sends an interrupt, INTRB, to the
computer. If this bit is cleared, PPI A does not send
the interrupt INTRB to the computer, regardless of
the setting of INTEN.
0
AIRQ0
PPI A Port A Interrupt Enable Bit—If this bit and
the INTEN bit in Interrupt Control Register 2 are
both set, PPI A sends an interrupt, INTRA, to the
computer. If this bit is cleared, PPI A does not send
the interrupt INTRA to the computer, regardless of
the setting of INTEN.
