© National Instruments
|
7-3
Buffered (Sample Clock) Edge Counting
With buffered edge counting (edge counting using a sample clock), the counter counts the
number of edges on the Source input after the counter is armed. The value of the counter is
sampled on each active edge of a sample clock. A DMA controller transfers the sampled values
to host memory.
The count values returned are the cumulative counts since the counter armed event. That is, the
sample clock does not reset the counter.
You can route the counter sample clock to the Gate input of the counter. You can configure the
counter to sample on the rising or falling edge of the sample clock.
Figure 7-4 shows an example of buffered edge counting. Notice that counting begins when the
counter is armed, which occurs before the first active edge on Gate.
Figure 7-4.
Buffered (Sample Clock) Edge Counting
Controlling the Direction of Counting
In edge counting applications, the counter can count up or down. You can configure the counter
to do the following:
•
Always count up
•
Always count down
•
Count up when the Counter
n
B input is high; count down when it is low
For information about connecting counter signals, refer to the
section.
Pulse-Width Measurement
In pulse-width measurements, the counter measures the width of a pulse on its Gate input signal.
You can configure the counter to measure the width of high pulses or low pulses on the Gate
signal.
You can route an internal or external periodic clock signal (with a known period) to the Source
input of the counter. The counter counts the number of rising (or falling) edges on the Source
signal while the pulse on the Gate signal is active.
3
6
3
Co
u
nter Armed
S
OURCE
Sa
mple Clock
(
Sa
mple on Ri
s
ing Edge)
Co
u
nter V
a
l
u
e
B
u
ffer
1
0
7
6
3
4
5
2
