National Instruments 6023E User Manual Download Page 29

Page: 29 / 136

Chapter 3

Hardware Overview

6023E/6024E/6025E User Manual

3-10

ni.com

Figure 3-5.

PCI RTSI Bus Signal Connection

RTSI

Bus

Connector

switch

RTSI

Switch

Clock

Trigger

DAQ-STC

TRIG1

TRIG2

CONVERT*

UPDATE*

WFTRIG

GPCTR0_SOURCE

GPCTR0_GATE

GPCTR0_OUT

STARTSCAN

AIGATE

SISOURCE

UISOURCE

GPCTR1_SOURCE

GPCTR1_GATE

RTSI_OSC (20 MHz)

Summary of Contents for 6023E

Page 1: ...DAQ 6023E 6024E 6025E User Manual Multifunction I O Devices for PCI PXI CompactPCI and PCMCIA Bus Computers 6023E 6024E 6025E User Manual December 2000 Edition Part Number 322072C 01...

Page 2: ...725 725 11 France 01 48 14 24 24 Germany 089 741 31 30 Greece 30 1 42 96 427 Hong Kong 2645 3186 India 91805275406 Israel 03 6120092 Italy 02 413091 Japan 03 5472 2970 Korea 02 596 7456 Mexico 5 280 7...

Page 3: ...service failures caused by owner s failure to follow the National Instruments installation operation or maintenance instructions owner s modification of the product owner s abuse misuse or negligent a...

Page 4: ...onal Instruments Application Software 1 3 NI DAQ Driver Software 1 4 Optional Equipment 1 5 Chapter 2 Installation and Configuration Software Installation 2 1 Unpacking 2 1 Hardware Installation 2 2 H...

Page 5: ...al Sources RSE Configuration 4 18 Single Ended Connections for Grounded Signal Sources NRSE Configuration 4 18 Common Mode Signal Rejection Considerations 4 19 Analog Output Signal Connections 4 19 Di...

Page 6: ..._OUT Signal 4 45 GPCTR0_UP_DOWN Signal 4 45 GPCTR1_SOURCE Signal 4 46 GPCTR1_GATE Signal 4 46 GPCTR1_OUT Signal 4 47 GPCTR1_UP_DOWN Signal 4 47 FREQ_OUT Signal 4 49 Field Wiring Considerations 4 49 Ch...

Page 7: ...gle Ended Input Connections for Ground Referenced Signals 4 19 Figure 4 9 Analog Output Connections 4 20 Figure 4 10 Digital I O Connections 4 21 Figure 4 11 Digital I O Connections Block Diagram 4 22...

Page 8: ...al Timing in Edge Detection Mode 4 47 Figure 4 40 GPCTR1_OUT Signal Timing 4 47 Figure 4 41 GPCTR Timing Summary 4 48 Figure B 1 68 Pin E Series Connector Pin Assignments B 3 Figure B 2 68 Pin Extende...

Page 9: ...es that the text following it applies only to a specific product a specific operating system or a specific software version This icon denotes a note which alerts you to important information This icon...

Page 10: ...PCI eXtensions for Instrumentation PXI is an open specification that builds off the CompactPCI specification by adding instrumentation specific features Related Documentation The following documents c...

Page 11: ...ut analog output and general purpose counter timer functions These groups include a total of seven 24 bit and three 16 bit counters and a maximum timing resolution of 50 ns The DAQ STC makes possible...

Page 12: ...t with the basic PCI interface on the CompactPCI bus Compatible operation is not guaranteed between CompactPCI devices with different sub buses nor between CompactPCI devices with sub buses and PXI Th...

Page 13: ...al Instruments Application Software LabVIEW features interactive graphics a state of the art user interface and a powerful graphical programming language The LabVIEW Data Acquisition VI Library a seri...

Page 14: ...sheet programs and word processors Using LabVIEW Measurement Studio or VirtualBench software greatly reduces the development time for your data acquisition and control application NI DAQ Driver Softwa...

Page 15: ...follows Cables and cable assemblies shielded and ribbon Connector blocks shielded and unshielded screw terminals RTSI bus cables SCXI modules and accessories for isolating amplifying exciting and mul...

Page 16: ...Chapter 1 Introduction 6023E 6024E 6025E User Manual 1 6 ni com For more information about these products refer to the National Instruments catalogue or web site or call the office nearest you...

Page 17: ...or your operating system and follow the instructions given there Unpacking Your device is shipped in an antistatic package to prevent electrostatic damage to the device Electrostatic discharge can dam...

Page 18: ...may be a tight fit but do not force the device into place 6 Screw the mounting bracket of the device to the back panel rail of the computer 7 Visually verify the installation 8 Replace the top cover o...

Page 19: ...fications makes these devices completely software configurable You must perform two types of configuration on the devices bus related and data acquisition related configuration The PCI devices are ful...

Page 20: ...on Memory PGIA Calibration Mux Analog Mode Multiplexer Analog Input Muxes Voltage REF Calibration DACs Dither Generator Calibration DACs 82C55A DAC0 DAC1 Analog Output Not on 6023E DAQ STC Analog Inpu...

Page 21: ...programmed on a per channel basis for multimode scanning For example you can configure the circuitry to scan 12 channels four DIFF channels and eight RSE channels Table 3 1 describes the three input...

Page 22: ...DIFF mode uses two analog input lines One line connects to the positive input of the programmable gain instrumentation amplifier PGIA of the device and the other connects to the negative input of the...

Page 23: ...lting in improved resolution For high speed applications not involving averaging or spectral analysis you may want to disable dithering to reduce noise Your software enables and disables the dithering...

Page 24: ...1 mV signal connects to channel 1 and suppose the PGIA is programmed to apply a gain of one to channel 0 and a gain of 100 to channel 1 When the multiplexer switches to channel 1 and the PGIA switche...

Page 25: ...1 k to perform high speed scanning Due to the previously described limitations of settling times resulting from these conditions multiple channel scanning is not recommended unless sampling rates are...

Page 26: ...nal I O mode 2 In modes 1 and 2 the three ports are divided into two groups group A and group B Each group has eight data bits plus control and status bits from Port C PC Modes 1 and 2 use handshaking...

Page 27: ...ection in this chapter and on the PFI pins as indicated in Chapter 4 Signal Connections Programmable Function Inputs Ten PFI pins are available on the device connector as PFI 0 9 and connect to the in...

Page 28: ...o use the internal timebase you can also program the device to drive its internal timebase over the RTSI bus to another device that is programmed to receive this timebase signal This clock source whet...

Page 29: ...0 ni com Figure 3 5 PCI RTSI Bus Signal Connection RTSI Bus Connector switch RTSI Switch Clock Trigger 7 DAQ STC TRIG1 TRIG2 CONVERT UPDATE WFTRIG GPCTR0_SOURCE GPCTR0_GATE GPCTR0_OUT STARTSCAN AIGATE...

Page 30: ...and 3 6 Table 3 3 Pins Used by PXI E Series Device PXIE Series Signal PXI Pin Name PXI J2 Pin Number RTSI 0 5 PXI Trigger 0 5 B16 A16 A17 A18 B18 C18 RTSI 6 PXI Star D17 RTSI Clock PXI Trigger 7 E16 R...

Page 31: ...connections I O Connector Figure 4 1 shows the pin assignments for the 68 pin I O connector on the PCI 6023E PCI 6024E and DAQCard 6024E Figure 4 2 shows the pin assignments for the 100 pin I O connec...

Page 32: ...ERVED DAC1OUT1 DAC0OUT1 ACH15 AIGND ACH6 ACH13 AIGND ACH4 AIGND ACH3 ACH10 AIGND ACH1 ACH8 DGND 1 Not available on the 6023E PFI8 GPCTR0_SOURCE PFI7 STARTSCAN GPCTR1_OUT PFI4 GPCTR1_GATE PFI3 GPCTR1_S...

Page 33: ...5 55 4 54 3 53 2 52 1 51 FREQ_OUT GND GPCTR0_OUT 5 V PFI9 GPCTR0_GATE GND PFI8 GPCTR0_SOURCE PA0 PFI7 STARTSCAN GND PFI6 WFTRIG PA1 PFI5 UPDATE GND GPCTR1_OUT PA2 PFI4 GPCTR1_GATE GND PFI3 GPCTR1_SOU...

Page 34: ...tput channel 1 AOGND Analog output ground the analog output voltages are referenced to this node All three ground references AIGND AOGND and DGND areconnected together on your device DGND Digital grou...

Page 35: ...TRIG2 DGND Input Output PFI1 Trigger 2 as an input this is one of the PFIs As an output this is the TRIG2 AI stop trigger signal In pretrigger applications a low to high transition indicates the initi...

Page 36: ...rt of each analog input scan in the interval scan A low to high transition indicates the start of the scan PFI8 GPCTR0_SOURCE DGND Input Output PFI8 Counter 0 Source as an input this is one of the PFI...

Page 37: ...6024E and 6025E only AO 0 1 Short circuit to ground 5 at 10 5 at 10 10 V s AOGND AO DGND DO VCC DO 0 1 Short circuit to ground 1A fused DIO 0 7 DIO Vcc 0 5 13 at Vcc 0 4 24 at 0 4 1 1 50 k pu PA 0 7...

Page 38: ...referenced PFI4 GPCTR1_GATE DIO Vcc 0 5 3 5 at Vcc 0 4 5 at 0 4 1 5 50 k pu GPCTR1_OUT DO 3 5 at Vcc 0 4 5 at 0 4 1 5 50 k pu PFI5 UPDATE DIO Vcc 0 5 3 5 at Vcc 0 4 5 at 0 4 1 5 50 k pu PFI6 WFTRIG DI...

Page 39: ...g system ground and is therefore already connected to a common ground point with respect to the device assuming that the computer is plugged into the same power system Non isolated outputs of instrume...

Page 40: ...re listed in the Protection column of Table 4 3 In NRSE mode the AISENSE signal connects internally to the negative input of the PGIA when their corresponding channels are selected In DIFF and RSE mod...

Page 41: ...e the signal to ground by using the RSE input mode or the DIFF input configuration with bias resistors see the Differential Connections for Nonreferenced or Floating Signal Sources section If you have...

Page 42: ...ing Ground Grounded Signal Source Examples Ungrounded Thermocouples Signal conditioning with isolated outputs Battery devices Examples Plug in instruments with nonisolated outputs V1 ACH V1 ACH ACH Se...

Page 43: ...nel for DIFF input each signal uses two multiplexer inputs one for the signal and one for its reference signal Therefore with a DIFF configuration for every channel up to eight analog input channels a...

Page 44: ...ut Connections for Ground Referenced Signals With this type of connection the PGIA rejects both the common mode noise in the signal and the ground potential difference between the signal source and th...

Page 45: ...e 4 6 shows two bias resistors connected in parallel with the signal leads of a floating signal source If you do not use the resistors and the source is truly floating the source is not likely to rema...

Page 46: ...oupled noise Also this configuration does not load down the source other than the very high input impedance of the PGIA You can fully balance the signal path by connecting another resistor of the same...

Page 47: ...als DIFF input connections are recommended for greater signal integrity for any input signal that does not meet the preceding conditions Using your software you can configure the channels for two diff...

Page 48: ...e input of the PGIA and connect the signal local ground reference to the negative input of the PGIA The ground point of the signal therefore connects to the AISENSE pin Any potential difference betwee...

Page 49: ...ce In addition with DIFF input connections the PGIA can reject common mode noise pickup in the leads connecting the signal sources to the device The PGIA can reject common mode signals as long as V in...

Page 50: ...nd DGND DIO 0 7 are the signals making up the DIO port and DGND is the ground reference signal for the DIO port You can program all lines individually as inputs or outputs Figure 4 10 shows signal con...

Page 51: ...utput Digital input applications include receiving TTL signals and sensing external device states such as the state of the switch shown in the Figure 4 11 Digital output applications include sending T...

Page 52: ...ent three 8 bit ports PA PB and PC You can program each port as an input or output port In Figure 4 11 port A of one PPI is configured for digital output and port B is configured for digital input Dig...

Page 53: ...n Note Table 4 4 shows both the port C signal assignments and the terminology correlation between different documentation sources The 82C55A terminology refers to the different 82C55A configurations a...

Page 54: ...of 0 4 VDC The DIO lines provide a maximum of 2 5 mA at 3 7 V in the high state Using the largest possible resistor ensures that you do not use more current than necessary to perform the pull down ta...

Page 55: ...g less drive current for other circuitry connected to this line The 7 1 k resistor reduces the amount of logic high source current by 0 4 mA with a 2 8 V output Timing Specifications 6025E only This s...

Page 56: ...becomes high when the 82C55A requests service during a data transfer You must set the appropriate interrupt enable bits to generate this signal RD Internal Read this signal is the read signal generate...

Page 57: ...mode 1 are shown in Figure 4 13 Figure 4 13 Timing Specifications for Mode 1 Input Transfer Name Description Minimum Maximum T1 STB Pulse Width 100 T2 STB 0 to IBF 1 150 T3 Data before STB 1 20 T4 ST...

Page 58: ...in mode 1 are shown in Figure 4 14 Figure 4 14 Timing Specifications for Mode 1 Output Transfer Name Description Minimum Maximum T1 WR 0 to INTR 0 250 T2 WR 1 to Output 200 T3 WR 1 to OBF 0 150 T4 ACK...

Page 59: ...Timing Specifications for Mode 2 Bidirectional Transfer Name Description Minimum Maximum T1 WR 1 to OBF 0 150 T2 Data before STB 1 20 T3 STB Pulse Width 100 T4 STB 0 to IBF 1 150 T5 Data after STB 1 5...

Page 60: ...omputer National Instruments is not liable for any damages resulting from such signal connections All external control over the timing of your device is routed through the 10 programmable function inp...

Page 61: ...O connector for different applications requiring alternative wiring You can individually enable each of the PFI pins to output a specific internal timing signal For example if you need the CONVERT sig...

Page 62: ...hat is controlled These requirements are listed in this chapter under the section for each applicable signal DAQ Timing Connections The DAQ timing signals are SCANCLK EXTSTROBE TRIG1 TRIG2 STARTSCAN C...

Page 63: ...400 to 500 ns pulse width and is software enabled Figure 4 19 shows the timing for the SCANCLK signal Figure 4 19 SCANCLK Signal Timing EXTSTROBE Signal EXTSTROBE is an output only signal that genera...

Page 64: ...for either rising or falling edge The selected edge of the TRIG1 signal starts the data acquisition sequence for both posttriggered and pretriggered acquisitions As an output the TRIG1 signal reflects...

Page 65: ...the TRIG2 signal initiates the posttriggered phase of a pretriggered acquisition sequence In pretriggered mode the TRIG1 signal initiates the data acquisition The scan counter indicates the minimum n...

Page 66: ...source for STARTSCAN and configure the polarity selection for either rising or falling edge The selected edge of the STARTSCAN signal initiates a scan The sample interval counter starts if you select...

Page 67: ...l Timing The CONVERT pulses are masked off until the device generates the STARTSCAN signal If you are using internally generated conversions the first CONVERT appears when the onboard sample interval...

Page 68: ...gnal is configured in the edge detection mode You can select any PFI pin as the source for CONVERT and configure the polarity selection for either rising or falling edge The selected edge of the CONVE...

Page 69: ...ly input the AIGATE signal which is not available as an output on the I O connector The AIGATE signal can mask off scans in a DAQ sequence You can configure the PFI pin you select as the source for th...

Page 70: ...0 MHz or 100 kHz internal timebase generates the SISOURCE signal unless you select some external source Figure 4 29 shows the timing requirements for the SISOURCE signal Figure 4 29 SISOURCE Signal Ti...

Page 71: ...uirements for the WFTRIG signal Figure 4 30 WFTRIG Input Signal Timing Figure 4 31 WFTRIG Output Signal Timing UPDATE Signal Any PFI pin can externally input the UPDATE signal which is available as an...

Page 72: ...ns of the leading edge Separate the UPDATE pulses with enough time that new data can be written to the DAC latches The device UI counter normally generates the UPDATE signal unless you select some ex...

Page 73: ...some external source General Purpose Timing Signal Connections The general purpose timing signals are GPCTR0_SOURCE GPCTR0_GATE GPCTR0_OUT GPCTR0_UP_DOWN GPCTR1_SOURCE GPCTR1_GATE GPCTR1_OUT GPCTR1_UP...

Page 74: ...CTR0_GATE pin As an input the GPCTR0_GATE signal is configured in the edge detection mode You can select any PFI pin as the source for GPCTR0_GATE and configure the polarity selection for either risin...

Page 75: ...or both options This output is set to high impedance at startup Figure 4 37 shows the timing of the GPCTR0_OUT signal Figure 4 37 GPCTR0_OUT Signal Timing GPCTR0_UP_DOWN Signal This signal can be exte...

Page 76: ...nts for the GPCTR1_SOURCE signal Figure 4 38 GPCTR1_SOURCE Signal Timing The maximum allowed frequency is 20 MHz with a minimum pulse width of 23 ns high or low There is no minimum frequency limitatio...

Page 77: ...neral purpose counter 1 You have two software selectable output options pulse on TC and toggle output polarity on TC The output polarity is software selectable for both options This output is set to h...

Page 78: ...rammed to count falling edges The GATE input timing parameters are referenced to the signal at the SOURCE input or to one of the internally generated signals on your device Figure 4 41 shows the GATE...

Page 79: ...y the numbers 1 through 16 The input clock of the frequency generator is software selectable from the internal 10 MHz and 100 kHz timebases The output polarity is software selectable This output is se...

Page 80: ...nd least accurate whereas the last level is the slowest most difficult and most accurate Loading Calibration Constants Your device is factory calibrated before shipment at approximately 25 C to the le...

Page 81: ...discussed in the following section If you are interested primarily in relative measurements you can ignore a small amount of gain error and self calibration should be sufficient External Calibration Y...

Page 82: ...ied to that channel This calibration mechanism is designed to work only with the internal 10 V reference Thus in general it is not possible to calibrate the analog output gain error when using an exte...

Page 83: ...t Characteristics Number of channels 16 single ended or 8 differential software selectable per channel Type of ADC Successive approximation Resolution 12 bits 1 in 4 096 Sampling rate 200 kS s guarant...

Page 84: ...872 0 0914 6 38 3 91 0 975 0 0010 16 504 5 89 1 28 5 5 0 0272 0 0314 3 20 1 95 0 488 0 0005 5 263 2 95 0 642 0 5 0 5 0 0872 0 0914 0 340 0 195 0 049 0 0010 0 846 0 295 0 064 0 05 0 05 0 0872 0 0914 0...

Page 85: ...calibration 28 mV max Postgain error after calibration 0 5 mV max Postgain error before calibration 100 mV max Gain error relative to calibration reference After calibration gain 1 0 02 of reading max...

Page 86: ...mmended warm up time 15 min Offset temperature coefficient Pregain 15 V C Postgain 240 V C Gain temperature coefficient 20 ppm C Analog Output 6024E and 6025E only Output Characteristics Number of cha...

Page 87: ...ibration 0 3 LSB typ 1 0 LSB max Before calibration 3 LSB max Monotonicity 12 bits guaranteed after calibration Offset error After calibration 1 0 mV max Before calibration 200 mV max Gain error relat...

Page 88: ...nd Power on state steady state 200 mV Initial power up glitch Magnitude 1 1 V Duration 2 0 ms Power reset glitch Magnitude 2 2 V Duration 4 2 s Dynamic Characteristics Settling time for full scale ste...

Page 89: ...ers Programmed I O PA 0 7 PB 0 7 PC 0 7 6025E only Digital logic levels Level Min Max Input low voltage Input high voltage Input low current Vin 0 V Input high current Vin 5 V 0 V 2 V 0 8 V 5 V 320 A...

Page 90: ...ming I O Number of channels 2 up down counter timers 1 frequency scaler Resolution Counter timers 24 bits Frequency scalers 4 bits Compatibility TTL CMOS Base clocks available Counter timers 20 MHz 10...

Page 91: ...year External calibration reference 6 and 10 V Onboard calibration reference Level 5 000 V 3 5 mV actual value stored in EEPROM Temperature coefficient 5 ppm C max Long term stability 15 ppm Power Req...

Page 92: ...Section 4 5 5 4 1 Half sine shock pulse 11 ms duration 30 g peak 30 shocks per face Operational random vibration 5 to 500 Hz 0 31 grms 3 axes Storage Environment Ambient temperature 20 to 70 C Relati...

Page 93: ...roximation Resolution 12 bits 1 in 4 096 Sampling rate 200 kS s guaranteed Input signal ranges Bipolar only Input coupling DC Max working voltage signal common mode Each input should remain within 11...

Page 94: ...of reading max Nominal Range V Absolute Accuracy Relative Accuracy of Reading Offset mV Noise Quantization mV Temp Drift C Absolute Accuracy at Full Scale mV Resolution mV Positive FS Negative FS 24 H...

Page 95: ...current 100 pA CMRR DC to 60 Hz Gain 0 5 1 0 85 dB Gain 10 100 90 dB Dynamic Characteristics Bandwidth Settling time for full scale step 5 s max to 1 0 LSB accuracy System noise LSBrms not including q...

Page 96: ...med I O Accuracy Information Transfer Characteristics Relative accuracy INL After calibration 0 5 LSB typ 1 0 LSB max Before calibration 4 LSB max DNL After calibration 0 5 LSB typ 1 0 LSB max Before...

Page 97: ...ion 0 75 of output max Voltage Output Range 10 V Output coupling DC Output impedance 0 1 max Current drive 5 mA max Protection Short circuit to ground Power on state steady state 200 mV Initial power...

Page 98: ...logic levels Power on state Input High Z 50 k pull up to 5 VDC Data transfers Programmed I O Timing I O Number of channels 2 up down counter timers 1 frequency scaler Resolution Counter timers 24 bits...

Page 99: ...transfers Interrupts programmed I O Triggers Digital Trigger Compatibility TTL Response Rising or falling edge Pulse width 10 ns min Calibration Recommended warm up time 30 min Interval 1 year Extern...

Page 100: ...sical PC card type Type II I O connector 68 position VHDCI female connector Environment Operating temperature 0 to 40 C with a maximum internal device temperature of 70 C as measured by onboard temper...

Page 101: ...or the analog input signals shielded twisted pair wires for each analog input pair yield the best results assuming that you use differential inputs Tie the shield for each signal pair to the ground re...

Page 102: ...National Instruments Optional Connectors The following table shows the optional connector and cable assembly combinations you can use for each device Device Connector Cable Assembly PCI 6023E 6024E 6...

Page 103: ...DIO4 RESERVED DAC1OUT1 DAC0OUT1 ACH15 AIGND ACH6 ACH13 AIGND ACH4 AIGND ACH3 ACH10 AIGND ACH1 ACH8 DGND 1 Not available on the 6023E PFI8 GPCTR0_SOURCE PFI7 STARTSCAN GPCTR1_OUT PFI4 GPCTR1_GATE PFI3...

Page 104: ...N C N C N C N C N C N C 5 V PA0 GND PA2 PA3 GND PA5 PA6 GND PB0 PB1 GND GND PB4 PB5 GND PB7 PC0 GND PC2 PC3 GND PC5 PC6 GND N C N C N C N C N C N C N C N C N C GND GND PA1 GND GND PA4 GND GND PA7 GND...

Page 105: ...CTR1_SOURCE PFI1 TRIG2 EXTSTROBE 5 V DGND DIO3 DIO2 DIO1 DIO0 AOGND DAC1OUT1 AISENSE ACH7 ACH6 ACH5 ACH4 ACH3 ACH2 ACH1 ACH0 AIGND FREQ_OUT PFI7 STARTSCAN PFI5 UPDATE PFI2 CONVERT PFI0 TRIG1 SCANCLK 5...

Page 106: ...n Extended Digital Input Connector Pin Assignments 5 V PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 GND GND GND GND GND GND GND GND GND GND GND GND G...

Page 107: ...e the groups independently with timing resolutions of 50 ns or 10 s With the DAQ STC you can interconnect a wide variety of internal timing signals to other internal blocks The interconnection scheme...

Page 108: ...tibles version 6 9 or higher Analog Input and Output I m using my device in differential analog input mode and I have connected a differential input signal but my readings are random and drift rapidly...

Page 109: ...signal source set to AO Update 2 Set up data acquisition timing so that the timing signal for A D conversion comes from PFI5 as follows If you are using NI DAQ call Select_Signal deviceNumber ND_IN_C...

Page 110: ...ll internal timing signals If you are using the NI DAQ language interface or LabWindows CVI use the Select_Signal function to route internal signals to the I O connector route external signals to inte...

Page 111: ...ents Corporation C 5 6023E 6024E 6025E User Manual after power on and Table 4 3 I O Signal Summary shows that there is a 50 k pull up resistor This pull up resistor sets the DIO 0 pin to a logic high...

Page 112: ...ss the latest example programs system configurators tutorials technical news as well as a community of developers ready to share their own techniques Customer Education National Instruments provides a...

Page 113: ...eb sites from the Worldwide Offices section of ni com Branch office web sites provide up to date contact information support phone numbers e mail addresses and current events If you have searched the...

Page 114: ...ry Prefix Meanings Value p pico 10 12 n nano 10 9 micro 10 6 m milli 10 3 k kilo 103 M mega 106 G giga 109 t tera 1012 Numbers Symbols degree greater than less than negative of or minus ohm per percen...

Page 115: ...log input ground signal AISENSE analog input sense signal ANSI American National Standards Institute AO analog output AOGND analog output ground signal ASIC Application Specific Integrated Circuit a p...

Page 116: ...re grouped to form ports CMRR common mode rejection ratio a measure of the ability of a differential amplifier to reject interference from a common mode signal usually expressed in decibels dB CONVERT...

Page 117: ...are tied to a ground reference whose voltage difference is amplified differential input the two terminal input to a differential amplifier DIO digital input output dithering the addition of Gaussian...

Page 118: ...batteries transformers or thermocouples FREQ_OUT frequency output signal ft feet G g grams gain the factor by which a signal is amplified sometimes expressed in decibels GATE gate signal glitch an un...

Page 119: ...D A transfer characteristic of the analog I O circuitry input bias current the current that flows into the inputs of a circuit input impedance the measured resistance and capacitance between the input...

Page 120: ...ode library a file containing compiled object modules each comprised of one of more functions that can be linked to other object modules that make use of these functions NIDAQMSC LIB is a library that...

Page 121: ...ment system reference but the voltage at this reference can vary with respect to the measurement system ground O OUT output pin a counter output pin where the counter can generate various TTL pulse wa...

Page 122: ...inite resolution of the conversion process R referenced signal sources signal sources with voltage signals that are referenced to a system ground such as the earth or a building ground Also called gro...

Page 123: ...number of input samples in a scan is equal to the number of channels in the input group For example one scan acquires one new sample from every analog input channel in the group scan clock the clock...

Page 124: ...controller synchronous 1 hardware a property of an event that is synchronized to a reference clock 2 software a property of a function that begins an operation and returns only when the operation is...

Page 125: ...in the group update rate the number of output updates per second V V volts Vcc positive supply voltage VDC volts direct current VI virtual instrument 1 a combination of hardware and or software elemen...

Page 126: ...veform multiple voltage readings taken at a specific sampling rate WFTRIG waveform generation trigger signal working voltage the highest voltage that should be applied to a product in normal use norma...

Page 127: ...mode 4 10 description table 4 4 signal summary table 4 7 AISENSE signal description table 4 4 NRSE mode 4 10 signal summary table 4 7 analog input available input configurations table 3 3 common ques...

Page 128: ...nsfer characteristics A 14 to A 15 voltage output A 15 AOGND signal analog output signal connections 4 19 to 4 20 description table 4 4 signal summary table 4 7 B bipolar input 3 3 block diagrams 6023...

Page 129: ...ons 4 20 to 4 21 signal summary table 4 7 DIFF mode description table 3 3 recommended configuration figure 4 12 differential connections 4 13 to 4 16 ground referenced signal sources 4 14 nonreference...

Page 130: ...4 46 GPCTR1_UP_DOWN signal 4 47 to 4 49 glitch analog output 3 6 GPCTR0_GATE signal 4 44 to 4 45 GPCTR0_OUT signal description table 4 6 general purpose timing signal connections 4 45 signal summary...

Page 131: ...nments figure B 6 68 pin E Series connector pin assignments figure B 3 68 pin extended digital input connector pin assignments figure B 4 pin assignments table 6023E 6024E 4 2 6025E 4 3 L LabVIEW and...

Page 132: ...WFTRIG signal description table 4 6 signal summary table 4 8 PFI7 STARTSCAN signal description table 4 6 signal summary table 4 8 PFI8 GPCTR0_SOURCE signal description table 4 6 signal summary table 4...

Page 133: ...formation C 1 installation and configuration C 2 timing and digital I O C 3 to C 5 R RD signal description table 4 26 mode 1 input timing figure 4 27 mode 2 bidirectional timing figure 4 29 referenced...

Page 134: ...ons 4 25 to 4 29 timing connections 4 30 to 4 49 DAQ timing connections 4 32 to 4 40 general purpose timing signal connections 4 43 to 4 49 programmable function input connections 4 31 to 4 32 wavefor...

Page 135: ...GPCTR0_OUT signal 4 45 GPCTR0_SOURCE signal 4 43 to 4 44 GPCTR0_UP_DOWN signal 4 45 GPCTR1_GATE signal 4 46 to 4 47 GPCTR1_OUT signal 4 47 GPCTR1_SOURCE signal 4 46 GPCTR1_UP_DOWN signal 4 47 to 4 49...

Page 136: ...d PXI buses A 6 PCMCIA bus A 15 W waveform generation questions about C 2 to C 3 waveform generation timing connections 4 40 to 4 43 UISOURCE signal 4 42 to 4 43 UPDATE signal 4 41 to 4 42 WFTRIG sign...

Search results

Summary of Contents for 6023E

Reviews:

Brands by name

Popular brands

National Instruments 6023E, User Manual

Search results

Summary of Contents for 6023E

Reviews:

Brands by name

Popular brands