National Instruments 5772R, User Manual And Specifications, Page: 8 / 34

Block Diagrams
The following figure shows the NI 5772 block diagram and signal flow.
Figure 3. NI 5772 Connector Signals and NI 5772 CLIP Signal Block Diagram
TRIG
NI 5772 Adapter Module
AI 0
AI 1
A
UX I/O
Analog
In
Path
ADC Clock
ADC Data
SClk
I2C (Shared)
Example
VI* Sda
ADC Control
ADC12D800RF
LabVIEW FPGA CLIP
Analog
In
Path
AD7291
Temperature
Sensor
REF IN
ADC Clock
ADC Data
ADC
Interface
ADC
Interface
AI 0 Data
<N..N-3>
AI 1 Data
<N..N-3>
AI 0 Data Over Range
<N..N-3>
AI 1 Data Over Range
<N..N-3>
16
16 12
12
Trigger Input (Sync & Async)
Trigger Output
Trigger WE
ADC12D800RF
DIO Port 1 WE Request
DIO Port 1 Rd Data <0...3>
DIO Port 1 Wr Data <0...3>
DIO Port 1 WE Actual
PFI <0...3> WE
PFI <0...3> Rd Data
PFI <0...3> Wr Data
DIO Port 0 WE Request
DIO Port 0 Rd Data <0...3>
DIO Port 0 Wr Data <0...3>
DIO Port 0 WE Actual
CLK IN
Clk Control
PLL Locked
PLL
HMC 703
PLL Loop
Filter
800 MHz
VCO
Enable PLL
Sync Clock
(IoModSyncClk)
User Command Idle
User Data
User Command Status
User Return
User Error
PLL Locked
Initialization Done
SPI Device Select
SPI Write
SPI Write Data
SPI Address
SPI Read Data
SPI Idle
Configuration
Engine
User Command
User Command Commit
SPI Read
Vconstant
(Free-Running)
I2C (Shared)
I2C (Shared)
Related Information
Using Your NI 5772R with a LabVIEW FPGA Example VI on page 12
8 | NI 5772R User Manual and Specifications | ni.com