Configuration and Installation
Chapter 2
SCXI-1162 User Manual
2-22
© National Instruments Corporation
2. Clear SLOT0SEL* to 0. This will deassert all SS* lines to all modules in all chassis.
3. For each bit, starting with the MSB, perform the following action:
a. Set SERDATIN = bit to be sent. These bits are the data that are being written to the
Slot-Select Register.
b. SERCLK = 0.
c. SERCLK = 1. This rising edge clocks the data.
4. Set SLOT0SEL* to 1. This will assert the SS* line of the module whose slot number was
written to Slot 0. If multiple chassis are being used, only the appropriate slot in the chassis
whose address corresponds to the written chassis number will be selected. When no
communication is taking place between the data acquisition board and any modules, write
zero to the Slot-Select Register to ensure that no accidental writes occur.
Figure 2-8 shows the timing requirements on the SERCLK and SERDATIN signals. You must
observe these timing requirements for all communications. T
delay
is a specification of the
SCXI-1162.
Tlow
Thigh
SERCLK
SERDATIN
SERDATOUT
Tsetup
Thold
Tdelay
Tlow
Minimum low time
65 nsec minimum
Thigh
Minimum high time
400 nsec minimum
Tsetup
SERDATIN setup time
200 nsec minimum
Thold
SERDATIN hold time
200 nsec minimum
Tdelay
SERDATOUT delay
450 nsec maximum
Figure 2-8. Serial Data Timing Diagram
After selecting the module slot as previously described, you must write first to the Address
Handler, then to the register of interest, for each read cycle from the module.
