© National Instruments Corporation
4-1
SCXI-1162 User Manual
Chapter 4
Register Descriptions
This chapter describes in detail the SCXI-1162 Address Handler, the Module ID Register, the
Data Register, the Parking Register, and the Slot 0 Registers.
Note: If you plan to use a programming software package such as NI-DAQ, LabWindows, or
LabVIEW with your SCXI-1162 board, you do not need to read this chapter.
Register Description
Register Description Format
This register description chapter discusses each of the SCXI-1162 registers and the Slot 0
registers. A detailed bit description of each register is given. The individual register description
gives the type, word size, and bit map of the register, followed by a description of each bit.
The register bit map shows a diagram of the register with the MSB shown on the left (bit 31 for a
32-bit register, bit 15 for a 16-bit register, and bit 7 for an 8-bit register) and the LSB shown on
the right (bit 0). A rectangle is used to represent each bit. Each bit is labeled with a name inside
its rectangle. An asterisk (*) after the bit name indicates that the bit is inverted (negative logic).
The Module ID register has a unique format and is described in the Module ID Register section.
In some of the registers, several bits are labeled with an X, indicating don't care bits. When you
write to a register, you may set or clear these bits without effect.
SCXI-1162 Registers
The SCXI-1162 is a class II module. It has an address handler that chooses one of three registers.
The Module ID Register is a 4-byte read-only register that contains the Module ID number of the
SCXI-1162. The Data Register is a 32-bit write-only register you use to control the output states
on the SCXI-1162. The Parking Register is a dummy register located at address FFFF. The
Address Handler is a write-only register that contains the address of the register to be read from
or written to.
Address Handler
You must write to the Address Handler at the beginning of each read from the SCXI-1162.
Write the address of the register of interest to this handler, which in turn enables the register of
interest. The Address Handler is two bytes long and contains the address of the register to be
read from or written to. The Address Handler is selected when SS* is asserted low and D*/A
indicates an address transfer (D*/A is high). At this time, the address is shifted in the Address
Handler Register, MSB first. Table 4-1 contains a list of register addresses.
