NAT-MCH Clock-PCB – Technical Reference Manual
Version 1.4
© N.A.T. GmbH
34
11.3.8 Source Selection 2 Register
The value of the Source Selection 2 Register decides which output (of the PLL) is connected
to the CLK2 Transceiver.
Table 17:
SRC_SEL2 Register
Source Selection 2 – Address 0x07
Default value 0x00
Bit
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Func -
-
-
SRC_SEL_CLK2
Table 18:
SRC_SEL2 - Register Bits
Bit
Name
Function
[4..0] SRC_SEL_
CLK2
Selects the output of the PLL which is connected to
CLK2
0x01 – C19o
0x02 – #C16o
0x03 – C8/C32o
0x04 – #C4/C65o
0x05 – C2o
0x06 – C1.5o
0x07 – C3o
0x08 – C6/8.4/34/44o
0x09 – F16o
0x0B – PLL_REF0
0x0C – PLL_REF1
0x0D – EXTREF_IN
0x0E – TIC_100u
0x0F – RES (do not use!)
0x10 – RES (do not use!)
0x11 – SW_CLK
0x12 – SYNC_CLK
0x13 – 20MHz (stratum3)
0x14 – holdover
all other values result in no connection
[7..5] -
no function
write as 0 and ignore when read
The SRC_SEL bits in combination with the OUTSEL bits (refer to the PLL Control 2
Register) set the frequency, which is transmitted to the AMCs.
