Motorola PPC/PMC-8260/DS1, Reference Manual, Page: 120 / 150

SSRAM Information for Support Package Programmers Memory Map and Devices
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SSRAM Information for Support Package Programmers
The PPC/PMC-8260/DS1 module provides 1 MByte on-board Synchronous Burst
SRAM (SSRAM) which is 32-bit wide and clocked at 66 MHz. This SSRAM is
connected to the local bus (32-bit wide data, 18-bit wide address) of the Power-
QUICC II processor. The 18-bit wide address local bus has an accessible memory
space of 256 KByte. Therefore, to realize the access to 1 MByte SSRAM four chip
select signals are consumed, each accessing 256 KByte of memory space. The two
missing high order address bits are generated out of the four chip select signals by
external glue logic on the PPC/PMC-8260/DS1.
The access time of the SSRAM is 10 ns. The SSRAM supports single-read, single-
write, burst-read, and burst-write access (parity generation and check is supported
as a boot option).
Note: The local bus does not burst when accessed from the PowerQUICC II
core or from the external master (PCI bridge PowerSPAN II). Therefore, re-
gions that are accessed across the 60x bridge to local bus must be marked as
cache-inhibited in the PowerQUICC II core MMU. Otherwise these burst ac-
cesses will be terminated with a machine check exception. The local bus uses
bursts of 32 byte for certain CPM Serial DMA (SDMA) and Independent
DMA (IDMA) accesses. As the local bus is only 32-bits wide, it performs an
eight-beat burst.
Table 29: SSRAM Timing Performance at 66 MHz (T=15.15 nsec)
Read/Write Without Parity (Default Setting) With Parity (Boot Option)
4-Byte Single Read 3 clocks 4 clocks
4-Byte Single Write 2 clocks 2 clocks
32-Byte Burst Read 3:1:3:1:3:1:3:1
(16 clocks) 4:2:2:2:2:2:2:2
(18 clocks)
32-Byte Burst Write 2:1:1:1:2:1:1:1
(10 clocks) 2:1:1:1:2:1:1:1
(10 clocks)
The SSRAM is accessible from the PowerQUICC II or the PCI bus via Power-
SPAN II.