Motorola PPC/PMC-8260/DS1, Reference Manual, Page: 113 / 150

Memory Map and Devices PowerSPAN II PCI Bus Bridge
PPC/PMC-8260/DS1 5 - 9
PowerSPAN II PCI Bus Bridge
The Tundra semiconductor PowerSPAN II chip is the bridge between the PCI bus
and the PowerQUICC II Processor Bus (PowerPC Bus or 60x bus).
The main features of the PowerSPAN II are:
• Processor Bus (PB) interface (also called 60x bus)
• PCI interface
• Four DMA controllers
• Mailboxes and doorbell capabilities
The following table shows the PowerSPAN II access from 60x and PCI bus.
Table 24: PowerSPAN II Access from 60x Bus
Device Size Width 60x Address Note
PowerSPAN II
registers 4 KByte 64 bit Programmable Decoded by Power-
SPAN II
PCI bus Programmable 64 bit Programmable Decoded by Power-
SPAN II
60x Bus Arbiter
On the PPC/PMC-8260/DS1 the PowerQUICC II internal arbiter is used as 60x-
bus arbiter. Therefore, if you want to change the access priorities of devices, for ex-
ample, you have to program the PowerQUICC II internal arbiter because the Pow-
erSPAN II 60x bus arbiter is not used.
E
2
PROM Contents
The PowerSPAN II’s I
2
C controller has a two-wire interface (Serial Data and Serial
Clock lines) which connects to a serial E
2
PROM.
Certain registers of the PowerSPAN II can be programmed at system reset by data
stored in the E
2
PROM. This allows, for example, to configure interrupts as input or
output and to set unique identifiers for cards on the PCI bus at reset and various im-
age parameters and addresses. Configuring the PowerSPAN II with the E
2
PROM
allows PowerSPAN II to boot up as a Plug and Play-compatible device. Power-
SPAN II supports reads from and writes to the E
2
PROM. The PowerSPAN II has a
master-only I
2
C bus-compatible interface that is used for the initialization of regis-
ters and for reading and writing PCI Vital Product Data (VPD). The PowerSPAN II