manualshive.com logo in svg

Motorola PPC/CPCI-690, Reference Manual, Page: 55 / 176

Share
Download
Motorola PPC/CPCI-690 Reference Manual Download Page 55

Installation

Switch Settings

PPC/CPCI-690

2 - 13

 

Switch Settings

The board provides three configuration switches, SW1, SW2, and SW4. 

Figure 6:

Location of Switches

For default settings, the white switches are moved to the OFF position.

Caution

• Board malfunction

Changing the setting of switches marked as ‘reserved’ causes the 
board to malfunction. 
Do not change the settings of switches marked as ‘reserved’ for they 
might carry production-related functions.

• Boot block damage

If you change the boot flash write protection you may unintentionally 
overwrite boot flash 2.
Only change the boot flash write protection if it is explicitly stated.

• Board damage

Setting/resetting the switches during operation causes board damage. 
Therefore, check and change switch settings before you install the 
board.

• Data loss and board malfunction

Disabling the PCI bus 0 reset and resetting the board when data trans-
fer via SENTINEL is performed result in data loss and malfunction of 
the board. 
Only operate the board with SW2-4 in its default position (OFF).

Summary of Contents for PPC/CPCI-690

Page 1: ...PPC CPCI 690 Reference Guide P N 227356 Revision AC June 2006 ...

Page 2: ...ntent hereof without obligation of Motorola to notify any person of such revision or changes Electronic versions of this material may be read online downloaded for personal use or referenced in another document as a URL to the Motorola Embedded Communications Computing Web site The text itself may not be published commercially in print or electronic form edited translated or otherwise altered with...

Page 3: ...her Sources of Information Safety Notes Sicherheitshinweise 1 Introduction About this Manual 1 3 Organization of this Manual 1 3 Feedback 1 4 Features 1 5 Standard Compliance 1 6 Ordering Information 1 7 Product Nomenclature 1 7 Order Numbers 1 7 ...

Page 4: ... 2 11 IDE Devices 2 12 Rear Transition Board 2 12 Switch Settings 2 13 Board Installation 2 16 Installation in a Nonpowered System 2 17 Installation Procedure 2 17 Removal Procedure 2 18 Installation in a Powered System Supporting Hot Swap 2 18 Man Machine Interface 2 19 Signals 2 19 Installation Procedure 2 19 Removal Procedure 2 20 3 Controls Indicators and Connectors Front Panel 3 3 PMC Cutouts...

Page 5: ...OST Results 4 5 Setting Boot Parameters 4 6 Selecting the Boot Device 4 8 Autoboot 4 10 Restoring Default Values 4 11 Command Set 4 12 Testing 4 14 atatest 4 14 bt 4 15 dread 4 17 drw 4 18 dwrite 4 19 Setting 4 20 baud 4 20 cache 4 21 execute 4 21 m 4 22 setboot 4 24 setcpci 4 25 userled 4 26 wdog 4 26 Copying 4 27 bm 4 27 nvramrd 4 27 nvramwr 4 28 ...

Page 6: ... config_wr 4 36 eeprom_read 4 37 eeprom_write 4 38 fprog 4 39 ipmi_flsupd 4 40 ipmi_request 4 41 lo 4 41 netload 4 43 netsave 4 45 Reset 4 47 hreset 4 47 reset 4 48 Miscellaneous 4 49 bf 4 49 bs 4 50 bv 4 51 ferase 4 52 go 4 53 5 Buses Block Diagram 5 3 System Controller 5 4 Ethernet Ports 5 4 Serial Ports 5 4 Watchdog 5 5 PPC Bus 5 6 Memory Bus 5 7 ...

Page 7: ...M 5 14 IPMI Controller 5 15 Temperature Sensor 5 16 I2C Bus Slave Addresses 5 17 Available IPMI Drivers 5 17 Local I2C Buses 5 18 Discovery I2C Bus 5 18 SENTINEL I2C Bus 5 19 6 Maps and Registers Overview 6 3 Address Maps 6 4 Interrupt Map 6 6 Interrupt Controller 6 6 System Controller MPP Configuration 6 6 External Interrupt Sources 6 8 ...

Page 8: ...ister 6 10 Software Reset Register 6 11 Miscellaneous Status Register 6 11 Switch Status Register 6 12 Memory Configuration Register 6 13 Last Reset Status Register 1 6 14 Last Reset Status Register 2 6 15 A Battery Exchange B Troubleshooting Index ...

Page 9: ...oard Upgrades and Accessories Combinations 2 8 Table 7 Switch Settings 2 14 Controls Indicators and Connectors Table 8 Description of Front Panel LEDs 3 6 PowerBoot Table 9 POST Bit Layout Results 4 5 Table 10 Setboot Options 4 6 Table 11 Boot Source Prerequisites 4 8 Table 12 Command Set Overview 4 12 Table 13 BT Test Types 4 15 Table 14 Navigation Commands 4 22 Buses Table 15 Memory Bus Characte...

Page 10: ...essor Memory Address Map 6 4 Table 26 PCI Memory Address Map 6 5 Table 27 I2C Address Map 6 5 Table 28 MPP and GPP Register Settings 6 6 Table 29 System Controller MPP Configuration 6 7 Table 30 External Interrupt Sources 6 8 Table 31 LED Control Register 6 10 Table 32 Software Reset Register 6 11 Table 33 Miscellaneous Status Register 6 11 Table 34 Switch Status Register 6 12 Table 35 Memory Conf...

Page 11: ...6 Figure 8 Button on Handle 2 21 Controls Indicators and Connectors Figure 9 Compatibility Glyphs for CompactPCI Standard and PSB Board Variants 3 3 Figure 10 CompactPCI Standard and PSB Front Panel 3 3 Figure 11 Ethernet 1 Connector Pinout 3 7 Figure 12 COM 1 and 2 Connector Pinout 3 7 Figure 13 Location of CompactPCI Connectors 3 8 Figure 14 J3 Connector Pinout 3 9 Figure 15 J5 Connector Pinout ...

Page 12: ...xii PPC CPCI 690 Battery Exchange Figure 19 Battery Location A 3 Figure 20 Dot Position on BatteryA 4 ...

Page 13: ...e 0 through F e g used for addresses and offsets 00002 Same for binary numbers digits are 0 and 1 x Generic use of a letter n Generic use of numbers n nn Decimal point indicator is signalled Bold Character format used to emphasize a word Courier Character format used for on screen output Courier Bold Character format used to characterize user input Italics Character format for references table and...

Page 14: ...IB Board Information Block BMC Baseboard Management Controller CAS Column Address Select COP Common On Chip Processor CPCI Compact Peripheral Component Interconnect CPU Central Processing Unit DRAM Dynamic Random Access Memory ECC Error Checking and Correction EPROM Erasable Programmable Read Only Memory ESD Electrostatic Discharge FIFO First In First Out GND Ground GPP General Purpose Pins I2C In...

Page 15: ...r PLD Programmable Logic Device PM Peripheral Management Controller PMC PCI Mezzanine Card PROM Programmable Read Only Memory PSB Packet Switching Backplane PTC Positive Temperature Coefficient RAM Random Access Memory RARP Reverse Address Resolution Protocol ROM Read Only Memory RTB Rear Transition Board RTC Real Time Clock SBC Single Board Computer SDR Sensor Data Record SDRAM Synchronous Dynami...

Page 16: ...xvi PPC CPCI 690 SRAM Static RAM TPE Twisted Pair Ethernet UART Universal Asynchronous Receiver Transmitter ...

Page 17: ...e 2 8 modified Figure 4 PMC Connectors and Slots page 2 10 added safety notes to Switch Settings page 2 13 changed SW2 4 from reserved to PCI bus 0 reset removed section Testing the Board removed note from Front Panel page 3 3 and modified figure modified Figure 12 COM 1 and 2 Connec tor Pinout page 3 7 corrected Figure 15 J5 Connector Pinout Rows A to C page 3 10 changed Pin D15 from CPCI_IPMB1_C...

Page 18: ...isters that are imple mented in logic page 5 14 changed description of Table 21 Slave Addresses of Devices Attached to IPMI Controller s I2C Buses page 5 17 removed description of Table 22 On Board I2C Devices page 5 18 changed RTB BIB to RTB ID ROM in Table 23 Off Board I2C Devices page 5 18 modified Figure 18 Connection to I2C Devices page 5 19 added section Interrupt Map page 6 6 added bit 6 to...

Page 19: ...4 39 netload page 4 43 netsave page 4 45 bs page 4 50 ferase page 4 52 changed examples 1 3 on page 4 43 changed example screen out put in help page 4 31 added informa tion on 750GX CPU to PPC Bus page 5 6 modified section Memory Bus page 5 7 added 750GX CPU to section Interrupt Map page 6 6 Editorial changes 223827 AA July 2004 Replaced IPMI firmware update procedure in ipmi_flsupd with reference...

Page 20: ...I Firmware for PPC CPCI 690 and PPC CPCI 695 Installation Guide Only available via Motorola literature cata log Galileo marvell com prod ucts communica tion discovery GT 64260A jsp GT 64260A System Controller for PowerPC Processors Intel intel com search for 28F128J3A and 28F640J3A 28F128J3A 28F640J3A 3 Volt StrataFlash Memory IBM ibm com search for PowerPC 750FX RISC Micro processor PowerPC 750FX...

Page 21: ...ardware Reference Manual PMC233 4 5 PMC243 4 5 High Capacity Disk Solu tions Samsung samsungsemi com search for K4S560832C K4S560832C 256MBit LVTTL SDRAM Vitesse vitesse com search for VSC215 VSC215 Baseboard Management Controller Company www Document ...

Page 22: ...xxii PPC CPCI 690 ...

Page 23: ...is meant to complete the knowledge of a specialist and must not be taken as replace ment for qualified personnel EMC The board has been tested in a standard Motorola system and found to comply with the limits for a Class A digital device in this system pursu ant to part 15 of the FCC Rules respectively EN 55022 Class A These lim its are designed to provide reasonable protection against harmful int...

Page 24: ...ting hot swap or high availability causes board damage and data loss Therefore only install or remove it from a powered system if the system itself supports hot swap or high availability and if the system documen tation explicitly includes appropriate guidelines Installing the board under hot swap conditions in and removing it from system slots causes board damage and data loss Therefore only inst...

Page 25: ... Expansion Only replace or expand components or system parts with those recom mended by Motorola Otherwise you are fully responsible for the impact on EMC and the possibly changed functionality of the product Check the total power consumption of all components installed see the technical specification of the respective components Ensure that any individual output current of any source stays within...

Page 26: ...ated Data loss and board malfunction Disabling the PCI bus 0 reset and resetting the board when data transfer via SENTINEL is performed result in data loss and malfunction of the board RJ 45 Connector The board provides an RJ 45 connector Connecting the wrong interfaces e g Ethernet and RS 485 or Ethernet and telephone may damage the board Therefore In order to avoid damage to the board make sure ...

Page 27: ...ata for ID ROM and IPMI ID ROM Updating the IPMI flash with wrong data will damage the IPMI control ler Only update the IPMI flash with data provided by Motorola Battery Wrong battery installation may result in a hazardous explosion and board damage Using the battery longer than ten years results in data loss Therefore exchange the battery before ten years of actual battery use have elapsed Exchan...

Page 28: ...xxviii PPC CPCI 690 ...

Page 29: ...rfen nur von durch Motorola ausgebildetem oder im Bereich Elektronik oder Elektrotechnik qualifiziertem Personal durchgeführt werden Die in diesem Handbuch enthaltenen Informationen dienen ausschließlich dazu das Wissen von Fachpersonal zu ergänzen können es aber in keinem Fall ersetzen EMV Das Board wurde in einem Motorola Standardsystem getestet Es erfüllt die für digitale Geräte der Klasse A gü...

Page 30: ...n bzw ziehen Sie bei Ein oder Ausbau des Boards nicht auf die Frontblende sondern benutzen Sie die Griffe Lesen Sie vor dem Ein oder Ausbau von zusätzlichen Geräten oder Modulen das dazugehörige Benutzerhandbuch Vergewissern Sie sich dass das Board über alle Stecker an die CompactPCI Backplane angeschlossen ist und Spannung an allen Versorgungskontakten anliegt Hot Swap Wenn Sie das Board im laufe...

Page 31: ...Sie das Board nur innerhalb der angegebenen Grenzwerte für die relative Luftfeuchtigkeit und Temperatur Stellen Sie vor dem Einschalten des Stroms sicher dass sich auf dem Board kein Kondensat befindet Wenn Sie das Board in einer Umgebung mit elektromagnetischer Strahlung betreiben stellen Sie sicher dass das Board mit dem CompactPCI System verschraubt ist und das System durch ein Gehäuse abgeschi...

Page 32: ...ter mit produktionsrelevanten Funktionen belegt sein können die im normalen Betrieb Störungen auslösen könnten Ein Ändern der Schaltereinstellungen während des laufenden Betriebs kann das Board beschädigen Prüfen und ändern Sie die Schaltereinstellungen bevor Sie das Board installieren Wenn Sie den Schreibschutz des Boot Flashes aufheben ist es möglich dass Sie Boot Flash 2 unabsichtlich überschre...

Page 33: ...erBoot Der Befehl ferase löscht den gesamten Speicher des 32 MByte User Flashs Wenn Sie kleinere Teile des User Flashs löschen möchten verwenden Sie zusätzlich die Offset und Length Parameter die im Abschnitt ferase auf Seite 4 52 beschrieben werden Ändern Sie die Konfiguration ist es möglich dass SENTINEL nicht mehr funktioniert Ändern Sie die Konfiguration nur wenn Sie sich über die Konsequenzen...

Page 34: ...e reiner Betrieb vorüber sind Der Austausch der Batterie bringt immer einen Datenverlust bei den Komponenten mit sich die sich durch die Batterie die Stromversorgung sichern Sichern Sie deshalb vor dem Batterieaustausch Ihre Daten Verwenden Sie beim Batteriewechsel immer den selben Batterietyp der bereits eingesetzt wurde Umweltschutz Entsorgen Sie alte Boards und Batterien gemäß der in Ihrem Land...

Page 35: ...1 Introduction ...

Page 36: ......

Page 37: ...board Sicherheitshinweise German translation of the Safety Notes chapter Introduction Provides a basic overview of the features of the board and this manual Installation Outlines the installation requirements hard ware accessories switch settings installa tion and removal procedures Controls Indicators and Connectors Describes the LEDs keys and connectors of the board PowerBoot Describes the main ...

Page 38: ...uals and how we can make them better Mail comments to Motorola GmbH ECC Embedded Communication Computing Lilienthalstr 15 85579 Neubiberg Munich Germany reader comments mcg mot com Battery Exchange Appendix Describes how to exchange the on board battery Troubleshooting Appendix Describes how to deal with problems related to the operation of the board Chapter Description ...

Page 39: ...ffers high performance Combined with full hot swap capabilities it is an ideal component for multi node processor sys tems Other important features of the CPCI 690 are Three 10 100MBit Ethernet ports Up to 2 GByte on board SDRAM Two 64 bit 66 MHz PMC interfaces CompactFlash and hard disk support Non monarch mode ProcessorPMC support Packet switching backplane PSB support System management support ...

Page 40: ...wing standards Table 1 Standard Compliance Standard Description EN 60950 UL 60950 UL 94V 0 1 predefined Motorola system Legal safety requirements EN 55022 EN 55024 FCC Part 15 Class A EMC requirements on system level ANSI IPC A610 Rev C Class 2 IPC 7711 and 7721 ANSI J 001 003 Manufacturing requirements ...

Page 41: ... PSB xxx SDRAM size in MByte ccc Processor clock frequency in MHz zz User flash capacity in MByte PSB Packet switching backplane variant Table 2 Ordering Information Excerpt Order No PPC CPCI 690 Description 110190 256 700 32 IBM 750FX PowerPC processor 667 MHz with 256 MByte main mem ory user flash 32 MByte 110192 512 700 32 IBM 750FX PowerPC processor 667 MHz with 512 MByte main mem ory user fla...

Page 42: ...h 32 MByte 121222 512 1000GX 32 PSB IBM 750GX PowerPC processor 1 GHz with 512 MByte main memory user flash 32 MByte for PICMG 2 16 Packet Switching Backplane systems Hardware Accessories PPC CPCI 690 110196 ACC RTB 602 Rear transition board and Installation Guide 110197 ACC RTB 602 PSB Rear transition board and Installation Guide for PICMG 2 16 Packet Switching Backplane systems 111170 PMC 243D H...

Page 43: ...2 Installation ...

Page 44: ......

Page 45: ...Installation Action Plan PPC CPCI 690 2 3 Action Plan To install the board the following steps are necessary and described in detail in the sections of this chapter ...

Page 46: ...Action Plan Installation 2 4 PPC CPCI 690 ...

Page 47: ...ponent temperature In order to meet the operating conditions forced air cooling is required at both sides of the board The environmental values given in the table below only apply to the board without any accessories If installing accessories their environ mental requirements must also be taken into account If you use the board together with an PMC 243D or PMC 245FD make sure the environmental val...

Page 48: ...th the respective accessory or ask your local Motorola representative The following table gives the typical power requirements for a board with 750FX processor running at 667 MHz 1 GByte SDRAM No accessories Table 3 Environmental Requirements Feature Operating Non Operating Temperature 0 C to 55 C may be further limited by hard disk 40 C to 85 C Forced air flow 300 LFM Temp change 0 5 C min 1 C mi...

Page 49: ... passively protected with positive temperature coefficient PTC fuses Table 4 Power Requirements for Boards with 750FX Processor 667 MHz Requirement 3 3V 5V VIO1 1 If 3 3V or 5V are used depends on used system 3 3V 5V Maximum power dissipation 9 6W 7 5W 1 32W 2 0W Min Voltage 3 20V 4 85V 3 20V 4 85V Max Voltage 3 45V 5 25V 3 45V 5 25V Max Current 2 9A 1 5A 0 4A 0 4A Table 5 Power Requirements for B...

Page 50: ... modules The slots can be used to install a PMC module with front panel interfaces and rear interfaces see Connectors page 3 7 The user I O signals of slot 1 are routed to the J3 connector the user I O signals of slot 2 are routed to the J5 connector enabling access to these pins on the RTB Note To ensure proper EMC shielding either operate the board with the blind panels for the PPC CPCI 690 fron...

Page 51: ...t have drill holes at the 3 3 V voltage key position the voltage keys pre vent these modules from being installed into the PMC slots Figure 2 Voltage Keys Installation Procedure 1 Remove blind panel of respective PMC slot from front panel 2 Store blind panel in safe place 3 Check that PMC module has a drill hole at 3 3V position If not the PMC module cannot be installed Figure 3 Location of 3 3V V...

Page 52: ...the PMC module exceeds 7 5W the board and the PMC module may be damaged Therefore make sure that the total max power consumption at 12V 5V and 3 3V level does not exceed 7 5W total over all used voltages 4 Plug PMC module into connectors of PMC slot 1 PN11 12 13 14 or PMC slot 2 PN21 22 23 and 24 Figure 4 PMC Connectors and Slots ...

Page 53: ... of module cover mounting holes of board Figure 5 Position of Mounting Holes 6 Place screws delivered with PMC module from bottom side into mounting holes 7 Fasten screws Removal Procedure 1 Remove screws 2 Disconnect PMC module from slot 3 Close front panel gap at free slot with blind panel ...

Page 54: ... IDE interface via a rear transition board if a PMC 244FP is plugged in PMC slot 1 Note If you want to connect further IDE devices via RTB install the PMC 244FP module into PMC slot 1 since only PMC slot 1 has routed the secondary IDE interface of the IDE controller to the backplane If you in stall it into PMC slot 2 the IDE devices on the secondary IDE interface do not work For further informatio...

Page 55: ...carry production related functions Boot block damage If you change the boot flash write protection you may unintentionally overwrite boot flash 2 Only change the boot flash write protection if it is explicitly stated Board damage Setting resetting the switches during operation causes board damage Therefore check and change switch settings before you install the board Data loss and board malfunctio...

Page 56: ...lt ON The IPMI SYSEN is active 3 Front panel reset OFF Reset key enabled default ON Reset key disabled 4 Reserved OFF Default SW2 1 Boot flash selection OFF Booting from boot flash 1 default ON Booting from boot flash 2 2 Boot flash write enable OFF Write disabled default ON Write enabled 3 User flash write protection OFF Protection disabled default ON Protection enabled 4 PCI bus 0 reset OFF PCI ...

Page 57: ...s PPC CPCI 690 2 15 SW4 1 Reserved OFF Default 2 Reserved OFF Default 3 Reserved OFF Default 4 Reserved OFF Default 1 The IPMI controller is BMC SYSEN active or PM SYSEN inactive Table 7 Switch Settings Switch Number Description ...

Page 58: ...ontroller in a system slot or as an intelligent I O board in a peripheral slot The PSB variant must be installed into a node slot Both board variants provide hot swap support i e they may be installed in or removed from a powered system This section is divided into two sub sections for installing the board in a nonpowered system and in a powered system supporting hot swap Note EN 55022 Class A and...

Page 59: ...non ESD protected environment causes component and board damage Before touching boards or electronic components make sure that you are working in an ESD safe environment 2 Check switch settings for consistency see Switch Settings page 2 13 3 Open handles 4 PSB variant Install board into node slot Standard CompactPCI variant Install board depending on intended function either in system slot marked ...

Page 60: ...igh availability The basic purpose of hot swap support and high availability is to allow the board to be installed in and removed from a powered system without adversely affect ing system operation With high availability support defective boards can be repaired and systems can be reconfigured without stopping system operation and with minimum operator interaction Caution Board damage and data loss...

Page 61: ...stem to indicate a service request The Control and Status registers allow to determine the source of the ENUM signal and to control the hot swap LED The HEALTHY signal is active whenev er all backplane and on board voltages are within their operating range Installation Procedure Caution Board damage and data loss Installing the board under hot swap conditions in system slots causes board damage an...

Page 62: ...wered system The hot swap LED stays blue until the board software connection pro cess has been completed 4 Close handles 5 Fasten board with screws Removal Procedure Before removing the board observe the following Caution Board damage and data loss Removing the board under hot swap conditions from system slots causes board damage and data loss Therefore only remove the board under hot swap conditi...

Page 63: ...ait until software disconnection process has been completed 3 Remove screws from front panel 4 Open handles 5 Remove board from peripheral slot of powered system From Full Hot Swap or High Availability System 1 Remove screws from front panel 2 Press red button to unlock handles Figure 8 Button on Handle 3 Open handles The hot swap switch will be opened automatically 4 Wait until blue hot swap LED ...

Page 64: ...Board Installation Installation 2 22 PPC CPCI 690 ...

Page 65: ...3 Controls Indicators and Connectors ...

Page 66: ......

Page 67: ...g whether you use a CompactPCI standard or a PSB board variant Figure 9 Compatibility Glyphs for CompactPCI Standard and PSB Board Variants The following figure highlights the position of the cutouts for the PMC modules the keys the connectors and the LEDs on the CPCI 690 front panel Figure 10 CompactPCI Standard and PSB Front Panel ...

Page 68: ...Front Panel Controls Indicators and Connectors 3 4 PPC CPCI 690 PMC Cutouts The front panel provides two cutouts to install PMC modules ...

Page 69: ...led and toggled If the board is installed into a system slot the main re set additionally generates a CompactPCI reset i e a reset of the whole sys tem If a board is installed into a PSB backplane that does not use the Compact PCI bus pressing the reset key results in a board reset When the reset key is pressed all on board I O devices and the CPU are re set Reset is held active until the key is r...

Page 70: ...dicates the sta tus of the Ethernet 1 default 2 and 3 interfaces respectively depending on configuration by software programmable see userled page 4 26 Green Ethernet link activity OFF No link activity User LED mode programmable see userled page 4 26 User LED 2 can be programmed to be red green or OFF HS Hot swap LED Indicates hot swap status Blue Board is installed and may be removed from the sys...

Page 71: ...nnectors The front panel provides the following connectors RJ45 for Ethernet 1 Micro D SUB for serial ports 1 and 2 The following connector pinouts provide information on signal assign ments Figure 11 Ethernet 1 Connector Pinout Figure 12 COM 1 and 2 Connector Pinout ...

Page 72: ...rs J1 J2 J3 and J5 The Com pactPCI interface is clocked with 33MHz and is 32 bit wide Figure 13 Location of CompactPCI Connectors J1 and J2 The J1 and J2 connectors implement the CompactPCI 64 bit connector pinout as specified by the CompactPCI specification PICMG 2 0 R3 0 Therefore these pinouts are not documented in this Reference Guide ...

Page 73: ...CI Connectors PPC CPCI 690 3 9 J3 Connector J3 provides interfaces to Ethernet 2 and 3 PMC1 user I O Figure 14 J3 Connector Pinout J5 Connector J5 provides interfaces to COM 1 and 2 PMC2 user I O ICMB and IPMB1 port RTB reset key and I2C devices ...

Page 74: ...CompactPCI Connectors Controls Indicators and Connectors 3 10 PPC CPCI 690 Figure 15 J5 Connector Pinout Rows A to C Figure 16 J5 Connector Pinout Rows D and E ...

Page 75: ...4 PowerBoot ...

Page 76: ......

Page 77: ...g the operating system PowerBoot performs basic hard ware tests and prepares the board for the initial boot up procedure PowerBoot can be used for the following tasks Booting the board from an operating system e g Linux Testing the board Booting the board is described in detail in Booting the Board page 4 5 The other tasks can be performed by means of entering commands de scribed briefly in Comman...

Page 78: ...0016 8FFFFFFF16 CompactPCI memory space 1 GByte 9000000016 9FFFFFFF16 On board PCI memory space PMC 1 GByte F000000016 F000000F16 Board registers CS 0 16 Bytes F010000016 F0107FFF16 RTC NVRAM CS 1 32 KByte F020000016 F020000F16 IPMI Controller CS 2 12 Bytes F020000016 F020000116 KCS01 1 Interface of IPMI controller 2 Bytes F020000816 F020000916 KCS11 2 Bytes F100000016 F100FFFF16 Discovery registe...

Page 79: ...after the next power on or after reset Reading POST Results If POST is executed before the boot up procedure or not can be set in the POST option in setboot If POST is enabled and executed its results are stored in the NVRAM at offset 7CF816 A fully functional CPCI 690 will show the value 0x3B for all tests which are okay A failure will not stop the power up process since debug functional ity is p...

Page 80: ...ted Table 10 Setboot Options Option Description Parameter Required to be set when Booting from Boot select Location of the binary image which will then be loaded to the load address 0 Net 1 Go 2 Flash Copy 3 ATA IDE Auto boot Auto boot option to boot automatically with a power up 0 Disable 1 Enable Net Flash ATA IDE Auto boot delay Time value to delay boot process Auto booting countdown can be sto...

Page 81: ...lect boot disk Boot disk to boot from ATA IDE TFTP ATA IDE boot file name Binary image name which will be down loaded via net or atapi image bin Net ATA IDE CompactPCI bus probe list Probe list for Compact PCI 8 7 6 5 4 3 2 Power on self test POST To enable or disable the power on self test 0 Enable 1 Disable Primary Booter To enable or disable the primary booter 0 Disable 1 Enable Watchdog dur in...

Page 82: ...pears PowerBoot _ Caution Data Loss The ferase command erases the whole 32 MByte storage of the 32 MByte user flash device If you want to erase smaller parts of the user flash device use the offset and length parameters described in ferase page 4 52 3 Enter ferase command to erase user flash ferase user_flash The following message appears Erasing flash memory done Erasing flash memory done Erasing...

Page 83: ...00100030 46 4f 52 43 45 20 46 4f 52 43 45 20 46 4f 52 43 00100040 45 20 46 4f 52 43 45 20 46 4f 52 43 45 20 46 4f 00100050 52 43 45 20 46 4f 52 43 45 20 46 4f 52 43 45 20 00100060 46 4f 52 43 45 20 46 4f 52 43 45 20 46 4f 52 43 00100070 45 20 46 4f 52 43 45 20 46 4f 52 43 45 20 46 4f 00100080 52 43 45 20 46 4f 52 43 45 20 46 4f 52 43 45 20 00100090 46 4f 52 43 45 20 46 4f 52 43 45 20 46 4f 52 43 0...

Page 84: ...43 45 20 46 4f 52 43 f40000a0 45 20 46 4f 52 43 45 20 46 4f 52 43 45 20 46 4f f40000b0 52 43 45 20 46 4f 52 43 45 20 46 4f 52 43 45 20 f40000c0 46 4f 52 43 45 20 46 4f 52 43 45 20 46 4f 52 43 f40000d0 45 20 46 4f 52 43 45 20 46 4f 52 43 45 20 46 4f f40000e0 52 43 45 20 46 4f 52 43 45 20 46 4f 52 43 45 20 f40000f0 46 4f 52 43 45 20 46 4f 52 43 45 20 46 4f 52 43 More cr PowerBoot Partitioning the Ha...

Page 85: ...d a value restoring the default values is only pos sible by means of either removing the battery from the board or writing a wrong value into the protected NVRAM range This results in a wrong NVRAM checksum and leads to a restoration of the default values after the next boot up If you want to restore the default values via the NVRAM proceed as fol lows 1 PowerBoot m f0107c00 2 Enter 3 f0107c00 323...

Page 86: ...ce dread 4 17 Memory write performance drw 4 18 Memory read and write performance dwrite 4 19 Settings Change baud rate baud 4 20 Enable available cache cache 4 21 Disable all caches and interrupts and start an executable image execute 4 21 Modify or display memory contents m 4 33 Modify boot options setboot 4 24 Set parameters for SENTINEL SROM setcpci 4 25 Set function of user LEDs userled 4 26 ...

Page 87: ... on board EEPROMs eeprom_read 4 37 Write data to an on board I2C EEPROM eeprom_write 4 38 Program flash memory fprog 4 39 Send values to the IPMI controller ipmi_request 4 41 Load s records into memory lo 4 41 Load binary image from a remote system via network interface netload 4 43 Save a memory area via TFTP into a file on a host system netsave 4 45 Reset Hardware reset hreset 4 47 Software rese...

Page 88: ...ormat SYNTAX atatest PARAMETERS None EXAMPLE PowerBoot atatest Testing ATA IDE interface Found 2 devices on this ATA interface Device 0 type ATA Device 1 type unknown type Device 0 is the selected device for this run Soft Reset Seek CHS polling Seek LBA polling ATA Identify CHS polling ATA Identify LBA polling Identify ATA IDE device Signature 0x848A Serial Number i5809080307 Model Number SanDisk ...

Page 89: ...e prime test fill the memory area specified by begin and end After the memory area has been filled the testing starts indicated by test forward i e memory is tested from begin to end test backward i e memory is tested from end to begin If an error occurs during the test the following error message will appear error at location 0x12345678 value found 0xAB should be 0xBA SYNTAX bt begin end e c Tabl...

Page 90: ...Walking ones test reverse done Walking zeros test 8bit done Walking zeros test reverse done Increment test 8bit done Checkerboard test 16bit done Checkerboard test reverse done Walking ones test 16bit done Walking ones test reverse done Walking zeros test 16bit done Walking zeros test reverse done Increment test 16bit done Checkerboard test 32bit done Checkerboard test reverse done Walking ones te...

Page 91: ... 8 16 32 64 128 256 512 d 2 02 227 12 10 9 9 9 9 9 d 2 03 14 11 10 9 9 9 9 9 d 2 04 14 11 10 9 9 9 9 9 d 2 05 14 11 10 9 9 9 9 9 d 2 06 14 11 10 9 9 9 9 9 d 2 07 16 13 12 11 10 10 10 18 d 2 08 16 13 12 11 10 11 18 18 d 2 09 16 13 12 11 12 18 18 18 d 2 10 16 13 12 13 18 18 18 20 d 2 11 17 13 16 19 18 18 21 159 d 2 12 18 23 21 20 19 25 160 160 d 2 13 18 23 21 20 32 161 161 160 d 2 14 18 23 21 46 163...

Page 92: ...128 256 512 d 2 02 85 77 73 71 69 69 69 69 d 2 03 86 77 73 71 69 69 69 69 d 2 04 86 77 73 71 69 69 69 69 d 2 05 86 77 73 71 69 69 69 69 d 2 06 86 77 73 71 69 69 69 69 d 2 07 86 77 73 71 69 69 69 69 d 2 08 86 77 73 71 69 69 69 69 d 2 09 86 77 73 71 69 69 69 69 d 2 10 86 77 73 71 69 69 69 70 d 2 11 85 77 73 71 69 69 71 242 d 2 12 87 78 74 72 70 74 250 250 d 2 13 87 78 74 72 79 251 251 250 d 2 14 87 ...

Page 93: ...38 138 138 d 2 03 172 155 146 142 140 138 138 138 d 2 04 172 155 146 142 140 138 138 138 d 2 05 172 155 146 142 140 138 138 138 d 2 06 172 155 146 142 140 138 138 138 d 2 07 172 155 146 142 140 138 138 138 d 2 08 172 155 146 142 140 138 138 138 d 2 09 172 155 146 142 140 138 138 138 d 2 10 172 155 146 142 140 138 138 138 d 2 11 172 155 146 142 140 138 138 138 d 2 12 172 155 146 142 140 138 138 138...

Page 94: ...o change the actual baud rate to the specified value To apply the new baud rate a reboot is necessary Note If you chose a baud rate the terminal is not able to handle you will not get any output on screen Inform yourself about the settings of your screen and choose baud rates which provide a screen output SYNTAX baud value PARAMETERS 600 1200 2400 4800 9600 19200 38400 115200 EXAMPLE PowerBoot bau...

Page 95: ...cts the instruction cache 2 Selects the 2nd level cache e d e Enables the cache d Disables the cache EXAMPLE PowerBoot cache d d Data cache disabled PowerBoot execute DESCRIPTION Command to disable all caches and interrupts and start an executable image SYNTAX execute address PARAMETERS address start address of the executable image EXAMPLE PowerBoot execute 100000 ...

Page 96: ...ds can be entered They do not change the access option in the command line The following key and commands are supported SYNTAX m address size type PARAMETERS Note Type options O and E override the options B W and L Access op tions B W L N and E check whether the write access has been success ful by performing a read access after the write access If the written and the read data do not match the co...

Page 97: ...rd sized 16 bit L Memory access is long word sized 32 bit type Specifies the memory access type Possible values are N Memory access is limited to writing the current contents are not dis played E Memory access is byte sized and refers only to even addresses O Memory access is byte sized and refers only to odd addresses EXAMPLE PowerBoot m 100000 b 00100000 00 4f 00100001 00 00100001 00 00100001 00...

Page 98: ...e parameters Ethernet 1 2 or 3 0 Additional tftp retries 00000000 RARP 1 or ARP 2 protocol 1 Server IP aaa bbb ccc ddd Target IP aaa bbb ccc ddd Select bootdisk 0 TFTP SCSI ATA IDE Boot file name PCI to PCI bridge host mode parameters Compact PCIbus probe list 8 7 6 5 4 3 2 8 7 6 5 4 3 2 Power On Self Test POST parameters Power ON Self Test POST 1 disable 0 enable 0 Primary Booter parameters FORCE...

Page 99: ...AR 3 translate 0x0 Downstream BAR 4 setup 0x0 Downstream BAR 4 translate 0x0 Upstream BAR 2 setup 0xfff00000 Upstream BAR 2 translate 0x0 Upstream BAR 3 setup 0x0 Upstream BAR 3 translate 0x0 Scratchpad 0x0 Expert settings Chip control 0 0x0 Chip control 1 0x0 Arbiter control and status 0x8020 Primary SERR control 0x7 Secondary SERR control 0x7 User capability ID 0x0 Message control 0x0 MSI next i...

Page 100: ...s disabled HW USERLED shows default state after power up ethX USERLED shows Ethernet activity Possible values for X are 1 2 or 3 for Ethernet ports 1 3 EXAMPLE PowerBoot userled 2 eth3 PowerBoot wdog DESCRIPTION Command to enable the watchdog SYNTAX wdog sec PARAMETERS sec Note The parameter is interpreted as a hexadecimal value Countdown in seconds before the reset EXAMPLE PowerBoot wdog 10 Setti...

Page 101: ...byte of the source memory area used for copying end Specifies the end address of the source memory area i e the first byte of the source memory area not used for copying destination Specifies the start address of the destination memory area where the first byte of the source memory area is copied to EXAMPLE PowerBoot bm 2D00 3D00 5E00 PowerBoot nvramrd DESCRIPTION Command to copy the NVRAM content...

Page 102: ...rea into the NVRAM and generate the cor rect checksum SYNTAX nvramwr scr address PARAMETERS scr address Location of the new NVRAM contents EXAMPLE PowerBoot nvramwr 100000 Do you really want to write data to NVRAM y n y Write 32KB data at address 0x00100000 to NVRAM CSUM 0xCEC PowerBoot ...

Page 103: ... Processor register values On board IPMI controller Memory contents Board temperature devshow DESCRIPTION Command to display information on the board PCI bus structure SYNTAX devshow 1 2 3 4 node verbose level PARAMETERS 1 2 3 4 Selects the information level 1 to 4 node Selects a specific node verbose level Shows if child nodes exist or not RETURNS Displays all found PCI devices and resources ...

Page 104: ...0 ref 0 Implements Classes PCI CPCI Implements bus type PCI bus Device type PCI Expands parent bus domain Driver Rtn Parm 0xfff1756c 0x1ff25c88 DevVen 0x00011146 SubSys 0x00000000 Base SubClass 0x06 0x04 No device information available BAR 0 87ffe000 4KB MEM 32bit BAR 1 8fffff00 128Byte IO Prefetchable Memory fff00000 to 000fffff DISABLED Memory Mapped IO fff00000 to 000fffff DISABLED IO Range 000...

Page 105: ... by Power Boot SYNTAX help PARAMETERS None EXAMPLE PowerBoot help Command words ATATEST Test of ATA IDE interface connection AUTOBOOT Init SETBOOT command parameter settings BAUD BAUD 600 1200 2400 4800 9600 19200 38400 115200 BF BF begin end value B W L P BM BM begin end destination BS BS begin end value B W L P BT BT begin end e c BV BV begin end destination CACHE CACHE d i 2 e d DEVSHOW Show bo...

Page 106: ...rt end Trgt Enet Trgt IP Srvr IP NVRAMRD NVRAMRD dest address NVRAMWR NVRAMWR src address PRIMABOOT Start Primary Booter FORCE internal use RESET RESET board SETBOOT SETBOOT edit autoboot parameters SETCPCI SETCPCI e edit cpci bridge boot parameters TEMP Show board temperature USERLED USERLED 1 2 red green dis HW ethX WDOG WDOG sec enables watch dog CONFIG_RD Host PCIbus cfg RD dom bus dev fun reg...

Page 107: ...N This command displays the memory contents The data is displayed in hexadecimal notation and ASCII code If the data cannot be displayed in ASCII code a full stop is displayed instead The memory contents are displayed in blocks of 16 lines each block repre senting 16 byte If you want to display the next block of lines press Enter If you want to return to the command line enter the full stop charac...

Page 108: ...0 00 f1000080 40 08 00 01 40 08 00 01 7f 08 00 00 7f 08 00 00 f1000090 e0 09 00 01 e0 09 00 01 ff 09 00 00 ff 09 00 00 f10000a0 00 09 00 01 00 09 00 01 3f 09 00 00 3f 09 00 00 f10000b0 40 09 00 01 40 09 00 01 7f 09 00 00 7f 09 00 00 f10000c0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f10000d0 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff f10000e0 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff...

Page 109: ...Load S records or a binary image via TFTP Save a specified memory area via TFTP config_rd DESCRIPTION Command to perform a PCI configuration read to a specific PCI location SYNTAX config_rd dom bus dev fun reg B W L PARAMETERS dom Domain number of first or second PCI bus bus Bus number dev Device number fun Function number reg Register offset B W L Size of the read byte word or long EXAMPLE PowerB...

Page 110: ...nly change the configuration if you are familiar with the consequences If after a change the board does not work reboot the board SYNTAX config_wr dom bus dev fun reg data B W L PARAMETERS dom Domain number of first or second PCI bus bus Bus number dev Device number fun Function number reg Register offset data Data to write B W L Size of the read byte word or long EXAMPLE PowerBoot config_wr 0 0 1...

Page 111: ... device is given by the eeprom_info command offs Offset from which the read starts byteCnt Count of bytes to be read dstAddr Destination of the read data EXAMPLE PowerBoot eeprom_read ID_ROM_0 0 30 MSG Begin of S record S11300000C200C851C2500344653626A6C6E720009 S1130010464F52434520434F4D505554455253008B S113002009435043492D36393000103231313032D2 S9030000FC MSG End of S record PowerBoot ...

Page 112: ...ng this data results in a malfunction of the board Do not overwrite the data for ID ROM and IPMI ID ROM SYNTAX eeprom_write e device offs byteCnt srcAddr PARAMETERS e Echo mode device Name of the device given by the eeprom_info command offs Offset to write to byteCnt Count of the bytes srcAddr Data address EXAMPLE PowerBoot eeprom_write ID_ROM_0 MSG Waiting for S record data MSG End of S record Po...

Page 113: ...ess containing the data with which the flash mem ory device is to be programmed flashOffset Specifies the destination offset within the flash memory device length Specifies the number of bytes to be programmed EXAMPLE 1 Suppose you want to reprogram the write protected boot flash 1 with the data stored at source address 0010000016 Since FPROG checks whether the flash is write protected or not the ...

Page 114: ...ide available via S M A R T SYNTAX IPMI_FLSUPD begin end addr PARAMETERS EXAMPLE PowerBoot netload ipmicore_all_0_96 s3r 100000 192 168 41 111 192 168 41 1 PHY Device at 100MB s and full duplex negotiated WANCOM MAC ADDRESS 00 80 42 11 E7 3C Transmitting ARP REQUEST Reception of ARP REPLY Transmitting TFTP REQUEST to server 00 80 42 10 5B C7 IP 192 168 41 1 PACKET 871 loaded 00100000 0016CD13 4457...

Page 115: ...arried out Loading S records from the console port to the memory Modifying the storage address while loading S records from the console port to the memory Verifying the S records Modifying the storage address while verifying the S records Displaying the number of errors which occurred during the last loading SYNTAX lo offset v e host commands PARAMETERS host commands Specifies a list of commands t...

Page 116: ...Command Set PowerBoot 4 42 PPC CPCI 690 EXAMPLE PowerBoot lo 100200 PowerBoot md 100200 10 00100200 54 68 69 73 20 69 73 20 61 20 74 65 73 74 00 00 This is a test PowerBoot _ ...

Page 117: ... SYNTAX netload c controller filename address Ethernet targetIP serverIP PARAMETERS controller Specifies the Ethernet interface Possible values are ETH1 ETH2 and ETH3 filename Absolute file name including the path name to access the file to be loaded The length of the file name is limited to 128 characters The file has to be a binary image in big endian notation address First byte of the memory us...

Page 118: ...sing RARP PowerBoot netload test 100000 00 80 42 0E 88 88 PHY Device at 100MB s and full duplex negotiated WANCOM MAC ADDRESS 00 80 42 0E 88 88 Transmitting RARP REQUEST Reception of RARP REPLY Transmitting TFTP REQUEST to server 00 80 42 10 5B C7 IP 192 168 41 1 PACKET 2049 loaded 00100000 00200000 1048577 bytes PowerBoot _ EXAMPLE 3 The file test is downloaded to 0010000016 on the CPU board with...

Page 119: ...values are ETH1 ETH2 and ETH3 filename Specifies the name of the file in the host system startAddr Specifies the starting address of the memory area to be saved into the file on the host endAddr Specifies the end address of the memory area to be saved into the file on the host Ethernet Specifies the Ethernet address of the CPU board targetIP Defines the Internet IP address of the CPU board target ...

Page 120: ...TFTP REQUEST to server 00 80 42 10 5B C7 IP 192 168 41 1 PACKET 2049 saved 00100000 001FFFFF 1048576 bytes PowerBoot EXAMPLE 3 PowerBoot netsave test 100000 1fffff 192 168 41 111 192 168 41 1 PHY Device at 100MB s and full duplex negotiated WANCOM MAC ADDRESS 00 80 42 11 E7 24 Transmitting ARP REQUEST Reception of ARP REPLY Transmitting TFTP REQUEST to server 00 80 42 10 5B C7 IP 192 168 41 1 PACK...

Page 121: ... Init DTLB ITLB for block translation enable MMU Init L1 Icache Init L1 Dcache Init L2 Cache Found IBM750FX at 667 MHz Init exception vectors starting at address 0x00000100 Onboard SDRAM 512MB RAM Init device library Discovery 0 is PCI 1 is PCI 1 PCI 0 is PCI 0 CompactPCI 0 is PCI 0 CompactPCI 20 Ethernet 1 0080 42 11 67 C1 Ethernet 2 0080 42 11 67 C2 Ethernet 3 0080 42 11 67 C3 Found RTB 602 Powe...

Page 122: ...t L1 Icache Init L1 Dcache Init L2 Cache Found IBM750FX at 667 MHz Init exception vectors starting at address 0x00000100 Onboard SDRAM 512MB RAM Init device library Discovery 0 is PCI 1 is PCI 1 PCI 0 is PCI 0 CompactPCI 0 is PCI 0 CompactPCI 20 Ethernet 1 0080 42 11 67 C1 Ethernet 2 0080 42 11 67 C2 Ethernet 3 0080 42 11 67 C3 Found RTB 602 PowerBoot V4 xx for PowerCoreCPCI CPCI 690 c by FORCE CO...

Page 123: ...W L P PARAMETERS begin First byte of the memory area used for filling end First byte of the memory area not used for filling value Specifies the constant for filling Possible constants are Byte value A Byte constant followed by the character B e g A5 B Word value A Word constant followed by the character W e g A5B6 W Long value A long constant followed by the character L e g A5B6C7D8 L String valu...

Page 124: ... which is read end Specifies the end address of the memory area which is searched i e the first byte of the memory area which is not read value Specifies the constant to search for Possible constants are byte value A byte constant followed by the character B e g 3F B word value A word constant followed by the character W e g 3F3F W long value A long constant followed by the character L e g EFEFEFE...

Page 125: ...area i e the first byte of the source memory area which is read end Specifies the end address of the source memory area i e the first byte of the source memory area which is not read destination Specifies the start address of the destination memory area i e the first byte of the destination memory area which is compared with the source mem ory EXAMPLE 1 A 4 KByte memory from 00002D0016 00003D0016 ...

Page 126: ...There are two tasks which can be done by means of FERASE Erasing a whole flash memory device Erasing a specified area of a flash memory device SYNTAX ferase flashDevice flashOffset length PARAMETERS flashDevice Specifies the name of the flash memory device to be erased If only flashDe vice is defined the whole flash memory device will be erased flashOffset Specifies the destination offset within t...

Page 127: ...flash device done PowerBoot _ go DESCRIPTION This command starts executing a binary image located in the DRAM memory After entering go you exit from PowerBoot At the end of the binary image enter the opcode blr to return to PowerBoot SYNTAX go address PARAMETERS address Specifies the starting address of the binary image EXAMPLE PowerBoot go 10000 ...

Page 128: ...Command Set PowerBoot 4 54 PPC CPCI 690 ...

Page 129: ...5 Buses ...

Page 130: ......

Page 131: ...Buses Block Diagram PPC CPCI 690 5 3 Block Diagram The block diagram shows how the board s devices work together and which data paths they use ...

Page 132: ...ector J3 On the standard variants the magnetics for port 2 and 3 are implemented on the RTB On the front panel a green LED is available which indicates an Ethernet link For further information on Ethernet LEDs refer to LEDs page 3 6 Serial Ports The system controller includes two multi protocol serial controllers MPSC which are configured for Universal Asynchronous Receiver Trans mitter UART mode ...

Page 133: ...b to field CTL1 If en abled the watchdog is a free running counter that needs to be triggered pe riodically in order to prevent expiration Watchdog service is done by writing 01b followed by 10b to field CTL2 of the Watchdog configuration register For further information refer to the GT 64260A System Controller for PowerPC Processors data sheet The watchdog is running with the system controller s ...

Page 134: ...CPUs PowerPC 750FX This CPU has an internal 64 KByte L1 cache and 512 KByte of L2 cache both with 256 bit wide cache paths Both caches are running at the full processor core frequency of 667 MHz or higher PowerPC 750GX This CPU has an internal 64 KByte L1 cache and 1 MByte of L2 cache both with 256 bit wide cache paths Both caches are running at the full processor core frequency of up to 1 GHz ...

Page 135: ... are used for row and column address The board is equipped with PC133 compliant unregistered SDRAM memo ry devices and has a maximum capacity from 256 MByte up to 1 GByte If the maximum capacity is 256 MByte one bank is equipped with 256 MBit devices and if it is 1 GByte two banks are equipped with 512 MBit devices using dense pack three level stacking technology Table 15 Memory Bus Characteristic...

Page 136: ...Swap page 2 18 The table below lists all fields in the SPROM of the SENTINEL the contents loaded into the registers at power up Note Invalid SPROM contents may cause malfunction of the board Table 16 Devices on PCI Bus 0 PCI Device Device Type ID SEL Dev No PCI IRQ REQ GNT Discovery PCI Inter face 0 GT 64260A 31 21 INTA Internal PCI to CompactPCI bridge SENTINEL 30 20 INTA INTD 4 Table 17 PCI Bus ...

Page 137: ...es 0000000016 Downstream BAR 2 DSR setup 1016 Yes FFF0000016 This defines a default PCI window of 1 MByte Downstream BAR 2 DSR translate 1416 Yes 0000000016 Downstream BAR 3 DSR setup 1816 Yes 0000000016 Downstream BAR 3 DSR translate 1C16 Yes 0000000016 Downstream BAR 4 DSR setup 2016 Yes 0000000016 Downstream BAR 4 DSR translate 2416 Yes 0000000016 Upstream BAR 2 DSR setup 2816 Yes FFF0000016 De...

Page 138: ...ry max latency preload 4716 No 0116 Upstream BAR 3 setup 4816 Yes 0000000016 Upstream BAR 3 translate 4C16 Yes 0000000016 Chip control 0 5416 Yes 000016 Chip control 1 5616 Yes 000016 Arbiter con trol status 5A16 Yes 800016 Primary SERR control 5D16 Yes 0716 Secondary SERR control 5F16 Yes 0716 GPIO control 6016 No F016 GPIO write data 6116 No 8016 GPIO IR mask 6316 No FF16 User capability ID 6816...

Page 139: ...s field defines Other Bridge Primary base class code 7B16 Yes 0616 This field defines Bridge Device Secondary pro gramming inter face 7D16 Yes 0016 Secondary sub class code 7E16 Yes 8016 This field defines Other Bridge Secondary base class code 7F16 Yes 0616 This field defines Bridge Device Table 18 SENTINEL SPROM Contents Register Name Offset Configurable Default Value Comment ...

Page 140: ...al secondary PCI agent PMC1 29 19 INTA INTD 1 PMC slot 2 PMC2 28 18 INTA INTD 2 PMC slot 2 optional secondary PCI agent PMC2 27 17 INTA INTD 3 Table 20 PCI Bus 1 Interrupt Routing PCI Device Device Interrupt Interrupt Received by System Controller Discovery PCI Interface 1 INTA INTD PMC Slot 1 INTA INTC INTB INTD INTC INTA PMC Slot 1 Secondary PCI Agent Pro cessorPMC specification INTD INTB INTA I...

Page 141: ... 2 The PMC 2 interface is a 3 3V compliant PCI interface with its user I O sig nals routed towards CompactPCI connector J5 PMC slot 2 can be used for Motorola s PMC 8260 module Non Monarch mode ProcessorPMC mod ules and Ramix IDE modules on module primary IDE interface as well as secondary interface via RTB are supported PMC Slot 2 Secondary PCI Agent Pro cessorPMC specification INTA INTA INTB INT...

Page 142: ...de flash devices offering up to 64 MByte user flash memory 32 MBytes are implemented on the orderable variants per default 64 MBytes of user flash memory are available as an assembly option The user flash memory is write enabled by default and can be repro grammed on board see Programming the User Flash page 4 8 Write protection can be enabled via switch setting see Table 7 Switch Settings page 2 ...

Page 143: ... sensor IPMB0 signals are available at CompactPCI connector J1 IPMB1 signals are available at CompactPCI connector J2 and at J5 via ACC RTB 602 ICMB signals are available at J5 via ACC RTB 602 The operational mode BMC PM can be set manually via switch see Table 7 Switch Settings page 2 14 If the manual selection is disabled au tomatic selection of PM or Base Board Management Controller BMC func ti...

Page 144: ...any SDRs are provided use the IPMI command Get Device SDR Info together with the API of the Motorola VxWorks IPMI driver To read the SDRs into your system management software use the IPMI command Get Device SDR To add the provided SDRs to the repository use the IPMI command Add SDR The temperature values can be read via the Master Write Read I2C IPMI command and the I2C slave address together with...

Page 145: ...oller It is part of the VxWorks 5 4 Tornado 2 0 BSP Rel 2 1 For further information refer to the VxWorks 5 4 Tornado 2 0 BSP Rel 2 1 Installation Guide and Release Notes and the IPMI Specification V 1 0 Table 21 Slave Addresses of Devices Attached to IPMI Controller s I2C Buses I2C Bus I2C Bus Slave Address Description 2 1010000x2 A016 ID ROM CPCI 690 XICOR X24LC128 serial E2 PROM 2 1010010x2 AA16...

Page 146: ...es like an RTB or PMC modules This I2C bus can be accessed via IPMI controller and Master write read command JTAG connector I2C interface integrated in system controller Table 22 On Board I2C Devices Device Type Size in KByte Board ID ROM 24LC128 128 IPMI ID ROM 24C02 2 Table 23 Off Board I2C Devices Device Type Size in KByte Description PIB1 Depends on used PMC module PMC 1 information block PIB2...

Page 147: ...uses Local I2C Buses PPC CPCI 690 5 19 Figure 18 Connection to I2C Devices SENTINEL I2C Bus This bus connects the SENTINEL with the SROM for configuration regis ters A 24C04 device with 4 KBytes is used ...

Page 148: ...Local I2C Buses Buses 5 20 PPC CPCI 690 ...

Page 149: ...6 Maps and Registers ...

Page 150: ......

Page 151: ...ard specific registers Table 24 Register Overview Register Description Last Reset Status register 1 Page 6 14 Last Reset Status register 2 Page 6 15 LED Control register Page 6 10 Memory Configuration register Page 6 13 Miscellaneous Status register Page 6 11 Software Reset register Page 6 11 Switch Status register Page 6 12 ...

Page 152: ... 1 1 Contains up to four PCI memory windows for each PCI bus segment 64 bit EF80000016 EFFFFFFF16 8 MBytes PCI I O space 2 2 Contains one PCI I O window for each PCI bus segment 64 bit F000000016 F000000716 8 Bytes Board registers 8 bit F000000816 F00FFFFF16 Reserved F010000016 F0107FFF16 32 KBytes RTC NVRAM 8 bit F010800016 F01FFFFF16 Reserved F020000016 F020000F16 16 Bytes IPMI controller 8 bit ...

Page 153: ... 25 Processor Memory Address Map 8000000016 EF7FFFFF16 1784 MByte PCI to PCI memory 64 bit EF80000016 EFFFFFFF16 8 MByte PCI to PCI I O space 64 bit F000000016 FFFFFFFF16 See Table 25 Processor Memory Address Map Table 27 I2C Address Map Bus Address Device SENTINEL I2C 1010000x2 A016 Serial ROM for SENTINEL registers Local I2C 1010000x2 A016 Board information block Local I2C 1010101x2 AA16 RTB inf...

Page 154: ...refer to the GT 64260A System Controller for PowerPC Processors datasheet System Controller MPP Configuration The system controller contains 32 multi purpose pins MPPs Each one can be assigned to a different functionality through the MPP Control registers for further information refer to the GT 64260A System Controller for Pow erPC Processors datasheet The MPP pins can be used as hardware control ...

Page 155: ...ut Active low 27 26 25 24 GPP 27 GPP 26 GPP 25 GPP 24 PCI bus 0 interrupts Input Active low 23 GPP 23 Watchdog interrupt in Input Active low 22 GPP 22 Reserved Input Active low 21 20 19 GPP 21 GPP 20 GPP 19 IPMI interrupts Input Active high 18 GPP 18 Ejector interrupt Input Active low 17 GPP 17 CompactPCI interrupt DEG Input Active low 16 GPP 16 CompactPCI interrupt FAL Input Active low 15 GPP 15 ...

Page 156: ...t Active low 2 GNT1 1 PCI bus 1 GNT Output Active low 1 REQ1 0 PCI bus 1 REQ Input Active low 0 GNT1 0 PCI bus 1 GNT Output Active low Table 29 System Controller MPP Configuration cont MPP Function Description Direction Polarity Table 30 External Interrupt Sources GPP Interrupt Description Source Polarity 31 30 29 28 PCI1_INTD PCI1_INTC PCI1_INTB PCI1_INTA Shared PCI interrupts from PCI bus 1 See ...

Page 157: ...s asserted if the board is installed into a PSB backplane without CompactPCI bus Hot swap switch Active low 17 CPCI_DEG Power supply status inter rupt from the Compact PCI backplane CompactPCI Active low 16 CPCI_FAL Power supply status inter rupt from the Compact PCI backplane CompactPCI Active low Table 30 External Interrupt Sources cont GPP Interrupt Description Source Polarity ...

Page 158: ...reset or Ethernet 1 2 and 3 link activity Note If the board is plugged into a PSB backplane without PCI bus opening the handle generates an EJECT_INT interrupt which indicates that the board is to be removed from the backplane Therefore bit 6 has to be set to 1 Table 31 LED Control Register Base Address F000000016 Offset 0016 Bit Signal Description Access 1 0 USER_LED1 Controls User LED 1 00 OFF 0...

Page 159: ...ress F000000016 Offset 0016 Bit Signal Description Access Table 32 Software Reset Register Base Address F000000016 Offset 0116 Bit Signal Description Access 7 0 SW_RESET Type of software initiated reset 1116 Board Reset r w Table 33 Miscellaneous Status Register Base Address F000000016 Offset 0216 Bit Signal Description Access 0 RTB_PRESENT Rear transition board 0 Not present 1 Present r 1 PMC1_PR...

Page 160: ...ash 1 is selected switch is ON r 1 SW2_BOOT_WE 0 Boot flash write protected switch is OFF 1 Boot flash write enabled switch is ON r 2 SW2_FLASH_WP 0 User flash write enabled switch is OFF 1 User flash write protected switch is ON r 3 SW2_PCI0_RST_DIS 0 PCI bus 0 reset enabled switch is OFF 1 PCI bus 0 reset disabled switch is ON r 4 SW4_RSV1 Reserved Switch 0 Default switch is OFF r 5 SW4_RSV2 Res...

Page 161: ...er Base Address F000000016 Offset 0416 Bit Signal Description Access 2 0 SDRAM_SIZE SDRAM configuration 000 Reserved 001 256 MByte 010 512 MByte 011 768 MByte 100 1 GByte 101 1 5 GByte 110 2 GByte 111 Reserved r 3 FLASH_SIZE User flash configuration 0 32 MByte 1 64 MByte r 4 SDRAM CAS SDRAM CAS latency 0 CAS latency is 3 1 CAS latency is 2 r 7 5 FPGA_REVISION FPGA revision status 000 Revision 1 0 ...

Page 162: ...CI_PRST CompactPCI push button reset 0 This type was not reason for last reset 1 This type was reason for last reset r 3 CPCI_RST CompactPCI reset 0 This type was not reason for last reset 1 This type was reason for last reset r 4 WD_RST Discovery watchdog reset 0 This type was not reason for last reset 1 This type was reason for last reset r 5 IPMI_RST IPMI reset 0 This type was not reason for la...

Page 163: ... information on the type of the last hardware reset Table 37 Last Reset Status Register 2 Base Address F000000016 Offset 0616 Bit Signal Description Access 0 SW_RST Software requested board reset 0 This type was not reason for last reset 1 This type was reason for last reset r 7 1 Reserved Reserved 0000000 Default r ...

Page 164: ...Register Maps and Registers 6 16 PPC CPCI 690 ...

Page 165: ...A Battery Exchange ...

Page 166: ......

Page 167: ... board damage Therefore make sure the battery is installed as described below Data loss Exchanging the battery after ten years of actual battery use have elapsed results in data loss Therefore exchange the battery before ten years have elapsed Data loss Exchanging the battery always results in data loss of the devices which use the battery as power backup Therefore backup affected data before exch...

Page 168: ...follow the instructions below 1 Remove board from backplane For board removal procedure see Board Installation page 2 16 2 Remove battery 3 When installing new battery ensure that dot on battery is in cor rect position see figure below Figure 20 Dot Position on Battery ...

Page 169: ...B Troubleshooting ...

Page 170: ......

Page 171: ...ical After Power On Problem Possible Reason Solution Unable to insert board into backplane Damaged plugs bent or broken pins backplane defect 1 Check CompactPCI slot position to be used for bent or broken pins 2 Replace backplane Board defect Replace board Keying of backplane does not fit to board 1 Check if you use correct board variant and replace board if neces sary 2 Replace backplane Problem ...

Page 172: ...or rectly Set interrupts correctly Wrong configuration of boot devices Configure boot devices cor rectly e g via PowerBoot set boot command Problem Possible Reason Solution Application software does not work Memory ranges of system and peripheral boards do not match Change application software so that memory ranges match I O cards and host Not enough disk capacity on mass storage device Add disk c...

Page 173: ...specified ranges Drivers are missing faulty or do not match hardware 1 Check that all used hardware parts have a driver matching the hardware 2 Reinstall hardware drivers Board defect Replace board Low system perfor mance Caches are disabled Enable caches Memory PMC mod ule does not work Module defect Replace module Module not defined for the used board 1 Check if module speci fication matches wit...

Page 174: ...fect Replace RTB RTB installed on wrong slot position Install RTB on adjacent slot position of the used board RTB not defined for the used peripheral or system board Install RTB defined for the used peripheral or system board Problem Possible Reason Solution ...

Page 175: ...current protection 2 7 Interrupt 4 12 4 20 4 21 5 10 NMI 5 5 Routing 5 8 5 12 Signal 2 19 IPMI 1 5 2 14 4 13 4 29 IPMI firmware upgrade 4 40 P PSB 1 5 2 16 3 3 3 5 R RJ45 3 7 S SDRAM 4 4 4 7 5 4 5 7 6 13 SENTINEL 1 5 2 19 4 12 4 20 4 25 Signaling level of PMC interface 2 9 System controller 2 16 3 6 6 4 6 7 6 8 T Temperature 2 5 2 6 Temperature sensor 5 16 5 17 W Watchdog 4 7 4 20 5 5 Enable 4 12 ...

Page 176: ...I 2 PPC CPCI 690 ...

Reviews:

No comments