Motorola PPC/CPCI-690, Reference Manual

Page: 154 / 176

Interrupt Map Maps and Registers
6 - 6 PPC/CPCI-690
Interrupt Map
The PowerPC 750FX/750GX processor provides three low active interrupt
inputs that are driven by the system controller:
• MCP# - machine check interrupt (NMI#)
• SMI# - system management interrupt
• INT# - standard CPU interrupt
The MCP# interrupt has highest priority followed by SMI# and INT#.
Interrupt Controller
The system controller includes an interrupt controller that routes internal
and external interrupt requests to both, the processor and the PCI buses 1
or 2.
Each of the internal or external interrupt sources can be enabled, disabled,
and routed completely by software. The interrupt controller can be config-
ured via the Interrupt Controller registers (for further information, refer to
the GT-64260A System Controller for PowerPC Processors datasheet).
System Controller MPP Configuration
The system controller contains 32 multi purpose pins (MPPs). Each one can
be assigned to a different functionality through the MPP Control registers
(for further information, refer to the GT-64260A System Controller for Pow-
erPC Processors datasheet
).
The MPP pins can be used as hardware control
signals to the system controller’s different interfaces or as general purpose
ports (GPP).
Each of the GPP pins can be assigned to act as a general purpose input or
output pin. They can be used to register external interrupts when assigned
as input pin. The GPP pins can be configured via the General Purpose Port
registers. The required CPCI-690 settings for the registers are shown in the
table below.
Table 28: MPP and GPP Register Settings
Register Address Data
MPP Control 0 F100F000
16
88888888
16
MPP Control 1 F100F004
16
00669977
16