Motorola PPC/CPCI-690, Reference Manual, Page: 135 / 176

Buses Memory Bus
PPC/CPCI-690 5 - 7
Memory Bus
The system controller has a 3.3V SDRAM interface running at frequencies
up to 133 MHz. The interface consists of a 15-bit wide address bus and a 64-
bit data bus plus eight additional bits for error checking and correction
(ECC). Two bits of the address bus are used for bank select, 13 bits are used
for row and column address.
The board is equipped with PC133 compliant unregistered SDRAM memo-
ry devices and has a maximum capacity from 256 MByte up to 1 GByte. If
the maximum capacity is 256 MByte, one bank is equipped with 256 MBit
devices and if it is 1 GByte, two banks are equipped with 512 MBit devices
using dense-pack three level stacking technology.
Table 15: Memory Bus Characteristics
Memory Characteristics Memory Capacity
below 1 GByte Memory Capacity
1 GByte
Memory speed 133 MHz 100 MHz
CAS support CAS 3 CAS 2