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Motorola Computer Group Documents

The publications listed below are on related products, and some may be 
referenced in this document. If not shipped with this product, manuals may 
be purchased by contacting your local Motorola sales office.

Note

Although not shown in the above list, each Motorola 
Computer Group manual publication number is suffixed with 
characters that represent the revision level of the document, 
such as “/xx2” (the second revision of a manual); a 
supplement bears the same number as the manual but has a 
suffix such as “/xx2A1” (the first supplement to the second 
revision of the manual).

Table A-1.  Motorola Computer Group Documents

Document Title

Publication

Number

 

MVME2400-Series VME Processor Module 
Installation and Use (this manual) 

V2400A/IH

MVME2400-Series VME Processor Module 
Programmer’s Reference Guide 

V2400A/PG

PPCBug Firmware Package User’s Manual (Parts 1 and 2) 

PPCBUGA1/UM

PPCBUGA2/UM

PPCBug 

Diagnostics 

Manual PPCDIAA/UM

PMCspan PMC Adapter Carrier Module Installation and Use

PMCSPANA/IH

Summary of Contents for MVME2401-1

Page 1: ...MVME2400 Series Single Board Computer Installation and Use V2400A IH1 ...

Page 2: ...rior written permission of Motorola Inc It is possible that this publication may contain reference to or information about Motorola products machines and programs programming or services that are not announced in your country Such references or information must not be construed to mean that Motorola intends to announce such Motorola products programming or services in your country Restricted Right...

Page 3: ...gging firmware and advanced debugger topics Other appendices provide the MVME2400 series specifications connector pin assignments and a glossary of terms Additional manuals you may wish to obtain are listed in Appendix A Ordering Related Documentation The information in this manual applies principally to the MVME2400 series module The PMCspan and PMCs are described briefly here but are documented ...

Page 4: ...llowing the signal name for signals which are edge significant denotes that the actions initiated by that signal occur on high to low transition In this manual assertion and negation are used to specify forcing a signal to a particular state In particular assertion and assert refer to a signal that is active or true negation and negate indicate a signal that is inactive or false These terms are us...

Page 5: ... or other qualified maintenance personnel may remove equipment covers for internal subassembly or component replacement or any internal adjustment Do not replace components with power cable connected Under certain conditions dangerous voltages may exist even with the power cable removed To avoid injuries always disconnect power and discharge circuits before touching them Do Not Service or Adjust A...

Page 6: ...Frequency Electromagnetic Field Immunity Test EN 61000 4 4 Electrical Fast Transient Burst Immunity Test EN 61000 4 5 Surge Immunity Test EN 61000 4 6 Conducted Disturbances Induced by Radio Frequency Fields Immunity Test EN 61000 4 11 Voltage Dips Short Interruptions and Voltage Variations Immunity Test ENV 50204 Radiated Electromagnetic Field from Digital Radio Telephones Immunity Test In accord...

Page 7: ...are and documentation are copyrighted materials Making unauthorized copies is prohibited by law No part of the software or documentation may be reproduced transmitted transcribed stored in a retrieval system or translated into any language or computer language in any form or by any means without the prior written permission of Motorola Inc Motorola and the Motorola symbol are registered trademarks...

Page 8: ......

Page 9: ...E240x 1 7 Setting the Flash Memory Bank A Bank B Reset Vector Header J8 1 10 Setting the VMEbus System Controller Selection Header J9 1 10 Setting the General Purpose Software Readable Header SRH Switch S3 1 11 PMCs 1 12 PMCspan 1 12 System Console Terminal 1 12 Installing the MVME240x Hardware 1 13 ESD Precautions 1 13 PMCs 1 13 Primary PMCspan 1 16 Secondary PMCspan 1 18 MVME240x 1 21 Installati...

Page 10: ... ASIC 3 7 PCI Bus Latency 3 8 PPC Bus Latency 3 10 Assumptions 3 12 Clock Ratios and Operating Frequencies 3 13 PPC60x Originated 3 13 PCI Originated 3 14 SDRAM Memory 3 14 SDRAM Latency 3 15 Flash Memory 3 19 ROM Flash Performance 3 19 Ethernet Interface 3 22 PCI Mezzanine Card PMC Interface 3 23 PMC Slot 1 Single Width PMC 3 23 PMC Slot 2 Single Width PMC 3 24 PMC Slots 1 and 2 Double Width PMC ...

Page 11: ...rupt Handling 4 6 DMA Channels 4 8 Sources of Reset 4 8 Endian Issues 4 10 Processor Memory Domain 4 10 PCI Domain 4 10 VMEbus Domain 4 11 CHAPTER 5 PPCBug PPCBug Overview 5 1 PPCBug Basics 5 1 Memory Requirements 5 3 PPCBug Implementation 5 3 MPU Hardware and Firmware Initialization 5 3 Using PPCBug 5 5 Debugger Commands 5 6 Diagnostic Tests 5 10 CHAPTER 6 Modifying the Environment Overview 6 1 C...

Page 12: ... Pin Assignments Introduction C 1 Pin Assignments C 1 VMEbus Connector P1 C 2 VMEbus Connector P2 C 4 Serial Port Connector DEBUG J2 C 6 Ethernet Connector 10BASET J3 C 6 CPU Debug Connector J1 C 7 PCI Expansion Connector J6 C 12 PCI Mezzanine Card Connectors J11 through J14 C 15 PCI Mezzanine Card Connectors J21 through J24 C 18 APPENDIX D Troubleshooting the MVME240x Solving Startup Problems D 1...

Page 13: ...MC Module Placement on MVME240x 1 15 Figure 1 4 PMCspan 002 Installation on an MVME240x 1 17 Figure 1 5 PMCspan 010 Installation onto a PMCspan 002 MVME240x 1 19 Figure 2 1 MVME240x DEBUG Port Configuration 2 6 Figure 3 1 MVME240x Block Diagram 3 5 Figure 3 2 Memory Block Diagram 3 10 Figure 4 1 VMEbus Master Mapping 4 5 Figure 4 2 MVME240x Interrupt Architecture 4 7 ...

Page 14: ...xiv ...

Page 15: ...mands 5 7 Table 5 2 Diagnostic Test Groups 5 12 Table A 1 Motorola Computer Group Documents A 1 Table A 2 Manufacturers Documents A 2 Table A 3 Related Specifications A 5 Table B 1 MVME240x Specifications B 1 Table C 1 P1 VMEbus Connector Pin Assignments C 2 Table C 2 P2 Connector Pin Assignment C 4 Table C 3 DEBUG J2 Connector Pin Assignments C 6 Table C 4 10 100 BASET J3 Connector Pin Assignment...

Page 16: ...xvi ...

Page 17: ...t panel cutouts provide access to PMC I O One double width or two single width PMCs can be installed directly on the MVME240x Optionally one or two PMCspan PCI expansion mezzanine modules can be added to provide the capability of up to four additional PMC modules Two RJ45 connectors on the front panel provide the interface to 10 100Base T Ethernet and to a debug serial port The following list is o...

Page 18: ...optional PCI expansion mezzanine modules are also used The MVME240x interfaces to the VMEbus via the P1 and P2 connectors which use the new 5 row 160 pin connectors as specified in the proposed VME64 Extension Standard It also draws 5V 12V and 12V power from the VMEbus backplane through these two connectors The 3 3V and 2 5V power used for the PCI bridge chip and possibly for the PMC mezzanine is ...

Page 19: ...le or PMC carrier board PMCspan provides the capability of adding two additional PMCs Two PMCspans can be stacked on an MVME240x providing four additional PMC slots for a total of six slots including the two onboard the MVME240x Table 1 2 lists the PMCspan models that are available for use with the MVME240x PCI Mezzanine Cards PMCs The PMC slots on the MVME240x board are IEEE P1386 1 compliant P2 ...

Page 20: ...bug console terminal is required only if you intend to use the MVME240x s debug firmware PPCBug interactively An RJ45 connector is provided on the front panel of the MVME240x for this purpose Overview of Start Up Procedures The following table lists the things you will need to do before you can use this board and tells where to find the information you need to perform each step Be sure to read thi...

Page 21: ...nformation on PMCs refer to the PMC manuals provided with these cards Install the primary PMCspan module if used Primary PMCspan 1 16 For additional information on PMCspan refer to the PMCspan PMC Adapter Carrier Module Installation and Use manual listed in Appendix A Ordering Related Documentation A 1 Install the secondary PMCspan module if used Secondary PMCspan 1 18 For additional information o...

Page 22: ...Manual listed in Appendix A Ordering Related Documentation A 1 Examine the environmental parameters and make any changes needed ENV Set Environment 6 3 You may also wish to obtain the PPCBug Firmware Package User s Manual listed in Appendix A Ordering Related Documentation A 1 Program the MVME240x module and PMCs as needed for your applications Preparing the MVME240x Hardware 1 7 Programming the M...

Page 23: ...ware To produce the desired configuration and ensure proper operation of the MVME240x you may need to carry out certain modifications before and after installing the modules The following paragraphs discuss the preparation of the MVME240x hardware components prior to installing them into a chassis and connecting them MVME240x The MVME240x provides software control over most options by setting bits...

Page 24: ... Figure 1 1 illustrates the placement of the switches jumper headers connectors and LED indicators on the MVME240x Manually configurable items on the MVME240x include Flash memory bank A bank B reset vector J8 VMEbus system controller selection header J9 General purpose software readable header S3 The MVME240x has been factory tested and is shipped with the configurations described in the followin...

Page 25: ...1 J9 J5 8 1 J11 J22 J21 J1 ETHERNET PORT J3 ABORT SWITCH RESET SWITCH DS 1 S1 S2 VME BUS PCI MEZZANINE CARD PCI MEZZANINE CARD J24 J23 J14 J13 J6 3 DEBUG PORT J2 DS 2 DS 3 DS 4 1 2 113 114 1 2 64 63 1 2 64 63 1 2 64 63 1 2 64 63 1 2 64 63 1 2 64 63 1 2 64 63 1 2 64 63 1 2 189 190 DEBUG CPU BFL PMC PMC 2 PMC1 3 1 J8 FLASH SOCKETS XU1 XU2 U9 D32 D1 D32 D1 U22 U17 U25 U23 U18 U21 U16 U19 U20 U15 U10 ...

Page 26: ... factory configuration or between J8 pins 2 and 3 for Bank B When the jumper is installed the SMC System Memory Controller of the Hawk ASIC maps 0xFFF00100 to the Bank B sockets Setting the VMEbus System Controller Selection Header J9 The MVME240x is factory configured in automatic system controller mode i e a jumper is installed across pins 2 and 3 of header J9 This means that the MVME240x determ...

Page 27: ... that particular bit SRH Register Bit 0 is associated with Pin 1 and Pin 16 of the SRH and SRH Register Bit 7 is associated with Pin 8 and Pin 9 of the SRH The SRH is a read only register If Motorola s PowerPC firmware PPCBug is being used it reserves all bits SRH0 to SRH7 If it is not being used the switch can be used for other applications Figure 1 2 General Purpose Software Readable Header 1 2 ...

Page 28: ...the PMCspan PMCAdapter Carrier Module Instllation and Use manual for instructions System Console Terminal Ensure that the switches are set in the proper position for all bits on switch S3 of the MVME240x board as shown in Figure 1 2 This is necessary when the PPCBug firmware is used Connect the terminal via a cable to the RJ45 DEBUG connector J2 See Table C 3 for pin signal assignments Set up the ...

Page 29: ...ase of a board component side up Do not slide the component over any surface If an ESD station is not available you can avoid damage resulting from ESD by wearing an antistatic wrist strap available at electronics stores that is attached to an unpainted metal part of the system chassis PMCs PCI mezzanine card PMC modules mount on top of the MVME240x module and or on a PMCspan Refer to Figure 1 3 a...

Page 30: ...uipment Use extreme caution when handling testing and adjusting 3 If the MVME240x has already been installed in a VMEbus card slot carefully remove it Lay the MVME240x flat with connectors P1 and P2 facing you Caution Avoid touching areas of integrated circuitry static discharge can damage these circuits 4 Remove the PCI filler plate from the selected PMC slot in the front panel of the MVME240x If...

Page 31: ...0x The four connectors on the underside of the PMC module should then connect smoothly with the corresponding connectors for a single width PMC J11 J12 J13 J14 or J21 J22 J23 J24 all eight for a double width PMC on the MVME240x 6 Insert the two short Phillips screws through the holes at the forward corners of the PMC module into the standoffs on the MVME240x Tighten the screws 7 If installing two ...

Page 32: ...red to your wrist and to ground while you are performing the installation procedure 2 Perform an operating system shutdown Turn the AC or DC power off and remove the AC cord or DC power lines from the system Remove chassis or system cover s as necessary for access to the VME module card cage Caution Inserting or removing modules with power applied may result in damage to module components Warning ...

Page 33: ...Installing the MVME240x Hardware http www mcg mot com literature 1 17 1 Figure 1 4 PMCspan 002 Installation on an MVME240x 2081 9708 P4 J6 ...

Page 34: ...h the holes at the corners of the PMCspan and into the standoffs on the MVME240x module Tighten the screws Note The screws have two different head diameters Use the screws with the smaller heads on the standoffs next to VMEbus connectors P1 and P2 Secondary PMCspan The PMCspan 010 PCI expansion module mounts on top of a PMCspan 002 PCI expansion module To install a PMCspan 010 on your MVME240x ref...

Page 35: ...Installing the MVME240x Hardware http www mcg mot com literature 1 19 1 Figure 1 5 PMCspan 010 Installation onto a PMCspan 002 MVME240x 2065 9708 P3 J3 ...

Page 36: ...us card slots and lay it flat with the P1 and P2 connectors facing you Caution Avoid touching areas of integrated circuitry static discharge can damage these circuits 4 Remove the four short Phillips screws from the standoffs in each corner of the primary PCI expansion module PMCspan 002 5 Attach the four standoffs to the PMCspan 002 6 Place the PMCspan 010 on top of the PMCspan 002 Align the moun...

Page 37: ...ground throughout the procedure 2 Perform an operating system shutdown a Turn the AC or DC power off and remove the AC cord or DC power lines from the system Caution Inserting or removing modules with power applied may result in damage to module components Warning Dangerous voltages capable of causing death are present in this equipment Use extreme caution when handling testing and adjusting b Rem...

Page 38: ...rly in the P1 and P2 connectors on the backplane Do not damage or bend connector pins 5 Secure the MVME240x and PMCspans if used in the chassis with the screws provided making good contact with the transverse mounting rails to minimize RF emissions Note Some VME backplanes e g those used in Motorola Modular Chassis systems have an auto jumpering feature for automatic propagation of the IACK and BG...

Page 39: ...s in the system must be handled by the PowerPC processor software Refer to the memory maps in Chapter 4 The MVME240x contains shared onboard DRAM whose base address is software selectable Both the onboard processor and off board VMEbus devices see this local DRAM at base physical address 00000000 as programmed by the PPCBug firmware This may be changed via software to any other base address Refer ...

Page 40: ...disable communicate with and determine the operational status of the processor s One register of the Universe set includes four bits that function as location monitors to allow one MVME240x processor to broadcast a signal to any other MVME240x processors All eight registers are accessible from any local processor as well as from the VMEbus ...

Page 41: ...cess is performed by the PPCBug firmware power up or system reset The firmware initializes the devices on the MVME240x module in preparation for booting the operating system The firmware is shipped from the factory with an appropriate set of defaults In most cases there is no need to modify the firmware configuration before you boot the operating system Refer to Chapter 6 for further information a...

Page 42: ...our LED light emitting diode status indicators BFL CPU PMC two located on the MVME240x front panel STARTUP INITIALIZATION MONITOR BOOTING POST Power up reset initialization Initialize devices on the MVME240x Power On Self Test diagnostics Firmware configured boot mechanism Interactive command driven on line PowerPC debugger when terminal connected if so configured Default is no boot module system ...

Page 43: ... signal if the MVME240x VME processor module is the system controller The Universe ASIC includes both a global and a local reset driver When the Universe operates as the VMEbus system controller the reset driver provides a global system reset by asserting the VMEbus signal SYSRESET A SYSRESET signal may be generated by the RESET switch a power up reset a watchdog timeout or by a control bit in the...

Page 44: ...3 The top green PMC LED indicates PCI activity lights when the PCI bus grant to PMC2 signal line on the PCI bus is active This indicates that a PMC installed on slot 2 is active PMC1 DS4 The bottom green PMC LED indicates PCI activity lights when the PCI bus grant to PMC1 signal line on the PCI bus is active This indicates that a PMC installed on slot 1 is active 10 100 BASET Port The RJ45 port on...

Page 45: ...or EIA 232 D DTE as shown in Figure 2 1 The DEBUG port may be used for connecting a terminal to the MVME240x to serve as the firmware console for the factory installed debugger PPCBug The port is configured as follows 8 bits per character 1 stop bit per character Parity disabled no parity Baud rate 9600 baud default baud rate at power up After power up the baud rate of the DEBUG port can be reconf...

Page 46: ...2 6 Computer Group Literature Center Web Site Operating Instructions 2 Figure 2 1 MVME240x DEBUG Port Configuration SOUT RTS DTR SIN CTS DCD Debug PC16550 MVME240x 4 2 8 7 5 1 6 3 RJ45 ...

Page 47: ...al for the particular PMC PCI MEZZANINE CARD PMC Slot 1 The right most lower opening labeled PCI MEZZANINE CARD on the MVME240x front panel provides front panel I O access to a PMC that is connected to the 64 pin connectors J11 through J14 on the MVME240x module Connector J14 allows rear panel P2 I O This slot is MVME240x Port 1 PCI MEZZANINE CARD PMC Slot 2 The left most upper opening labeled PCI...

Page 48: ...ctors for PMC interface to a secondary PCI bus and a user specific I O It also has a P1 connector and a 5 row P2 connector for power and VMEbus I O The PMCspan has two green LEDs on its front panel one for each PMC slot labeled PMC2 and PMC1 Both LEDs are illuminated during reset An individual LED is illuminated whenever a PMC has been granted bus mastership of the secondary PCI bus The right most...

Page 49: ...found in the MVME2400 Series VME Processor Module Programmer s Reference Guide part number V2400A PG Refer to it for a functional description of the MVME240x in greater depth Features The following table summarizes the features of the MVME240x VME processor module Table 3 1 MVME240x Features Feature Description Microprocessor 233 MHZ MPC750 PowerPCTM processor MVME2401 2402 models 350 MHZ MPC750 P...

Page 50: ...async serial port routed to front panel RJ45 10BaseT 100BaseTX Ethernet interface routed to front panel RJ45 Switches Reset RST and Abort ABT Status LEDs Four Board fail BFL CPU PMC one for PMC slot 2 one for slot 1 Timers One 16 bit timer in W83C553 ISA bridge four 32 bit timers in MPIC device Watchdog timer provided in SGS Thomson M48T59 VME I O VMEbus P2 connector PCI interface Two IEEE P1386 1...

Page 51: ...rface A32 A24 A16 D64 MBLT D32 D16 D08 Master and Slave Local bus to VMEbus interface A16 A24 A32 D8 D16 D32 VMEbus interrupter VMEbus interrupt handler Global Control Status Register GCSR for interprocessor communications DMA for fast local memory VMEbus transfers A16 A24 A32 D16 D32 D64 Table 3 1 MVME240x Features Continued Feature Description ...

Page 52: ...rtion of the Hawk ASIC provides the interface from the Processor Bus to the PCI A W83C553 PCI ISA Bridge PIB Controller device performs the bridge function between PCI and ISA The Universe ASIC device provides the interface between the PCI Local Bus and the VMEbus Part of the Hawk ASIC is the ECC memory controller The Peripheral Component Interface PCI local bus is a key feature In addition to the...

Page 53: ...n System Registers FLASH 1MB to 9MB Clock Generator VME Bridge Universe Ethernet PIB W83c553 Buffers 10 100TX serial port ISA Registers RTC NVRAM WD MK48T559 TL16C550 UART Front Panel SDRAM 32 64 128MB ISA Bus VME P2 RJ45 RJ45 PMC FrontIO PMC Front IO SLot1 Slot2 2 64 bit PMC Slot L2 Cache 512KB Processor MPC750 or 1M Hawk ASIC System Memory Controller SMC and PCI Host Bridge PHB DEC21143 ...

Page 54: ...s a back door L2 cache structure via the MPC750 processor chip The MCP750 s L2 cache is implemented with an onchip 2 way set associative tag memory and external direct mapped synchronous SRAMs for data storage The external SRAMs are accessed through a dedicated 72 bit wide 64 bits of data and 8 bits of parity L2 cache port The board is populated with 1MB of L2 cache SRAMs The L2 cache can operate ...

Page 55: ...nal bus frequencies up to 100MHz There are four programmable map decoders for each direction to provide flexible address mappings between the MPC and the PCI Local Bus Refer to the MVME2400 Programmer s Reference Guide for additional information The Hawk ASIC also provides an MPIC Interrupt Controller to handle various interrupt sources The interrupt sources are Four MPIC Timer Interrupts the inte...

Page 56: ...at 1 Beat 2 Beat 3 Beat 4 Total Burst Read 9 1 1 1 12 9 1 1 1 12 5 2 Burst Write 3 1 1 1 6 3 1 1 1 6 Single Read 9 9 9 9 Single Write 3 3 3 3 Burst Read 12 1 1 1 15 12 1 1 1 15 3 2 Burst Write 3 1 1 1 6 3 1 1 1 6 Single Read 12 12 12 12 Single Write 3 3 3 3 Burst Read 9 1 1 1 12 9 1 1 1 12 3 1 Burst Write 3 1 1 1 6 3 1 1 1 6 Single Read 9 9 Single Write 3 3 Burst Read 11 1 1 1 14 11 1 1 1 14 2 1 B...

Page 57: ...7 18 474 26 492 4 533 3 2 64 bit Reads 19 225 27 316 37 346 4 533 32 bit Writes 18 237 34 251 50 256 8 267 32 bit Reads 28 152 44 194 60 213 8 267 64 bit Writes 10 213 18 237 26 246 4 266 3 1 64 bit Reads 16 133 24 178 32 200 4 266 32 bit Writes 18 118 34 125 50 128 8 133 32 bit Reads 24 89 40 107 56 114 8 133 64 bit Writes 10 213 18 237 26 246 4 266 2 1 64 bit Reads 18 118 26 164 34 188 4 266 32 ...

Page 58: ... Beat 2 Beat 3 Beat 4 Total Beat 1 Beat 2 Beat 3 Beat 4 Total Burst Read 40 1 1 1 43 29 1 1 1 32 5 2 Burst Write 5 1 1 1 8 5 1 1 1 8 Single Read 22 22 Single Write 5 5 Burst Read 26 1 1 1 29 20 1 1 1 23 3 2 Burst Write 5 1 1 1 8 5 1 1 1 8 Single Read 16 16 Single Write 5 5 Burst Read 45 1 1 1 48 33 1 1 1 36 3 1 Burst Write 5 1 1 1 8 5 1 1 1 8 Single Read 24 24 Single Write 5 5 Burst Read 33 1 1 1 ...

Page 59: ...78 137 148 108 35 76 32 bit Reads 42 5 63 64 bit Writes 14 457 38 337 68 282 15 213 3 2 64 bit Reads 22 5 142 32 bit Writes 14 457 50 256 92 209 21 152 32 bit Reads 28 5 112 64 bit Writes 14 457 67 191 127 151 30 107 3 1 64 bit Reads 36 89 32 bit Writes 14 457 98 131 182 105 42 76 32 bit Reads 48 67 64 bit Writes 14 305 48 178 88 145 20 107 2 1 64 bit Reads 28 76 32 bit Writes 14 305 64 133 120 10...

Page 60: ...it Writes 18 118 34 125 50 128 8 133 32 bit Reads 24 89 40 107 56 114 8 133 64 bit Writes 10 427 18 474 26 492 4 533 3 2 64 bit Reads 19 225 27 316 37 346 4 533 32 bit Writes 18 237 34 251 50 256 8 267 32 bit Reads 28 152 44 194 60 213 8 267 64 bit Writes 10 213 18 237 26 246 4 266 3 1 64 bit Reads 16 133 24 178 32 200 4 266 32 bit Writes 18 118 34 125 50 128 8 133 32 bit Reads 24 89 40 107 56 114...

Page 61: ...ts on the same clock period that TS_ is asserted PPC60x bus is idle at the time of the start of the transaction i e no pipelining effects Cache aligned transfer not critical word first PCI medium responder with no zero states One clock request one clock grant PCI arbitration Write posting enabled Default FIFO threshold settings Single beat writes are aligned 32 bit transfer always executed aws 32 ...

Page 62: ...affic limited to PHB transactions only Write posting and read adhead enabled Default FIFO threshold settings One cache line 32 bytes SDRAM Memory The MVME2400 SDRAM memory size can be 32MB 64MB or 128MB The SDRAM blocks are controlled by the Hawk ASIC which provides single bit error correction and double bit error detection ECC is calculated over 72 bits The memory block size is dependant upon the...

Page 63: ... The figure on the next page defines the times that are specified in the table Table 3 9 60x Bus to SDRAM Access Timing 100MHz PC100 SDRAMs ACCESS TYPE Access Time tB1 tB2 tB3 tB4 Comments 4 Beat Read after idle SDRAM Bank Inactive 10 1 1 1 4 Beat Read after idle SDRAM Bank Active Page Miss 12 1 1 1 4 Beat Read after idle SDRAM Bank Active Page Hit 7 1 1 1 4 Beat Read after 4 Beat Read SDRAM Bank ...

Page 64: ...SDRAM Bank Active Page Miss 12 1 Beat Read after idle SDRAM Bank Active Page Hit 7 1 Beat Read after 1 Beat Read SDRAM Bank Active Page Miss 8 1 Beat Read after 1 Beat Read SDRAM Bank Active Page Hit 5 1 Beat Write after idle SDRAM Bank Active or Inactive 5 1 Beat Write after 1 Beat Write SDRAM Bank Active Page Miss 13 1 Beat Write after 1 Beat Write SDRAM Bank Active Page Hit 8 Table 3 9 60x Bus ...

Page 65: ...ods tRAS 5 CLK Periods tRC 7 CLK Periods tDP 2 CLK Periods and the swr_dpl bit is set in the SDRAM Speed Attributes Register 2 The Hawk is configured for no external registers on the SDRAM control signals 3 tB1 tB2 tB3 and tB4 are specified in the following figure Figure 3 2 Timing Definitions for PPC Bus to SDRAM Access tB1 From Idle tB1 Back to Back tB2 tB3 tB4 ...

Page 66: ...o the rising edge of the CLK that samples the first TA_ low of the next data tenure The tB2 function reflects the number of CLK periods from the rising edge of the CLK that samples the first TA_ low in a burst data tenure to the rising edge of the CLK that samples the second TA_ low in that data tenure The tB3 function reflects the number of CLK periods from the rising edge of the CLK that samples...

Page 67: ... provides functionality for Booting the system Initializing after a reset Displaying and modifying configuration variables Running self tests and diagnostics Updating firmware ROM Under normal operation the Flash devices are in read only mode their contents are pre defined and they are protected against inadvertent writes due to loss of power conditions However for programming purposes programming...

Page 68: ...Beat 3rd Beat 4th Beat 16 Bits 64 Bits 16 Bits 64 Bits 16 Bits 64 Bits 16 Bits 64 Bits 16 Bits 64 Bits 4 Beat Read 70 22 64 16 64 16 64 16 262 70 4 Beat Write N A N A 1 Beat Read 1 byte 22 22 22 22 1 Beat Read 2 to 8 bytes 70 22 70 22 1 Beat Write 21 21 21 21 Table 3 11 PPC Bus to ROM Flash Access Timing 80ns 100MHz ACCESS TYPE CLOCK PERIODS REQUIRED FOR Total Clocks 1st Beat 2nd Beat 3rd Beat 4th...

Page 69: ...d Beat 4th Beat 16 Bits 64 Bits 16 Bits 64 Bits 16 Bits 64 Bits 16 Bits 64 Bits 16 Bits 64 Bits 4 Beat Read 42 15 36 9 36 9 36 9 150 42 4 Beat Write N A N A 1 Beat Read 1 byte 15 15 15 15 1 Beat Read 2 to 8 bytes 42 15 42 15 1 Beat Write 21 21 21 21 Table 3 13 PPC Bus to ROM Flash Access Timing 30ns 100MHz ACCESS TYPE CLOCK PERIODS REQUIRED FOR Total Clocks 1st Beat 2nd Beat 3rd Beat 4th Beat 16 B...

Page 70: ... the six bytes including the Ethernet station address are stored in the NVRAM BBRAM configuration area specified by boot ROM That is the value 08003E2xxxxx is stored in NVRAM The MVME240x debugger PPCBug has the capability to retrieve the Ethernet station address via the CNFG command Note The unique Ethernet address is set at the factory and should not be changed Any attempt to change this address...

Page 71: ...ne or two PMC carrier boards or PMCspan PCI expansion modules on the MVME240x for additional expansion The MVME240x supports two PMC slots Two sets of four 64 pin connectors on the base board J11 J14 and J21 J24 interface with 32 bit 64 bit IEEE P1386 1 PMC compatible mezzanines to add any desirable function Refer to Appendix C for the pin assignments of the PMC connectors For detailed programming...

Page 72: ... PMC slots 1 and 2 with a double width PMC have the following characteristics PCI Expansion The PMCspan expansion module connector J6 is a 114 pin Mictor connector It is located near P2 on the primary side of the MVME240x Its interrupt lines are routed to the MPIC Mezzanine Type PCI Mezzanine Card PMC Mezzanine Size S1B Single width standard depth 75mm x 150mm with front panel PMC Connectors J21 t...

Page 73: ...mmer s Reference Guide Maximum performance is achieved with D64 Multiplexed Block Transfers MBLT The on chip DMA channel should be used to move large blocks of data to from the VMEbus The Universe should be able to reach 50MB second in 64 bit MBLT mode The MVME2400 interfaces to the VMEbus via the P1 and P2 connectors which use the new 5 row 160 pin connectors as specified in the VME64 extension s...

Page 74: ...owing functions PCI bus arbitration for ISA Industry Standard Architecture bus DMA not functional on MVME240x The PHB PCI Host Bridge MPU local bus interface function implemented by the Hawk ASIC All on board PCI devices The PMC slot ISA bus arbitration for DMA devices ISA interrupt mapping for four PCI interrupts Interrupt controller functionality to support 14 ISA interrupts Edge level control f...

Page 75: ...month and year in BCD 24 hour format Corrections for 28 29 leap year and 30 day months are made automatically The clock generates no interrupts Although the M48T559 is an 8 bit device 8 16 and 32 bit accesses from the ISA bus to the M48T559 are supported Refer to the MVME2400 Series VME Processor Module Programmer s Reference Guide and to the M48T559 data sheet for detailed programming and battery...

Page 76: ...ice diagrammed in Figure 3 1 They can be programmed to generate periodic interrupts to the processor Interval Timers The PIB controller has three built in counters that are equivalent to those found in an 82C54 programmable interval timer The counters are grouped into one timer unit Timer 1 in the PIB controller Each counter output has a specific function Counter 0 is associated with interrupt req...

Page 77: ...s There is one 16 bit timer and four 32 bit timers on the MVME240x The 16 bit timer is provided by the PIB The Hawk device provides the four 32 bit timers that may be used for system timing or to generate periodic interrupts For information on programming these timers refer to the data sheet for the W83C553 PIB controller and to the MVME2400 Series VME Processor Module Programmer s Reference Guide...

Page 78: ...3 30 Computer Group Literature Center Web Site Functional Description 3 ...

Page 79: ...he PMCs refer to the applicable user s manual furnished with the PMCs Memory Maps There are multiple buses on the MVME240x and each bus domain has its own view of the memory map The following sections describe the MVME240x memory organization from the following three points of view The mapping of all resources as viewed by the MPU processor bus memory map The mapping of onboard resources as viewed...

Page 80: ...le 4 1 defines the entire default map 00000000 to FFFFFFFF Notes The first 1MB of Flash bank A soldered Flash up to 8MB appears in this range after a reset if the rom_b_rv control bit in the SMC s ROM B Base Size register is cleared If the rom_b_rv control bit is set this address range maps to Flash bank B socketed 1MB Flash Table 4 1 Processor Default View of the Memory Map Processor Address Size...

Page 81: ...application For detailed PCI memory maps including suggested CHRP and PREP compatible memory maps refer to the MVME2400 Series VME Processor Module Programmer s Reference Guide VMEbus Memory Map The VMEbus is programmable Like other parts of the MVME240x memory map the mapping of local resources as viewed by VMEbus masters varies among applications The Universe PCI VME bus bridge ASIC includes a u...

Page 82: ...the MVME240x Hawk ASIC MPU PCI bus bridge controller Winbond W83C553 PIB PCI ISA bus bridge controller DECchip 21143 Ethernet controller UniverseII ASIC PCI VME bus bridge controller PMC Slot 1 PCI mezzanine card PMC Slot 2 PCI mezzanine card PCI Expansion Slot The Winbond W83C553 PIB device supplies the PCI arbitration support for these seven types of devices The PIB supports flexible arbitration...

Page 83: ...A16 VME A24 VME A16 PROGRAMMABLE SPACE PCI MEMORY PROCESSOR PCI MEMORY SPACE PCI ISA MEMORY SPACE PCI I O SPACE MPC RESOURCES NOTE 1 NOTE 1 NOTE 2 NOTE 3 ONBOARD MEMORY 1 Programmable mapping done by Hawk ASIC 2 Programmable mapping performed via PCI Slave images in Universe ASIC 3 Programmable mapping performed via Special Slave image SLSI in Universe ASIC NOTES ...

Page 84: ...mer interrupts transfer error interrupts or memory error interrupts The processor processor self interrupts The PCI bus interrupts from PCI devices The ISA bus interrupts from ISA devices Figure 4 2 illustrates interrupt architecture on the MVME240x For details on interrupt handling refer to the MVME2400 Series VME Processor Module Programmer s Reference Guide Table 4 2 PCI Arbitration Assignments...

Page 85: ... literature 4 7 4 Figure 4 2 MVME240x Interrupt Architecture The MVME240x routes the interrupts from the PMCs and PCI expansion slots as follows 11559 00 9609 PIB 8529 Pair Processor INT_ MCP_ Hawk MPIC INT SERR_ PERR_ PCI Interrupts ISA Interrupts ...

Page 86: ...roller 3 Watchdog timer Reset function controlled by the SGS Thomson MK48T559 timekeeper device resets the VMEbus when the MVME240x is system controller 4 ALT_RST function controlled by the Port 92 register in the PIB resets the VMEbus when the MVME240x is system controller 5 PCI ISA I O Reset function controlled by the Clock Divisor register in the PIB 6 The VMEbus SYSRESET signal Hawk MPIC PMC S...

Page 87: ...s are affected by the various types of resets For details on using resets refer to the MVME2400 Series VME Processor Module Programmer s Reference Guide Table 4 3 Classes of Reset and Effectiveness Device Affected Processor Hawk ASIC PCI Devices ISA Devices VMEbus as system controller Reset Source Power On reset Reset switch Watchdog reset VME SYSRESET signal VME System SW reset VME Local SW reset...

Page 88: ...PU PCI bus bridge controller SMC memory controller as well as DRAM Flash and system registers always appear as big endian Role of the Hawk ASIC Because the PCI bus is little endian the PHB portion of the Hawk performs byte swapping in both directions from PCI to memory and from the processor to PCI to maintain address invariance while programmed to operate in big endian mode with the processor and...

Page 89: ...riance regardless of the mode of operation in the processor s domain VMEbus Domain The VMEbus is inherently big endian All devices connected directly to the VMEbus must operate in big endian mode regardless of the mode of operation in the processor s domain In big endian mode byte swapping is performed first by the Universe ASIC and then by the PHB The result is transparent to big endian software ...

Page 90: ...4 12 Computer Group Literature Center Web Site Programming the MVME240x 4 ...

Page 91: ... advanced user topics For full user information about PPCbug refer to the PPCBug Firmware Package User s Manual and the PPCBug Diagnostics Manual listed in the Related Documentation appendix PPCBug Basics The PowerPC debug firmware PPCBug is a powerful evaluation and debugging tool for systems built around the Motorola PowerPC microcomputers Facilities are available for loading and executing user ...

Page 92: ...or that accepts commands from the system console terminal When using PPCBug you operate out of either the debugger directory or the diagnostic directory If you are in the debugger directory the debugger prompt PPC4 Bug is displayed and you have all of the debugger commands at your disposal If you are in the diagnostic directory the diagnostic prompt PPC4 Diag is displayed and you have all of the d...

Page 93: ...sically PPCBug is contained in two socketed 32 pin PLCC Flash devices that together provide 1MB of storage The executable code is checksummed at every power on or reset firmware entry and the result which includes a precalculated checksum contained in the Flash devices is verified against the expected checksum MPU Hardware and Firmware Initialization The debugger performs the MPU hardware and firm...

Page 94: ...peed of read only memory 16 Enables the MPU s instruction cache 17 Copies the MPU s exception vector table from FFF00000 to 00000000 18 Verifies MPU type 19 Enables the superscalar feature of the MPU superscalar processor boards only 20 Verifies the external bus clock speed of the MPU 21 Determines the debugger s console host ports and initializes the PC16550A 22 Displays the debugger s copyright ...

Page 95: ... boot 35 Executes the debugger monitor i e issues the PPC4 Bug prompt Using PPCBug PPCBug is command driven it performs its various operations in response to commands that you enter at the keyboard When the PPC4 Bug prompt appears on the screen the debugger is ready to accept debugger commands When the PPC4 Diag prompt appears on the screen the debugger is ready to accept diagnostics commands To s...

Page 96: ...ce before the first argument Precede all other arguments with either a space or comma One or more options Precede an option or a string of options with a semicolon If no option is entered the command s default option conditions are used Debugger Commands The individual debugger commands are listed in the following table The commands are described in detail in the PPCBug Firmware Package User s Man...

Page 97: ...CACHE Modify Cache State CM Concurrent Mode NOCM No Concurrent Mode CNFG Configure Board Information Block CS Checksum CSAR PCI Configuration Space READ Access CSAW PCI Configuration Space WRITE Access DC Data Conversion DS One Line Disassembler DU Dump S Records ECHO Echo String ENV Set Environment FORK Fork Idle MPU at Address FORKWR Fork Idle MPU with Registers GD Go Direct Ignore Breakpoints G...

Page 98: ... O Control for Disk IOI I O Inquiry IOP I O Physical Direct Disk Access IOT I O Teach for Configuring Disk Controller IRD Idle MPU Register Display IRM Idle MPU Register Modify IRS Idle MPU Register Set LO Load S Records from Host MA Macro Define Display NOMA Macro Delete MAE Macro Edit MAL Enable Macro Listing NOMAL Disable Macro Listing MAR Load Macros MAW Save Macros MD MDS Memory Display MENU ...

Page 99: ...Teach Configuration NPING Network Ping OF Offset Registers Display Modify PA Printer Attach NOPA Printer Detach PBOOT Bootstrap Operating System PF Port Format NOPF Port Detach PFLASH Program FLASH Memory PS Put RTC into Power Save Mode RB ROMboot Enable NORB ROMboot Disable RD Register Display REMOTE Remote RESET Cold Warm Reset RL Read Loop RM Register Modify RS Register Set RUN MPU Execution St...

Page 100: ...ories by using the SD Switch Directories command You may view a list of the commands in the directory that you are currently in by using the HE Help command SD Switch Directories SET Set Time and Date SROM SROM Examine Modify SYM Symbol Table Attach NOSYM Symbol Table Detach SYMS Symbol Table Display Search T Trace TA Terminal Attach TIME Display Time and Date TM Transparent Mode TT Trace to Tempo...

Page 101: ...diagnostic directory the diagnostic prompt PPC4 Diag displays and all of the debugger and diagnostic commands are available PPCBug s diagnostic test groups are listed in the Table 5 2 Note that not all tests are performed on the MVME240x Using the HE command you can list the diagnostic routines available in each test group Refer to the PPCBug Diagnostics Manual for complete descriptions of the dia...

Page 102: ...Diagnostic Test Groups Test Group Description CL1283 Parallel Interface CL1283 Tests DEC DEC21x43 Ethernet Controller Tests HAWK HAWK Tests ISABRDGE PCI ISA Bridge Tests KBD8730x PC8730x Keyboard Mouse Tests L2CACHE Level 2 Cache Tests NCR NCR 53C8xx SCSI 2 I O Processor Tests PAR8730x Parallel Interface PC8730x Test UART Serial Input Output Tests PCIBUS PCI PMC Generic Tests RAM Local RAM Tests R...

Page 103: ...ameters of the hardware Use the PPCBug command CNFG to change those parameters Use the PPCBug command ENV to change configurable PPCBug parameters in NVRAM The CNFG and ENV commands are both described in the PPCBug Firmware Package User s Manual Refer to that manual for general information about their use and capabilities The following paragraphs present additional information aboutCNFG and ENV th...

Page 104: ...e considered data strings and data strings are right justified The data strings are padded with zeroes if the length is not met The Board Information Block is factory configured before shipment There is no need to modify block parameters unless the NVRAM is corrupted Refer to the MVME2400 Series VME Processor Module Programmer s Reference Guide for the actual location and other information about t...

Page 105: ...de Listed and described below are the parameters that you can configure using ENV The default values shown were those in effect when this publication went to print Configuring the PPCBug Parameters The parameters that can be configured using ENV are Bug or System environment B S B Field Service Menu Enable Y N N B Bug is the mode where no system type of support is displayed However system related ...

Page 106: ...tiprocessor Control Register MPCR in shared RAM to pass and start execution of the cross loaded program B Use both the GCSR and the MPCR methods to pass and start execution of the cross loaded program Default N Do not use any Remote Start Method Y Accesses will be made to the appropriate system buses e g VMEbus local MPU bus to determine the presence of supported controllers Default N Accesses wil...

Page 107: ...ting same boot image from a network interface as from a mass storage device N Do not enable PReP style network booting Default Y Negate the VMEbus SYSFAIL signal during board initialization N Negate the VMEbus SYSFAIL signal after successful completion or entrance into the bug command monitor Default Y Local SCSI bus is reset on debugger setup N Local SCSI bus is not reset on debugger setup Defaul...

Page 108: ...low you the option of stopping the boot by use of the BREAK key The time value is from 0 255 seconds Default 5 seconds Auto Boot Enable Y N N Auto Boot at power up only Y N N Y Give boot priority to devices defined in the fw boot path global environment variable GEV N Do not give boot priority to devices listed in the fw boot path GEV Default Y Give boot priority to devices defined in the fw boot ...

Page 109: ...is to be booted as specified in the PowerPC Reference Platform PRP specification If set to zero the firmware will search the partitions in order 1 2 3 4 until it finds the first bootable partition That is then the partition that will be booted Other acceptable values are 1 2 3 or 4 In these four cases the partition specified will be booted without searching Auto Boot Abort Delay 7 The time in seco...

Page 110: ...of stopping the boot by use of the BREAK key The time value is from 0 255 seconds Default 5 seconds ROM Boot Direct Starting Address FFF00000 The first location tested when PPCBug searches for a ROMboot module Default FFF00000 ROM Boot Direct Ending Address FFFFFFFC The last location tested when PPCBug searches for a ROMboot module Default FFFFFFFC Y The ROMboot function is enabled N The ROMboot f...

Page 111: ...the NETboot sequence will delay before starting the boot The purpose for the delay is to allow you the option of stopping the boot by use of the BREAK key The time value is from 0 255 seconds Default 5 seconds Network Auto Boot Configuration Parameters Offset NVRAM 00001000 The address where the network interface configuration parameters are to be saved retained in NVRAM these parameters are the n...

Page 112: ...ata within NVRAM Memory Size Enable Y N Y Memory Size Starting Address 00000000 The default Starting Address is 00000000 Memory Size Ending Address 02000000 The default Ending Address is the calculated size of local memory If the memory start is changed from 00000000 this value will also need to be adjusted DRAM Speed in NANO Seconds 60 The default setting for this parameter will vary depending on...

Page 113: ...allowable ROMNAL setting is 0 the highest allowable is F The value to enter depends on processor speed refer to Chapter 1 or Appendix B for appropriate values The default value varies according to the system s bus clock speed Note ROM Next Access Length is not applicable to the MVME2400 The configured value is ignored by PPCBug DRAM Parity Enable On Detection Always Never O A N O Note This paramet...

Page 114: ...played will indicate how far the initialization sequence had progressed before stalling The codes are enabled by an ENV parameter Serial Startup Code Master Enable Y N N A line feed can be inserted after each code is displayed to prevent it from being overwritten by the next code This is also enabled by an ENV parameter Serial Startup Code LF Enable Y N N The list of LED serial codes is included i...

Page 115: ...rse chip PCI Slave Image 1 Control C0820000 The configured value is written into the LSI1_CTL register of the Universe chip PCI Slave Image 1 Base Address Register 01000000 The configured value is written into the LSI1_BS register of the Universe chip PCI Slave Image 1 Bound Address Register 20000000 The configured value is written into the LSI1_BD register of the Universe chip PCI Slave Image 1 T...

Page 116: ... configured value is written into the LSI3_BD register of the Universe chip PCI Slave Image 3 Translation Offset D0000000 The configured value is written into the LSI3_TO register of the Universe chip VMEbus Slave Image 0 Control E0F20000 The configured value is written into the VSI0_CTL register of the Universe chip VMEbus Slave Image 0 Base Address Register 00000000 The configured value is writt...

Page 117: ...VSI2_CTL register of the Universe chip VMEbus Slave Image 2 Base Address Register 00000000 The configured value is written into the VSI2_BS register of the Universe chip VMEbus Slave Image 2 Bound Address Register 00000000 The configured value is written into the VSI2_BD register of the Universe chip VMEbus Slave Image 2 Translation Offset 00000000 The configured value is written into the VSI2_TO ...

Page 118: ...SC register of the Universe chip Special PCI Slave Image Register 00000000 The configured value is written into the SLSI register of the Universe chip Master Control Register 80C00000 The configured value is written into the MAST_CTL register of the Universe chip Miscellaneous Control Register 52060000 The configured value is written into the MISC_CTL register of the Universe chip User AM Codes 00...

Page 119: ...ision level of the document such as xx2 the second revision of a manual a supplement bears the same number as the manual but has a suffix such as xx2A1 the first supplement to the second revision of the manual Table A 1 Motorola Computer Group Documents Document Title Publication Number MVME2400 Series VME Processor Module Installation and Use this manual V2400A IH MVME2400 Series VME Processor Mo...

Page 120: ...ment Title and Source Publication Number PowerPC 750TM RISC Microprocessor Technical Summary Literature Distribution Center for Motorola Telephone 1 800 441 2447 FAX 602 994 6430 or 303 675 2150 E mail ldcformotorola hibbertco com MPC750 D PowerPC 750TM RISC Microprocessor User s Manual Literature Distribution Center for Motorola Telephone 1 800 441 2447 FAX 602 994 6430 or 303 675 2150 E mail ldc...

Page 121: ... 01 TL16C550C UART Texas Instruments Liteerature Center P O Box 17228 Denver CO 80217 2228 URL www ti com sc docs pics home htm TL16C550C 82378 System I O SIO PCI to ISA Bridge Controller Intel Corporation Literature Sales P O Box 7641 Mt Prospect Illinois 60056 7641 Telephone 1 800 548 4725 290473 003 DECchip 21143 PCI Fast Ethernet LAN Controller Hardware Reference Manual Digital Equipment Corpo...

Page 122: ...M SRAM Data Sheet SGS Thomson Microelectronics Group Marketing Headquarters or nearest Sales Office 1000 East Bell Road Phoenix Arizona 85022 Telephone 602 867 6100 M48T59 Universe User Manual Tundra Semiconductor coproration 603 March Road Kanata ON K2K 2M5 Canada Telephone 1 800 267 7231 OR 695 High Glen Drive San Jose California 95133 USA Telephone 408 258 3600 FAX 408 258 3659 Universe Part Nu...

Page 123: ...4 Scottsdale Arizona 85260 3415 Telephone 602 951 8866 FAX 602 951 0720 ANSI VITA 1 1994 NOTE An earlier version of this specification is available as Versatile Backplane Bus VMEbus Institute of Electrical and Electronics Engineers Inc Publication and Sales Department 345 East 47th Street New York New York 10017 21633 Telephone 1 800 678 4333 ANSI IEEE Standard 1014 1987 OR Microprocessor system b...

Page 124: ... 14070 Portland Oregon 97214 4070 Marketing Help Line Telephone 503 696 6111 Document Specification Ordering Telephone 1 800 433 5177or 503 797 4207 FAX 503 234 6762 PCI Local Bus Specification PowerPC Reference Platform PRP Specification Third Edition Version 1 0 Volumes I and II International Business Machines Corporation Power Personal Systems Architecture 11400 Burnet Rd Austin TX 78758 3493 D...

Page 125: ...732 FAX 716 871 6511 OR IBM 1580 Route 52 Bldg 504 Hopewell Junction NY 12533 7531 Telephone 1 800 PowerPC OR Morgan Kaufmann PUblishers Inc 340 Pine street Sixth Floor San Francisco CA 94104 3205 USA Telephone 413 392 2665 FAX 415 982 2665I Interface Between Data Terminal Equipment and Data Circuit Terminating Equipment Employing Serial Binary Data Interchange EIA 232 D Electronic Industries Asso...

Page 126: ...Related Specifications A 8 Computer Group Literature Center Web Site A ...

Page 127: ...estimated 5 2 60ns EDO to 8 7 50ns EDO 16KB 16KB I D on chip cache MPC750 350 MHz SPECint95 10 8 50ns EDO 32KB 32KB I D on chip cache Memory SDRAM 32MB 64MB or 128MB ECC protected Flash 1MB via two 32 pin PLCC sockets 8MB via surface mount TOD clock device M48T559 8KB NVRAM Timers One watchdog timer time out generates reset Four real time 16 bit programmable timers Power requirements with no PMCs ...

Page 128: ... 0 mm x 149 0 mm Basic double wide 149 0 mm x 149 0 mm PMC I O Front panel and or VMEbus P2 I O PCI expansion connector Address Data A32 D32 D46 114 pin connector PCI bus clock 33 MHz Signalling 5V Peripheral Computer Interface PCI PCI bridge PCIbus 32 64 bit 33MHz VMEbus ANSI VITA 1 1994 VME64 previously IEEE STD 1014 DTB master A16 A32 D08 D64 BLT DTB slave A24 A32 D08 D64 BLT UAT Arbiter Round ...

Page 129: ...nsity system configuration An assembly of three axial fans rated at 100 CFM per fan is placed directly under the VME card cage The incoming air temperature is measured between the fan assembly and the card cage where the incoming airstream first encounters the module under test Test software is executed as the module is subjected to ambient temperature variations Case temperatures of critical high...

Page 130: ...t Compliance was achieved under the following conditions Shielded cables on all external I O ports Cable shields connected to chassis ground via metal shell connectors bonded to a conductive module front panel Conductive chassis rails connected to chassis ground This provides the path for connecting shields to chassis ground Front panel screws properly tightened All peripherals were EMC compliant ...

Page 131: ...nect signals consult the support information documentation for the MVME240x contact your Motorola sales office Connector Location Table VMEbus connector P1 C 1 VMEbus connector P2 I O P2 C 2 Debug serial port RJ45 DEBUG J2 C 3 Ethernet port RJ45 10 100 BASET J3 C 4 CPU debug connector J1 C 5 PCI expansion connector J6 C 6 PMC connectors Slot 1 32 bit PCI J11 J12 C 7 64 bit PCI extension and P2 I O...

Page 132: ...11 Not Used 4 5 Not Used VD4 VBGOUT0 VD12 Not Used 5 6 GND VD5 VBGIN1 VD13 Not Used 6 7 Not Used VD6 VBGOUT1 VD14 Not Used 7 8 GND VD7 VBGIN2 VD15 Not Used 8 9 Not Used GND VBGOUT2 GND VMEGAP 9 10 GND VSYSCLK VBGIN3 VSYSFAIL VMEGA0 10 11 Not Used GND VBGOUT3 VBERR VMEGA1 11 12 GND VDS1 VBR0 VSYSRESET Not Used 12 13 Not Used VDS0 VBR1 VLWORD VMEGA2 13 14 GND VWRITE VBR2 VAM5 Not Used 14 15 Not Used...

Page 133: ...5 VA12 Not Used 26 27 Not Used VA4 VIRQ4 VA11 Not Used 27 28 GND VA3 VIRQ3 VA10 Not Used 28 29 Not Used VA2 VIRQ2 VA9 Not Used 29 30 GND VA1 VIRQ1 VA8 Not Used 30 31 Not Used 12V 5VSTDBY 12V GND 31 32 GND 5V 5V 5V Not Used 32 Table C 1 P1 VMEbus Connector Pin Assignments Continued ...

Page 134: ...1 PMC1_14 J14 14 VA27 PMC1_13 J14 13 PMC2_10 J24 10 7 8 GND PMC1_16 J14 16 VA28 PMC1_15 J14 15 PMC2_12 J24 12 8 9 PMC2_14 J24 14 PMC1_18 J14 18 VA29 PMC1_17 J14 17 PMC2_13 J24 13 9 10 GND PMC1_20 J14 20 VA30 PMC1_19 J14 19 PMC2_15 J24 15 10 11 PMC2_17 J24 17 PMC1_22 J14 22 VA31 PMC1_21 J14 21 PMC2_16 J24 16 11 12 GND PMC1_24 J14 24 GND PMC1_23 J14 23 PMC2_18 J24 18 12 13 PMC2_20 J24 20 PMC1_26 J14...

Page 135: ...ND PMC1_52 J14 52 VD27 PMC1_51 J14 51 PMC2_39 J24 39 26 27 PMC2_41 J24 41 PMC1_54 J14 54 VD28 PMC1_53 J14 53 PMC2_40 J24 40 27 28 GND PMC1_56 J14 56 VD29 PMC1_55 J14 55 PMC2_42 J24 42 28 29 PMC2_44 J24 44 PMC1_58 J14 58 VD30 PMC1_57 J14 57 PMC2_43 J24 43 29 30 GND PMC1_60 J14 60 VD31 PMC1_59 J14 59 PMC2_45 J24 45 30 31 PMC2_46 J24 46 PMC1_62 J14 62 GND PMC1_61 J14 61 GND 31 32 GND PMC1_64 J14 64 5...

Page 136: ...gnments for this connector are as follows Ethernet Connector 10BASET J3 The 10BaseT 100BaseTx connector is an RJ45 connector located on the front plate of the MVME240x The pin assignments for this connector are as follows Table C 3 DEBUG J2 Connector Pin Assignments 1 DCD 2 RTS 3 GND 4 TXD 5 RXD 6 GND 7 CTS 8 DTR Table C 4 10 100 BASET J3 Connector Pin Assignments 1 TD 2 TD 3 RD 4 No Connect 5 No ...

Page 137: ... miscellaneous signals The pin assignments for this connector are as follows Table C 5 Debug Connector Pin Assignments 1 PA0 GND PA1 2 3 PA2 PA3 4 5 PA4 PA5 6 7 PA6 PA7 8 9 PA8 PA9 10 11 PA10 PA11 12 13 PA12 PA13 14 15 PA14 PA15 16 17 PA16 PA17 18 19 PA18 PA19 20 21 PA20 PA21 22 23 PA22 PA23 24 25 PA24 PA25 26 27 PA26 PA27 28 29 PA28 PA29 30 31 PA30 PA31 32 33 PAPAR0 PAPAR1 34 35 PAPAR2 PAPAR3 36 ...

Page 138: ... 44 45 PD6 PD7 46 47 PD8 PD9 48 49 PD10 PD11 50 51 PD12 PD13 52 53 PD14 PD15 54 55 PD16 PD17 56 57 PD18 PD19 58 59 PA20 PD21 60 61 PD22 PD23 62 63 PD24 PD25 64 65 PD26 PD27 66 67 PD28 PD29 68 69 PD30 PD31 70 71 PD32 PD33 72 73 PD34 PD35 74 75 PD36 PD37 76 Table C 5 Debug Connector Pin Assignments Continued ...

Page 139: ...44 PD45 84 85 PD46 PD47 86 87 PD48 PD49 88 89 PA50 PD51 90 91 PD52 PD53 92 93 PD54 PD55 94 95 PD56 PD57 96 97 PD58 PD59 98 99 PD60 PD61 100 101 PD62 PD63 102 103 PDPAR0 PDPAR1 104 105 PDPAR2 PDPAR3 106 107 PDPAR4 PDPAR5 108 109 PDPAR6 PDPAR7 110 111 112 113 DPE DBDIS 114 Table C 5 Debug Connector Pin Assignments Continued ...

Page 140: ...TSIZ2 120 121 TT3 TC0 122 123 TT4 TC1 124 125 CI TC2 126 127 WT CSE0 128 129 GLOBAL CSE1 130 131 SHARED DBWO 132 133 AACK TS 134 135 ARTY XATS 136 137 DRTY TBST 138 139 TA 140 141 TEA 142 143 DBG 144 145 DBB 146 147 ABB 148 149 TCLK_OUT CPUGNT0 150 151 CPUREQ0 152 Table C 5 Debug Connector Pin Assignments Continued ...

Page 141: ... CKSTPI 160 161 L2BR CKSTPO 162 163 L2BG HALTED 164 165 L2CLAIM TLBISYNC 166 167 TBEN 168 169 SUSPEND 170 171 DRVMOD0 172 173 DRVMOD1 174 175 NAPRUN 176 177 SRESET1 QREQ 178 179 SRESET0 QACK 180 181 HRESET TDO 182 183 GND TDI 184 185 CPUCLK TCK 186 187 CPUCLK TMS 188 189 CPUCLK TRST 190 Table C 5 Debug Connector Pin Assignments Continued ...

Page 142: ...signments for this connector are as follows Table C 6 J6 PCI Expansion Connector Pin Assignments 1 3 3V GND 3 3V 2 3 PCICLK PMCINTA 4 5 GND PMCINTB 6 7 PURST PMCINTC 8 9 HRESET PMCINTD 10 11 TDO TDI 12 13 TMS TCK 14 15 TRST PCIXP 16 17 PCIXGNT PCIXREQ 18 19 12V 12V 20 21 PERR SERR 22 23 LOCK SDONE 24 25 DEVSEL SBO 26 27 GND GND 28 29 TRDY IRDY 30 31 STOP FRAME 32 33 GND GND 34 35 ACK64 Reserved 36...

Page 143: ...BE2 44 45 AD1 AD0 46 47 AD3 AD2 48 49 AD5 AD4 50 51 AD7 AD6 52 53 AD9 AD8 54 55 AD11 AD10 56 57 AD13 AD12 58 59 AD15 AD14 60 61 AD17 AD16 62 63 AD19 AD18 64 65 AD21 AD20 66 67 AD23 AD22 68 69 AD25 AD24 70 71 AD27 AD26 72 73 AD29 AD28 74 75 AD31 AD30 76 Table C 6 J6 PCI Expansion Connector Pin Assignments Continued ...

Page 144: ...AD33 AD32 84 85 AD35 AD34 86 87 AD37 AD36 88 89 AD39 AD38 90 91 AD41 AD40 92 93 AD43 AD42 94 95 AD45 AD44 96 97 AD47 AD46 98 99 AD49 AD48 100 101 AD51 AD50 102 103 AD53 AD52 104 105 AD55 AD54 106 107 AD57 AD56 108 109 AD59 AD58 110 111 AD61 AD60 112 113 AD63 AD62 114 Table C 6 J6 PCI Expansion Connector Pin Assignments Continued ...

Page 145: ... TDI GND 6 7 PMCPRSNT1 5V 8 7 GND Not Used 8 9 INTD Not Used 10 9 Not Used Not Used 10 11 GND Not Used 12 11 Pull up 3 3V 12 13 CLK GND 14 13 RST Pull down 14 15 GND PMCGNT1 16 15 3 3V Pull down 16 17 PMCREQ1 5V 18 17 Not Used GND 18 19 5V Vio AD31 20 19 AD30 AD29 20 21 AD28 AD27 22 21 GND AD26 22 23 AD25 GND 24 23 AD24 3 3V 24 25 GND C BE3 26 25 IDSEL1 AD23 26 27 AD22 AD21 28 27 3 3V AD20 28 29 A...

Page 146: ... PMC1_5 P2 C3 PMC1_6 P2 A3 6 7 C BE4 GND 8 7 PMC1_7 P2 C4 PMC1_8 P2 A4 8 9 5V Vio PAR64 10 9 PMC1 _9 P2 C5 PMC1_10 P2 A5 10 11 AD63 AD62 12 11 PMC1_11 P2 C6 PMC1_12 P2 A6 12 13 AD61 GND 14 13 PMC1_13 P2 C7 PMC1_14 P2 A7 14 15 GND AD60 16 15 PMC1_15 P2 C8 PMC1_16 P2 A8 16 17 AD59 AD58 18 17 PMC1_17 P2 C9 PMC1_18 P2 A9 18 19 AD57 GND 20 19 PMC1_19 P2 C10 PMC1_20 P2 A10 20 21 5V Vio AD56 22 21 PMC1_2...

Page 147: ... AD40 46 45 PMC1_45 P2 C23 PMC1_46 P2 A23 46 47 AD39 AD38 48 47 PMC1_47 P2 C24 PMC1_48 P2 A24 48 49 AD37 GND 50 49 PMC1_49 P2 C25 PMC1_50 P2 A25 50 51 GND AD36 52 51 PMC1_51 P2 C26 PMC1_52 P2 A26 52 53 AD35 AD34 54 53 PMC1_53 P2 C27 PMC1_54 P2 A27 54 55 AD33 GND 56 55 PMC1_55 P2 C28 PMC1_56 P2 A28 56 57 5V Vio AD32 58 57 PMC1_57 P2 C29 PMC1_58 P2 A29 58 59 Reserved Reserved 60 59 PMC1_59 P2 C30 PM...

Page 148: ... 6 5 TDI GND 6 7 PMCPRSNT2 5V 8 7 GND Not Used 8 9 INTD Not Used 10 9 Not Used Not Used 10 11 GND Not Used 12 11 Pull up 3 3V 12 13 CLK GND 14 13 RST Pull down 14 15 GND PMCGNT2 16 15 3 3V Pull down 16 17 PMCREQ2 5V 18 17 Not Used GND 18 19 5V Vio AD31 20 19 AD30 AD29 20 21 AD28 AD27 22 21 GND AD26 22 23 AD25 GND 24 23 AD24 3 3V 24 25 GND C BE3 26 25 IDSEL2 AD23 26 27 AD22 AD21 28 27 3 3V AD20 28 ...

Page 149: ... P2 D3 4 5 C BE6 C BE5 6 5 PMC2_5 P2 Z3 PMC2_6 P2 D4 6 7 C BE4 GND 8 7 PMC2_7 P2 D5 PMC2_8 P2 Z5 8 9 5V Vio PAR64 10 9 PMC2_9 P2 D6 PMC2_10 P2 D7 10 11 AD63 AD62 12 11 PMC2_11 P2 Z7 PMC2_12 P2 D8 12 13 AD61 GND 14 13 PMC2_13 P2 D9 PMC2_14 P2 Z9 14 15 GND AD60 16 15 PMC2_15 P2 D10 PMC2_16 P2 D11 16 17 AD59 AD58 18 17 PMC2_17 P2 Z11 PMC2_18 P2 D12 18 19 AD57 GND 20 19 PMC2_19 P2 D13 PMC2_20 P2 Z13 2...

Page 150: ...7 PMC2_42 P2 D28 42 43 AD41 GND 44 43 PMC2_43 P2 D29 PMC2_44 P2 Z29 44 45 GND AD40 46 45 PMC2_45 P2 D30 PMC2_46 P2 Z31 46 47 AD39 AD38 48 47 Not Used Not Used 48 49 AD37 GND 50 49 Not Used Not Used 50 51 GND AD36 52 51 Not Used Not Used 52 53 AD35 AD34 54 53 Not Used Not Used 54 55 AD33 GND 56 55 Not Used Not Used 56 57 5V Vio AD32 58 57 Not Used Not Used 58 59 Reserved Reserved 60 59 Not Used Not...

Page 151: ...terminal A If the CPU LED is not lit the board may not be getting correct power 1 Make sure the system is plugged in 2 Check that the board is securely installed in its backplane or chassis 3 Check that all necessary cables are connected to the board per this manual 4 Check for compliance with Installation Considerations per this manual 5 Review the Installation and Startup procedures per this man...

Page 152: ...er debugger devices are installedl 3 Reconnect power 4 Restart the system by double button reset press the RST and ABT switches at the same time release RST first wait seven seconds then release ABT 5 If the debug prompt appears go to step IV or step V as indicated If the debug prompt does not appear go to step VI B The board may need to be reset IV Debug prompt PPC1 Bug appears at powerup but the...

Page 153: ...e clock speed and or Ethernet Address and then later return to env CR and step 3 7 Run the selftests by typing in st CR The tests take as much as 10 minutes depending on RAM size They are complete when the prompt returns The onboard selftest is a valuable tool in isolating defects 8 The system may indicate that it has passed all the selftests Or it may indicate a test that failed If neither happen...

Page 154: ...annot be corrected using the steps given A There may be some fault in the board hardware or the on board debugging and diagnostic firmware 1 Document the problem and return the board for service 2 Phone 1 800 222 5640 TROUBLESHOOTING PROCEDURE COMPLETE Table D 1 Troubleshooting MVME240x Modules Continued Condition Possible Problem Try This ...

Page 155: ...wires capable of carrying data at 10 Mbps for a maximum distance of 185 meters Also known as twisted pair Ethernet 100Base TX An Ethernet implementation in which the physical medium is an unshielded twisted pair UTP of wires capable of carrying data at 100 Mbps for a maximum distance of 100 meters Also known as fast Ethernet ACIA Asynchronous Communications Interface Adapter AIX Advanced Interacti...

Page 156: ...y particular alignment BLT BLock Transfer board The term more commonly used to refer to a PCB printed circuit board Basically a flat board made of nonconducting material such as plastic or fiberglass on which chips and other electronic components are mounted Also referred to as a circuit board or card bpi bits per inch bps bits per second bus The pathway used to communicate between the CPU memory ...

Page 157: ...e Reference Platform CHRP A specification published by Apple IBM and Motorola which defines the devices interfaces and data formats that make up a CHRP compliant system using a PowerPC processor Composite Video Signal CVS CVBS Signal that carries video picture information for color brightness and synchronizing signals for both horizontal and vertical scans Sometimes referred to as Baseband Video c...

Page 158: ... IBM An architectural system using a 32 bit bus that allows data to be transferred between peripherals in 32 bit chunks instead of 16 bit or 8 bit that most systems use With the transfer of larger bits of information the machine is able to perform much faster than the standard ISA bus system EPP Enhanced Parallel Port EPROM Erasable Programmable Read Only Memory A memory storage device that can be...

Page 159: ...rovide hardware assist for graphics drawing algorithms by performing logical functions on data written to display memory HAL Hardware Abstraction Layer The lower level hardware interface module of the Windows NT operating system It contains platform specific functionality hardware A computing system is normally spoken of as having two major components hardware and software Hardware is the term use...

Page 160: ...cturers for color decoding ISA bus Industry Standard Architecture bus The de facto standard system bus for IBM compatible computers until the introduction of VESA and PCI Used in the reference platform specification IBM ISASIO ISA Super Input Output device ISDN Integrated Services Digital Network A standard for digitally transmitting video audio and electronic data over public phone networks LAN L...

Page 161: ...ng substantially different results The specification is based on a large number of samplings in one place running continuously and the rate at which failure occurs MTBF is not representative of how long a device or any individual device is likely to last nor is it a warranty but rather a gauge of the relative reliability of a family of products multisession The ability to record additional informa...

Page 162: ...nternational Association bus A standard external interconnect bus which allows peripherals adhering to the standard to be plugged in and used without further system modification PCR PCI Configuration Register PDS Processor Direct Slot PHB PCI Host Bridge physical address A binary address that refers to the actual location of information stored in secondary storage PIB PCI to ISA Bridge pixel An ac...

Page 163: ...64 entry buffer and an 8KB instruction and data cache It provides a selectable 32 bit or 64 bit data bus and a separate 32 bit address bus PowerPC 603 is used by Motorola Inc under license from IBM PowerPC 604 The third implementation of the PowerPC family of microprocessors currently under development PowerPC 604 is used by Motorola Inc under license from IBM PowerPC Reference Platform PRP A spec...

Page 164: ...dio Frequency Interference RGB The three separate color signals Red Green and Blue Used with color displays an interface that uses these three color signals as opposed to an interface used with a monochrome display that requires only a single signal Both digital and analog RGB interfaces exist RISC See Reduced Instruction Set Computer RISC ROM Read Only Memory RTC Real Time Clock SBC Single Board ...

Page 165: ... group of programs languages operating procedures and documentation of a computer system Software is the real interface between the user and the computer SRAM Static Random Access Memory SSBLT Source Synchronous BLock Transfer standard s A set of detailed technical guidelines used as a means of establishing uniformity in an area of hardware or software development SVGA Super Video Graphics Array I...

Page 166: ...address issued by a CPU that indirectly refers to the location of information in primary memory such as main memory When data is copied from disk to main memory the physical address is changed to the virtual address VL bus See VESA Local bus VL bus VMEchip2 MCG second generation VMEbus interface ASIC Motorola VME2PCI MCG ASIC that interfaces between the PCI bus and the VMEchip2 device volatile mem...

Page 167: ...phics Array An improved IBM VGA monitor standard that provides at least 256 simultaneous colors and a screen resolution of 1024 x 768 pixels Y Signal Luminance This determines the brightness of each spot pixel on a CRT screen either color or B W systems but not the color ...

Page 168: ...Glossary GL 14 Computer Group Literature Center Web Site G L O S S A R Y ...

Page 169: ...VMEbus 1 2 battery 3 28 baud rate 1 12 2 5 BFL LED 2 4 BFL LED DS1 2 4 BG and IACK signals 1 22 bits per character 1 12 2 5 block diagram MVME240x 3 4 board information block 6 2 board layout MVME240x 1 9 board placement 1 22 board structure 6 2 bridge as Hawk function 3 7 bug basics 5 1 buses standard 3 4 4 1 C cables I O ports B 4 chassis VMEsystem 1 4 CNFG 6 2 commands PPCBug 5 5 commands debug...

Page 170: ...SIC 4 10 function of Universe ASIC 4 11 PCI domain 4 10 processor memory domain 4 10 VMEbus domain 4 11 ENV Auto Boot Abort Delay 6 8 Auto Boot Controller 6 8 Auto Boot Default String 6 8 Auto Boot Device 6 8 Auto Boot Partition Number 6 8 L2 Cache Parity Enable 6 12 Memory Size 6 11 Negate VMEbus SYSFAIL Always 6 5 Network Auto Boot Controller 6 10 NVRAM Bootlist 6 6 Primary SCSI Bus Negotiations...

Page 171: ...23 installing multiple MVME240x boards 1 23 MVME240x into chassis 1 21 MVME240x 1 21 MVME240x hardware 1 13 PCI mezzanine cards 1 13 PMCs 1 13 PMCspan 1 16 1 18 primary PMCspan 1 16 secondary PMCspan 1 18 interconnect signals C 1 interface Ethernet 3 22 PCI bus 3 23 VMEbus 3 25 interrupt architecture MVME240x 4 7 Interrupt Controller MPIC 3 28 interrupt support 4 6 interval timers 3 28 ISA Bus 3 4...

Page 172: ...ler 6 10 Network Auto Boot enable 6 9 NIOT debugger command using 6 10 Non Volatile RAM NVRAM 6 1 6 3 NVRAM BBRAM configuration area 3 22 NVRAM Bootlist 6 6 O operating parameters 6 1 operation parameter Auto Boot Abort Delay 6 8 parameter Auto Boot Controller 6 8 parameter Auto Boot Default String 6 8 parameter Auto Boot Device 6 8 parameter Auto Boot Partition Number 6 8 parameter L2 Cache Parit...

Page 173: ...PMC slot 1 2 7 PMC1 connector pin assignments J11 and J12 C 15 PMC1 connector pin assignments J13 and J14 C 16 PMC1 LED DS4 2 4 PMC2 LED 2 4 PMC2 PMC slot 2 use 2 7 PMC2 connector pin assignments J21 and J22 C 18 PMC2 connector pin assignments J23 and J24 C 19 PMC2 LED DS3 2 4 PMCs installing 1 13 preparing 1 12 PMCspan 1 12 2 8 preparing 1 12 PMCspan Expansion Mezzanine 1 3 PMCspan 002 Installati...

Page 174: ...ocks 3 14 latency 3 15 memory sizes 3 14 SDRAM memory 3 14 secondary PMCspan installing 1 18 Secondary SCSI identifier 6 5 serial port MVME240x 2 5 set environment to bug operating system ENV 6 3 setup terminal 1 22 SGS Thomson MK48T559 timekeeper de vice 4 8 shielded cables B 4 size of base board B 2 SNAPHAT battery as part of Real Time Clock 3 27 software readable jumpers 1 11 sources of reset 4...

Page 175: ...g the hardware 1 7 uppercase 5 12 using the front panels 2 1 V vibration operating B 2 VME Processor Module board layout 1 9 VME Processor Module MVME240x 1 2 VMEbus 3 4 B 2 address data configurations 1 23 backplane 1 2 connectors C 2 memory map 4 3 memory maps 4 3 system controller selection header J9 1 10 Universe ASIC 3 25 VMEbus interface 6 13 VMEbus system controller selection J9 1 8 VMEsyst...

Page 176: ...Index IN 8 Computer Group Literature Center Web Site I N D E X ...

Page 177: ...puter Installation and Use MVME2400 Series Single Board Computer Installation and Use 34 pages 1 8 spine 36 84 pages 3 16 1 4 spine 86 100 pages 5 16 spine 102 180 pages 3 8 1 2 spine 182 308 pages 5 8 1 1 8 spine 2 lines allowed Cover ...

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