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Motorola MVME172, Programmer'S Reference Manual

The Motorola MVME172 Programmer's Reference Manual is a comprehensive manual providing detailed instructions and information for programming this high-performance device. Available for free download from our website, it offers programmers easy access to essential information to maximize the potential of the MVME172.

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MCECC

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When (SC1, SC0) do not indicate that snooping is inhibited, the MCECC 
pair responds differently to DRAM accesses, based on whether the cycle 
is a read or a write, and on the snoop wait (SWAIT) control bit. 

For a read with SWAIT = 0, the MCECC pair immediately starts a read 
cycle to the DRAM and latches the data from the DRAMs. It waits, 
however, for MI* to be negated before it enables the data (that has been 
latched) onto the local bus and asserts TA* or TEA*. If TA* or TEA* is 
asserted by another local bus slave before MI* is negated, then the 
MCECC pair assumes that the cycle is over and that the DRAM is not to 
participate in that cycle. 

For a read with SWAIT = 1, the MCECC pair behaves the same as with 
SWAIT = 0 except that it does not start the DRAM read cycle until it sees 
the MI* signal negated. Note that this means that if another local bus slave 
asserts TA* or TEA* before MI* is negated, then the MCECC pair never 
starts the DRAM read cycle. 

For a write cycle, the MCECC pair always waits for MI* to be negated 
before it begins a write cycle to the DRAM. If another local bus slave 
asserts TA* or TEA* before MI* is negated, then the MCECC pair never 
starts the DRAM write cycle. 

ECC

The MCECC pair performs single bit error correction and double bit error 
detection (SECDED). The 32 bit wide local data bus is divided into lower 
(D00-D15) and upper (D16-D31) halves. Each half is routed through an 
MCECC, which multiplexes it with half of the 128 bit wide DRAM. This 
allows each MCECC to connect to 64 bits of the DRAM. Each MCECC 
additionally connects to 8 bits of check bit DRAM. This actually makes the 
DRAM array 144 bits wide (128 bits of normal data and 16 bits of check 
data). 

Cycle Types

To support ECC, the MCECC pair always deals with DRAM using full 
width (144 bits, 72 bits for each MCECC) accesses. When the local bus 
master requests any size read of DRAM, the MCECC pair reads 144 bits. 
When the local bus master requests a line write to DRAM, the MCECC 

Summary of Contents for MVME172

Page 1: ...MVME172 VME Embedded Controller Programmer s Reference Guide VME172A PG2 Edition of February 1999 ...

Page 2: ...rior written permission of Motorola Inc It is possible that this publication may contain reference to or information about Motorola products machines and programs programming or services that are not announced in your country Such references or information must not be construed to mean that Motorola intends to announce such Motorola products programming or services in your country Restricted Right...

Page 3: ...sed which precedes data and address parameters by a character identifying the numeric format as follows For example 12 is the decimal number twelve and 12 is the decimal number eighteen Unless otherwise specified all address references are in hexadecimal An asterisk following the signal name for signals which arelevel significant denotes that the signal is true or valid when the signal is low An a...

Page 4: ...indicate that a bit is in the state that enables the function it controls The term false is used to indicate that the bit is in the state that disables the function it controls In all tables the terms 0 and 1 are used to describe the actual value that should be written to the bit or the value that it yields when read The term status bit is used to describe a bit in a register that reflects a speci...

Page 5: ...This equipment generates uses and can radiate electro magnetic energy It may cause or be susceptible to electro magnetic interference EMI if not installed and used in a cabinet with adequate EMI protection Motorola and the Motorola symbol are registered trademarks of Motorola Inc All other products mentioned in this document are trademarks or registered trademarks of their respective holders Copyr...

Page 6: ...Place holder ...

Page 7: ...us Memory Map 1 46 VMEbus Accesses to the Local Bus 1 47 VMEbus Short I O Memory Map 1 47 Software Support Considerations 1 47 Interrupts 1 47 Cache Coherency 1 48 Sources of Local BERR 1 48 Local Bus Time out 1 48 VMEbus Access Time out 1 49 VMEbus BERR 1 49 Local DRAM Parity Error 1 49 VMEchip2 1 49 Bus Error Processing 1 49 Description of Error Conditions on the MVME172 1 50 MPU Parity Error 1 ...

Page 8: ...us to VMEbus DMA Controller 2 10 No Address Increment DMA Transfers 2 12 DMAC VMEbus Requester 2 13 Tick and Watchdog Timers 2 14 Prescaler 2 14 Tick Timers 2 15 Watchdog Timer 2 15 VMEbus Interrupter 2 16 VMEbus System Controller 2 17 Arbiter 2 17 IACK Daisy Chain Driver 2 17 Bus Timer 2 17 Reset Driver 2 18 Local Bus Interrupter and Interrupt Handler 2 18 Global Control and Status Registers 2 20...

Page 9: ...Ebus Master Starting Address Register 4 2 42 Local Bus Slave VMEbus Master Address Translation Address Register 4 2 42 Local Bus Slave VMEbus Master Address Translation Select Register 4 2 42 Local Bus Slave VMEbus Master Attribute Register 4 2 43 Local Bus Slave VMEbus Master Attribute Register 3 2 44 Local Bus Slave VMEbus Master Attribute Register 2 2 45 Local Bus Slave VMEbus Master Attribute ...

Page 10: ...terrupter Status Register bits 8 15 2 80 Local Bus Interrupter Status Register bits 0 7 2 81 Local Bus Interrupter Enable Register bits 24 31 2 82 Local Bus Interrupter Enable Register bits 16 23 2 83 Local Bus Interrupter Enable Register bits 8 15 2 84 Local Bus Interrupter Enable Register bits 0 7 2 85 Software Interrupt Set Register bits 8 15 2 86 Interrupt Clear Register bits 24 31 2 86 Interr...

Page 11: ...trol Register 2 107 General Purpose Register 0 2 108 General Purpose Register 1 2 108 General Purpose Register 2 2 109 General Purpose Register 3 2 109 General Purpose Register 4 2 110 General Purpose Register 5 2 110 CHAPTER 3 MC2 Chip Introduction 3 1 Summary of Major Features 3 1 Functional Description 3 2 MC2 Chip Initialization 3 2 Flash and PROM Interface 3 2 BBRAM Interface 3 3 82596CA LAN ...

Page 12: ... Space Base Address Register 3 25 SRAM Space Base Address Register 3 26 DRAM Space Size Register 3 26 DRAM SRAM Options Register 3 27 SRAM Space Size Register 3 29 LANC Error Status Register 3 30 82596CA LANC Interrupt Control Register 3 31 LANC Bus Error Interrupt Control Register 3 32 SCSI Error Status Register 3 33 General Purpose Inputs Register 3 33 MVME172 Version Register 3 35 SCSI Interrup...

Page 13: ...a or Double Size IP_ab Memory Base Address Registers 4 20 IP_b Memory Base Address Registers 4 20 IP_c or Double Size IP_cd Memory Base Address Registers 4 21 IP_d Memory Base Address Registers 4 21 IP_a IP_b IP_c IP_d Memory Size Registers 4 21 IP_a IP_b IP_c and IP_d IRQ0 and IRQ1 Interrupt Control Registers 4 23 IP_a IP_b IP_c and IP_d General Control Registers 4 24 IP Clock Register 4 28 DMA A...

Page 14: ...urst Read 5 6 Cycle Type Burst Write 5 6 Single Bit Error Cycle Type Non Burst Write 5 6 Double Bit Error Cycle Type Non Burst Write 5 6 Triple or Greater Bit Error Cycle Type Non Burst Write 5 6 Single Bit Error Cycle Type Scrub 5 6 Double Bit Error Cycle Type Scrub 5 7 Triple or Greater Bit Error Cycle Type Scrub 5 7 Error Logging 5 7 Scrub 5 7 Refresh 5 8 Arbitration 5 8 Chip Defaults 5 8 Progr...

Page 15: ...ess Counter Bits 23 16 5 30 Scrub Address Counter Bits 15 8 5 30 Scrub Address Counter Bits 7 4 5 31 Error Logger Register 5 31 Error Address Bits 31 24 5 32 Error Address Bits 23 16 5 33 Error Address Bits 15 8 5 33 Error Address Bits 7 4 5 33 Error Syndrome Register 5 34 Defaults Register 1 5 34 Defaults Register 2 5 36 Initialization 5 37 Syndrome Decode 5 39 APPENDIX A Related Documentation Mo...

Page 16: ...Memory Map 1 35 Table 1 12 Z85230 SCC Register Addresses 1 37 Table 1 13 82596CA Ethernet LAN Memory Map 1 38 Table 1 14 53C710 SCSI Memory Map 1 39 Table 1 15 MK48T58 BBRAM TOD Clock Memory Map 1 40 Table 1 16 BBRAM Configuration Area Memory Map 1 41 Table 1 17 TOD Clock Memory Map 1 42 Table 2 1 VMEchip2 Memory Map LCSR Summary Sheet 1 of 2 2 22 Table 2 2 DMAC Command Table Format 2 53 Table 2 3...

Page 17: ...C Specifications 5 3 Table 5 2 MCECC Internal Register Memory Map Part 1 5 10 Table 5 3 MCECC Internal Register Memory Map Part 2 5 12 Table A 1 Motorola Computer Group Documents A 1 Table A 2 Manufacturers Documents A 2 ...

Page 18: ...xviii ...

Page 19: ...as cache coherency interrupts and bus errors All programmable registers in the MVME172 that reside in ASICs are covered in the chapters on those ASICs Chapter 2 covers the VMEchip2 Chapter 3 covers the MC2 chip and Chapter 4 covers the IP2 chip Chapter 5 covers the MCECC chip used only on 200 300 Series MVME172 Appendix A describes using interrupts For those interested in programmable register bit...

Page 20: ...MVME172 installation and use manual furnished with your 400 500 Series MVME172 for more information The VMEbus interface is provided by an ASIC called the VMEchip2 The VMEchip2 includes two tick timers a watchdog timer programmable map decoders for the master and slave interfaces and a VMEbus to from local bus DMA controller a VMEbus to from local bus non DMA programmed access interface a VMEbus i...

Page 21: ...PROMs may be shipped separately Flash One Intel 28F016SA 2M x 8 Flash memory device 2MB Flash memory total with write protection optional NVRAM and TOD 8K by 8 Non Volatile RAM NVRAM and Time of Day TOD clock with battery backup Timers Four 32 bit Tick Timers and Watchdog Timer in the MC2 Chip ASIC for periodic interrupts Two 32 bit Tick Timers and Watchdog Timer in the VMEchip2 ASIC for periodic ...

Page 22: ...special ordered without the VMEbus interface VMEbus system controller functions VMEbus interface to local bus A24 A32 D8 D16 D32 D8 D16 D32 D64 BLT BLT Block Transfer Local bus to VMEbus interface A16 A24 A32 D8 D16 D32 VMEbus interrupter VMEbus interrupt handler Global CSR for interprocessor communications DMA for fast local memory VMEbus transfers A16 A24 A32 D16 D32 D16 D32 D64 BLT Switches Two...

Page 23: ...d Also the bus grant daisy chain and the interrupt acknowledge daisy chain have zero ohm bypass resistors installed To support this feature certain logic in the VMEchip2 has been duplicated in the MC2 chip Table 1 2 on page 1 8 defines the location of the redundant logic This logic is inhibited in the MC2 chip if the VMEchip2 is present The enables for these functions are controlled by software an...

Page 24: ...rollers Flash 2MB MC2 chip 128KB SRAM Memory Array w Battery M48T58 Battery Backed 8KB RAM Clock 4 8 16 32 64MB Memory Array 4 8 16MB Parity DRAM Memory Array MC68LC060 MPU VMEbus A32 24 D64 32 16 08 Master Slave IndustryPack I O 2 Channels Optional Ethernet Transceiver DB 15 Front Panel Connector SCSI Peripherals 68 pin Front Panel SCSI Connector Optional Optional 4 Serial Ports RJ 45 Front Panel...

Page 25: ...y Array w Battery M48T58 Battery Backed 8KB RAM Clock 4 8 16MB Parity DRAM Memory Array MC68LC060 MPU VMEbus A32 24 D64 32 16 08 Master Slave IndustryPack I O 4 Channels Optional Ethernet Transceiver connections are Via P2 and Transition Modules Optional Optional EIA 232 Transceivers 2038 9706 Optional MC68060 A32 D32 Configuration Dependent 2 Serial Ports DB 25 Front Panel or Via P2 and Transitio...

Page 26: ...7 The SRAM and PROM decoder in the VMEchip2 version 2 must be disabled by software before any accesses are made to these address spaces 8 32 bit prescaler The prescaler can also be accessed at FFF40064 when the optional VMEbus is not enabled Table 1 2 Redundant Functions in the VMEchip2 and MC2 Chip VMEchip2 MC2 Chip Notes Address Bit Address Bit FFF40060 28 24 FFF42044 28 24 1 5 FFF40060 22 19 17...

Page 27: ...ewed by local bus masters local bus memory map and 2 the mapping of onboard resources as viewed by VMEbus masters VMEbus memory map The memory and I O maps which are described in the following tables are correct for all local bus masters There is some address translation capability in the VMEchip2 This allows multiple MVME172 modules on the same VMEbus with different virtual local bus maps as view...

Page 28: ...ries MVME172 Table 1 3 200 300 Series MVME172 Local Bus Memory Map Address Range Devices Accessed Port Width Size Software Cache Inhibit Notes Programmable DRAM on parity mezzanine D32 4MB 16MB N 2 Programmable DRAM on ECC mezzanine D32 4MB 64MB N 2 Programmable Onboard SRAM D32 128KB N 2 Programmable VMEbus A32 A24 D32 D16 4 Programmable IP_a memory D32 D8 64KB 8MB 2 4 Programmable IP_b memory D3...

Page 29: ...on tables in your MVME172 installation manual for further details 2 This area is user programmable The DRAM and SRAM decoder is programmed in the MC2 chip the local to VMEbus decoders are programmed in the VMEchip2 and the IP memory space is programmed in the IP2 3 Size is approximate 4 Cache inhibit depends on the devices in the area mapped 5 The EPROM and Flash are dynamically sized by the MC2 c...

Page 30: ...che Inhibit Note s Programmable DRAM on board D32 4MB 16 MB N 2 Programmable SRAM D32 128KB 2MB N 2 Programmable VMEbus A32 A24 D32 D16 4 Programmable IP_a Memory D32 D8 64KB 8MB 2 4 Programmable IP_b Memory D32 D8 64KB 8MB 2 4 Programmable IP_c Memory D32 D8 64KB 8MB 2 4 Programmable IP_d Memory D32 D8 64KB 8MB 2 4 FF800000 FF9FFFFF Flash PROM D32 2MB N 1 5 FFA00000 FFBFFFFF PROM Flash D32 2MB N ...

Page 31: ...ce size is less than the allocated memory map size for some entries the device contents repeat for those entries If jumper GPI3 is installed the Flash device is accessed If GPI3 is not installed the PROM is accessed 6 The Flash and PROM are sized by the MC2 chip ASIC from an 8 bit private bus to the 32 bit MPU local bus Because the device size is less than the allocated memory map size for some en...

Page 32: ... D8 256B 1 3 FFF40200 FFF40FFF Reserved 3 5KB 4 5 FFF41000 FFF41FFF Reserved 4KB 4 FFF42000 FFF42FFF MC2 chip D32 D8 4KB 1 FFF43000 FFF430FF MCECC 1 D8 256B 1 8 FFF43100 FFF431FF MCECC 2 D8 256B 1 8 FFF43200 FFF43FFF MCECCs repeated 3 5KB 1 5 8 FFF44000 FFF44FFF Reserved 8KB 4 FFF45000 FFF45800 SCC 1 Z85230 D8 2KB 1 2 FFF45801 FFF45FFF SCC 2 Z85230 D8 2KB 1 2 FFF46000 FFF46FFF LAN 82596CA D32 4KB ...

Page 33: ...6B 7 FFF58800 FFF5887F Reserved 128B 1 FFF58880 FFF588FF Reserved 128B 1 FFF58900 FFF5897F Reserved 128B 1 FFF58980 FFF589FF Reserved 128B 1 FFF58A00 FFF58A7F Reserved 128B 1 FFF58A80 FFF58AFF Reserved 128B 1 FFF58B00 FFF58B7F Reserved 128B 1 FFF58B80 FFF58BFF Reserved 128B 1 FFF58C00 FFF58CFF Reserved 256B 1 FFF58D00 FFF58DFF Reserved 256B 1 FFF58E00 FFF58EFF Reserved 256B 1 FFF58F00 FFF58FFF Res...

Page 34: ...FFFBC800 FFFBC81F Reserved 2KB 1 FFFBD000 FFFBFFFF Reserved 12KB 4 FFFC0000 FFFCFFFF M48T58 BBRAM TOD Clock D32 D8 64KB 1 9 FFFD0000 FFFEFFFF Reserved 128K B 4 Table 1 5 200 300 Series MVME172 Local I O Devices Memory Map Continued Address Range Devices Accessed Port Width Size Notes ...

Page 35: ...s to the GCSR may be 8 16 or 32 bits Reads to the LCSR and GCSR may be 8 16 or 32 bits Byte reads should be used to read the interrupt vector 4 This area does not return an acknowledge signal If the local bus timer is enabled the access times out and is terminated by a TEA signal 5 Size is approximate 6 Port commands to the 82596CA must be written as two 16 bit writes upper word first and lower wo...

Page 36: ...F SCSI 53C710 D32 D8 4KB 1 FFF48000 FFF57FFF Reserved 64KB 4 FFF58000 FFF5807F IP2 chip IP_a I O D16 128B 1 FFF58080 FFF580FF IP2 chip IP_a ID D16 128B 1 FFF58100 FFF5817F IP2 chip IP_b I O D16 128B 1 FFF58180 FFF581FF IP2 chip IP_b ID Read D16 128B 1 FFF58200 FFF5827F IP2 chip IP_c I O D16 128B 1 FFF58280 FFF582FF IP2 chip IP_c ID D16 128B 1 FFF58300 FFF5837F IP2 chip IP_d I O D16 128B 1 FFF58380...

Page 37: ... 256B 1 FFF58E00 FFF58EFF Reserved 256B 1 FFF58F00 FFF58FFF Reserved 256B 1 FFFBC000 FFFBC01F IP2 chip registers D32 D8 2KB 1 FFFBC800 FFFBC81F Reserved 2KB 1 FFFBD000 FFFBFFFF Reserved 12KB 4 FFFC0000 FFFC7FFF MK48T58 BBRAM TOD clock D32 D8 32KB 1 FFFC8000 FFFCBFFF MK48T58 D32 D8 16KB 1 7 FFFCC000 FFFCFFFF MK48T58 D32 D8 16KB 1 7 FFFD0000 FFFEFFFF Reserved 128KB 4 Table 1 6 400 500 Series MVME172...

Page 38: ...s an indirect access mode to the data registers which is functional and must be used 3 Writes to the LCSR in the VMEchip2 must be 32 bits LCSR writes of 8 or 16 bits terminate with a TEA signal Writes to the GCSR may be 8 16 or 32 bits Reads to the LCSR and GCSR may be 8 16 or 32 bits Byte reads should be used to read the interrupt vector 4 This area does not return an acknowledge signal If the lo...

Page 39: ...ting your local Motorola sales representative A non disclosure agreement may be required VMEchip2 Table 1 7 MC2 chip Table 1 8 IP2 chip Table 1 9 IP2 chip Control and Status Registers Table 1 10 MCECC chip Table 1 11 Z85230 SCC Register addresses Table 1 12 82596CA Ethernet LAN chip Table 1 13 53C710 SCSI chip Table 1 14 MK48T58 BBRAM TOD clock Table 1 15 BBRAM configuration area Table 1 16 TOD cl...

Page 40: ... ENDING ADDRESS 4 MASTER ADDRESS TRANSLATION ADDRESS 4 VMEchip2 LCSR Base Address FFF40000 OFFSET 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 MAST D16 EN MAST WP EN MAST D16 EN MAST WP EN MASTER AM 3 MASTER AM 4 GCSR GROUP SELECT GCSR BOARD SELECT MAST 4 EN MAST 3 EN MAST 2 EN MAST 1 EN TICK 2 1 TIC...

Page 41: ...RESS TRANSLATION SELECT 1 SLAVE ADDRESS TRANSLATION SELECT 2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 IO2 EN IO2 WP EN IO2 S U IO2 P D IO1 EN IO1 D16 EN IO1 WP EN IO1 S U 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 MASTER AM 2 MASTER AM 1 ROM SIZE ROM BANK B SPEED ROM BANK A SPEED DMA TBL INT DMA LB SNP MODE DMA INC VME DMA INC LB DMA D64 BLK DMA BLK DMA AM 5 DMA AM 4 ...

Page 42: ...R IRQ PE IRQ IRQ1E IRQ TIC2 IRQ TIC1 IRQ VME IACK IRQ DMA IRQ SIG3 IRQ SIG2 IRQ SIG1 IRQ SIG0 IRQ LM1 IRQ LM0 IRQ ABORT IRQ LEVEL SYS FAIL IRQ LEVEL MST WP ERROR IRQ LEVEL VME IACK IRQ LEVEL DMA IRQ LEVEL SIG 3 IRQ LEVEL SIG 2 IRQ LEVEL SW7 IRQ LEVEL SW6 IRQ LEVEL SW5 IRQ LEVEL SW4 IRQ LEVEL SPARE IRQ LEVEL VME IRQ 7 IRQ LEVEL VME IRQ 6 IRQ LEVEL VME IRQ 5 IRQ LEVEL VECTOR BASE REGISTER 0 VECTOR B...

Page 43: ...0 CLR IRQ 15 CLR IRQ 14 CLR IRQ 13 CLR IRQ 12 CLR IRQ 11 CLR IRQ 10 CLR IRQ 9 CLR IRQ 8 SET IRQ 15 SET IRQ 14 SET IRQ 13 SET IRQ 12 SET IRQ 11 SET IRQ 10 SET IRQ 9 SET IRQ 8 SW7 IRQ SW6 IRQ SW5 IRQ SW4 IRQ SW3 IRQ SW2 IRQ SW1 IRQ SW0 IRQ SPARE VME IRQ7 VME IRQ6 VME IRQ5 VME IRQ4 VME IRQ3 VME IRQ2 VME IRQ1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 GPIOO P ERROR IRQ LEVEL IRQ1E IRQ LEVEL TIC TIMER 2 IRQ...

Page 44: ...7 6 5 4 3 2 1 0 0 0 Chip Revision Chip ID 2 4 LM 3 LM 2 LM 1 LM 0 SI G3 SI G2 SI G1 SI G0 RS T ISF BF SCO N SYS FL X X X 4 8 General Purpose Control and Status Register 0 6 C General Purpose Control and Status Register 1 8 10 General Purpose Control and Status Register 2 A 14 General Purpose Control and Status Register 3 C 18 General Purpose Control and Status Register 4 E 1C General Purpose Contr...

Page 45: ... Interrupt Control 1C DRAM Parity Error Interrupt Control SCC Interrupt Control Tick Timer 4 Control Tick Timer 3 Control 20 DRAM Space Base Address Register SRAM Space Base Address Register 24 DRAM Space Size DRAM SRAM Options SRAM Space Size Reserved 28 LANC Error Status Reserved LANC Interrupt Control LANC Bus Error Interrupt Control 2C SCSI Error Status General Purpose Inputs MVME172 Version S...

Page 46: ...ble IP_d Memory Space D16 D8 64KB 8MB FFF58000 FFF5807F IP_a I O Space D16 128B FFF58080 FFF580BF IP_a ID Space D16 64B FFF580C0 FFF580FF IP_a ID Space Repeated D16 64B FFF58100 FFF5817F IP_b I O Space D16 128B FFF58180 FFF581BF IP_b ID Space D16 64B FFF581C0 FFF581FF IP_b ID Space Repeated D16 64B FFF58200 FFF5827F IP_c I O Space D16 128B FFF58280 FFF582BF IP_c ID Space D16 64B FFF582C0 FFF582FF ...

Page 47: ...BASE29 d_BASE28 d_BASE27 d_BASE26 d_BASE25 d_BASE24 0B IP_d MEM BASE LOWER d_BASE23 d_BASE22 d_BASE21 d_BASE20 d_BASE19 d_BASE18 d_BASE17 d_BASE16 0C IP_a MEM SIZE a_SIZE23 a_SIZE22 a_SIZE21 a_SIZE20 a_SIZE19 a_SIZE18 a_SIZE17 a_SIZE16 0D IP_b MEM SIZE b_SIZE23 b_SIZE22 b_SIZE21 b_SIZE20 b_SIZE19 b_SIZE18 b_SIZE17 b_SIZE16 0E IP_c MEM SIZE c_cSIZE23 c_SIZE22 c_SIZE21 c_SIZE20 c_SIZE19 c_SIZE18 c_S...

Page 48: ...1A IP_c GENERAL CONTROL c_ERR 0 c_RT1 c_RT0 c_WIDTH1 c_WIDTH0 c_BTD c_MEN 1B IP_d GENERAL CONTROL d_ERR 0 d_RT1 d_RT0 d_WIDTH1 d_WIDTH0 d_BTD d_MEN 1C RESERVED 0 0 0 0 0 0 0 0 1D IP CLOCK 0 0 0 0 0 0 0 IP32 1E DMA ARBITRATION CONTROL 0 0 0 0 0 ROTAT PRI1 PRI0 1F IP RESET 0 0 0 0 0 0 0 RES Table 1 10 IP2 Chip Memory Map Control and Status Registers Continued Register Offset Register Name Register B...

Page 49: ...LB ADDR LBA7 LBA6 LBA5 LBA4 LBA3 LBA2 LBA1 LBA0 2C DMA_a IP ADDR 0 0 0 0 0 0 0 0 2D DMA_a IP ADDR IPA23 IPA22 IPA21 IPA20 IPA19 IPA18 IPA17 IPA16 2E DMA_a IP ADDR IPA15 IPA14 IPA13 IPA12 IPA11 IPA10 IPA9 IPA8 2F DMA_a IP ADDR IPA7 IPA6 IPA5 IPA4 IPA3 IPA2 IPA1 IPA0 30 DMA_aBYTE CNT 0 0 0 0 0 0 0 0 31 DMA_aBYTE CNT BCNT23 BCNT22 BCNT21 BCNT20 BCNT19 BCNT18 BCNT17 BCNT16 32 DMA_aBYTE CNT BCNT15 BCNT...

Page 50: ...A12 LBA11 LBA10 LBA9 LBA8 43 DMA_b LB ADDR LBA7 LBA6 LBA5 LBA4 LBA3 LBA2 LBA1 LBA0 44 DMA_b IP ADDR 0 0 0 0 0 0 0 0 45 DMA_b IP ADDR IPA23 IPA22 IPA21 IPA20 IPA19 IPA18 IPA17 IPA16 46 DMA_b IP ADDR IPA15 IPA14 IPA13 IPA12 IPA11 IPA10 IPA9 IPA8 47 DMA_b IP ADDR IPA7 IPA6 IPA5 IPA4 IPA3 IPA2 IPA1 IPA0 48 DMA_bBYTE CNT 0 0 0 0 0 0 0 0 49 DMA_bBYTE CNT BCNT23 BCNT22 BCNT21 BCNT20 BCNT19 BCNT18 BCNT17 ...

Page 51: ... LB ADDR LBA7 LBA6 LBA5 LBA4 LBA3 LBA2 LBA1 LBA0 5C DMA_c IP ADDR 0 0 0 0 0 0 0 0 5D DMA_c IP ADDR IPA23 IPA22 IPA21 IPA20 IPA19 IPA18 IPA17 IPA16 5E DMA_c IP ADDR IPA15 IPA14 IPA13 IPA12 IPA11 IPA10 IPA9 IPA8 5F DMA_c IP ADDR IPA7 IPA6 IPA5 IPA4 IPA3 IPA2 IPA1 IPA0 60 DMA_cBYTE CNT 0 0 0 0 0 0 0 0 61 DMA_cBYTE CNT BCNT23 BCNT22 BCNT21 BCNT20 BCNT19 BCNT18 BCNT17 BCNT16 62 DMA_cBYTE CNT BCNT15 BCN...

Page 52: ...ADDR LBA15 LBA14 LBA13 LBA12 LBA11 LBA10 LBA9 LBA8 73 DMA_d LB ADDR LBA7 LBA6 LBA5 LBA4 LBA3 LBA2 LBA1 LBA0 74 DMA_d IP ADDR 0 0 0 0 0 0 0 0 75 DMA_d IP ADDR IPA23 IPA22 IPA21 IPA20 IPA19 IPA18 IPA17 IPA16 76 DMA_d IP ADDR IPA15 IPA14 IPA13 IPA12 IPA11 IPA10 IPA9 IPA8 77 DMA_d IP ADDR IPA7 IPA6 IPA5 IPA4 IPA3 IPA2 IPA1 IPA0 78 DMA_dBYTE CNT 0 0 0 0 0 0 0 0 79 DMA_dBYTE CNT BCNT23 BCNT22 BCNT21 BCN...

Page 53: ...0 0 0 0 0 0 0 0 0 10 DUMMY 1 0 0 0 0 0 0 0 0 14 BASE ADDRESS BAD31 BAD30 BAD29 BAD28 BAD27 BAD26 BAD25 BAD24 18 DRAM CONTRL BAD23 BAD22 RWB5 SWAIT RWB3 NCEIEN NCEBEN RAMEN 1C BCLK FREQ BCK7 BCK6 BCK5 BCK4 BCK3 BCK2 BCK1 BCK0 20 DATA CONTRL 0 0 DERC ZFILL RWCKB 0 0 0 24 SCRUB CNTRL RACODE RADATA HITDIS SCRB SCRBEN 0 SBEIEN IDIS 28 SCRUB PERIOD SBPD15 SBPD14 SBPD13 SBPD12 SBPD11 SBPD10 SBPD9 SBPD8 2...

Page 54: ...C7 SAC6 SAC5 SAC4 0 0 0 0 5C ERROR LOGGER ERRLOG ERD ESCRB ERA EALT 0 MBE SBE 60 ERROR ADDRESS EA31 EA30 EA29 EA28 EA27 EA26 EA25 EA24 64 ERROR ADDRESS EA23 EA22 EA21 EA20 EA19 EA18 EA17 EA16 68 ERROR ADDRESS EA15 EA14 EA13 EA12 EA11 EA10 EA9 EA8 6C ERROR ADDRESS EA7 EA6 EA5 EA4 0 0 0 0 70 ERROR SYNDROME S7 S6 S5 S4 S3 S2 S1 S0 74 DEFAULTS1 WRHDIS STATCOL FSTRD SELI1 SELI0 RSIZ2 RSIZ1 RSIZ0 78 DEF...

Page 55: ...wing two macros are examples dev_addr is a pointer to the base address of the SCC SCCR0 is the offset to the SCC control register 0 define READ_SCC VAR_NAME dev_addr SCCR0 0x08 VAR_NAME dev_addr SCCR0 define WRITE_SCC VAR_NAME dev_addr SCCR0 0x08 dev_addr SCCR0 VAR_NAME Table 1 12 Z85230 SCC Register Addresses SCC Z85230 SCC Register Address SCC 1 All MVME172 modules Port B Control FFF45001 Port B...

Page 56: ...tem Configuration Pointer to the command registers prior to writing to the MPU Channel Attention register Writes to the System Configuration Pointer must be upper word first lower word second Table 1 13 82596CA Ethernet LAN Memory Map 82596CA Ethernet LAN Directly Accessible Registers Address Data Bits D31 D16 D15 D0 FFF46000 Upper Command Word Lower Command Word FFF46004 MPU Channel Attention CA ...

Page 57: ...gister Address Map SCRIPTs Mode and Little Endian Mode 00 SIEN SDID SCNTL1 SCNTL0 00 04 SOCL SODL SXFER SCID 04 08 SBCL SBDL SIDL SFBR 08 0C SSTAT2 SSTAT1 SSTAT0 DSTAT 0C 10 DSA 10 14 CTEST3 CTEST2 CTEST1 CTEST0 14 18 CTEST7 CTEST6 CTEST5 CTEST4 18 1C TEMP 1C 20 LCRC CTEST8 ISTAT DFIFO 20 24 DCMD DBC 24 28 DNAD 28 2C DSP 2C 30 DSPS 30 34 SCRATCH 34 38 DCNTL DWT DIEN DMODE 38 3C ADDER 3C ...

Page 58: ...d by Motorola networking software The third area may be used by an operating system The fourth area is used by the MVME172 board debugger MVME172Bug The fifth area detailed in Table 1 16 is the configuration area The sixth area the TOD clock detailed in Table 1 17 is defined by the chip hardware Table 1 15 MK48T58 BBRAM TOD Clock Memory Map Address Range Description Size Bytes FFFC0000 FFFC0FFF Us...

Page 59: ...Serial Number 8 FFFC1F46 FFFC1F4D Static Mezz PWB 8 FFFC1F4E FFFC1F4D Static Mezz Serial 8 FFFC1F56 FFFC1F5D ECC1 Mezz PWB 8 FFFC1F5E FFFC1F5D ECC1 Mezz Serial 8 FFFC1F66 FFFC1F65 ECC2 Mezz PWB 8 FFFC1F6E FFFC1F75 ECC2 Mezz Serial 8 FFFC1F76 FFFC1F7D Ser Port 2 Pers PWB 8 FFFC1F7E FFFC1F85 Ser Port 2 Pers Serial No 8 FFFC1F86 FFFC1F8D IP_a Board ID 8 FFFC1F8E FFFC1F95 IP_a Board Serial Number 8 FF...

Page 60: ...Serial Number 8 4FFFC1FDE FFFC1FE5 IP_d Board PWB 8 FFFC1FE6 FFFC1FF6 Reserved 65 FFFC1FF7 Checksum 1 Table 1 17 TOD Clock Memory Map Address Data Bits Function D7 D6 D5 D4 D3 D2 D1 D0 FFFC1FF8 W R S Calibration Control FFFC1FF9 ST Seconds 00 FFFC1FFA x Minutes 00 FFFC1FFB x x Hour 00 FFFC1FFC x FT x x x Day 01 FFFC1FFD x x Date 01 FFFC1FFE x x x Month 01 FFFC1FFF Year 00 Table 1 16 BBRAM Configur...

Page 61: ...c1mem_serial 8 char ecc2mem_pwb 8 char ecc2mem_srial 8 char port2_pwb 8 char port2_serial 8 char ipa_brdid 8 char ipa_serial 8 char ipa_pwb 8 char ipb_brdid 8 char ipb_serial 8 char ipb_pwb 8 char ipc_brdid 8 char ipc_serial 8 char ipc_pwb 8 char ipd_brdid 8 char ipd_serial 8 char ipd_pwb 8 char reserved 17 char cksum 1 The fields are defined as follows 1 Four bytes are reserved for the revision o...

Page 62: ...efix This is for the main logic board if more than one board is required for a set Additional boards in a set are defined by a structure for that set For example for an MVME172 board with MC68060 SCSI Ethernet 4MB DRAM and 512KB SRAM at revision A the PWA field contains 01 W318xB01A The 12 characters are followed by four blanks 5 Four bytes contain the speed of the board in MHz The first two bytes...

Page 63: ...entifier in ascii ECC2 Memory Mezzanine serial number in ascii 12 Eight bytes are reserved for the serial number assigned to the serial port 2 personality board in ASCII format 13 Eight bytes are reserved for the board identifier in ASCII assigned to the optional first IndustryPack a 14 Eight bytes are reserved for the serial number in ASCII assigned to the optional first IndustryPack a 15 Eight b...

Page 64: ...ck d 25 Growth space 65 bytes is reserved This pads the structure to an even 256 bytes 26 The final one byte of the area is reserved for a checksum as defined in the Debugging Package for Motorola 68K CISC CPUs User s Manual for security and data integrity of the configuration area of the NVRAM This data is stored in hexadecimal format Interrupt Acknowledge Map The local bus distinguishes interrup...

Page 65: ...cycles There are also many sources of bus error First let us consider how interrupts are handled Interrupts The MC68060 uses hardware vectored interrupts Most interrupt sources are level and base vector programmable Interrupt vectors from the MC2 chip and the VMEchip2 have two sections a base value which can be set by the processor usually the upper four bits and the lower bits which are set accor...

Page 66: ...e software must also mark all onboard and off board I O areas as cache inhibited and serialized Sources of Local BERR A TEA signal indicating a bus error is returned to the local bus master when a local bus time out occurs a DRAM parity error occurs and parity checking is enabled or a VME bus error occurs during a VMEbus access Note The 400 500 Series MVME172 models do not contain parity DRAM The ...

Page 67: ...rect configuration information causes the VMEchip2 to incorrectly access a device on the VMEbus such as driving LWORD low to a 16 bit board a hardware error occurs on the VMEbus or a VMEbus slave reports an access error such as parity error Local DRAM Parity Error Note The 400 500 Series MVME172 models do not contain parity DRAM When parity checking is enabled the current bus master receives a bus...

Page 68: ... This section list the various error conditions that are reported by the MVME172 hardware A subsection heading identifies each type of error condition A standard format gives a description of the error indicates how notification of the error condition is made indicates which status register s have information about the error and concludes with some comments pertaining to each particular error MPU ...

Page 69: ...E172 VMEbus access time out The latter is the time from when the VMEbus has been requested to when it is granted MPU TEA Cause Unidentified Description An error occurred while the MPU was attempting an access MPU Notification TEA is asserted during an MPU access Status Bit 10 of the MPU Status and DMA Interrupt Count Register at address FFF40048 in the VMEchip2 Comments No status was given as to t...

Page 70: ...cription The DMAC experienced a VMEbus error during an attempted transfer MPU Notification DMAC interrupt when enabled Status The VME bit is set in the DMAC Status Register address FFF40048 bit 1 Comments This indicates the DMAC attempted to access a VMEbus address at which there was no resource or the VMEbus slave returned a BERR signal DMAC Parity Error Note The 400 500 Series MVME172 models do ...

Page 71: ... The DLOB bit is set in the DMAC Status Register address FFF40048 bit 4 Comments This is normally caused by a programming error The local bus address of the DMAC should not be programmed with a local bus address that maps to the VMEbus If the TBL bit is set address FFF40048 bit 2 the error occurred during a command table access otherwise the error occurred during a data access DMAC LTO Error Descr...

Page 72: ...r and additional status was not provided MPU Notification DMAC interrupt when enabled Status The DLBE bit is set in the DMAC Status Register address FFF40048 bit 6 Comments An 8 or 16 bit write to the LCSR in the VMEchip2 causes this error If the TBL bit is set address FFF40048 bit 2 the error occurred during a command table access otherwise the error occurred during a data access LAN Parity Error...

Page 73: ...hip LAN Error Status Register FFF42028 Comments The LANCE has no ability to respond to TEA so the error interrupt and status are provided in the MC2 chip Control for the interrupt is in the MC2 chip LAN Error Interrupt Control Register FFF4202B LAN LTO Error Description Local Bus Time out occurred while the LANCE was local bus master MPU Notification MC2 chip Interrupt LAN ERROR IRQ Status MC2 chi...

Page 74: ...ments 53C710 interrupt enables are controlled in the 53C710 and in the MC2 chip SCSI Interrupt Control Register FFF4202F SCSI Off Board Error Description Error encountered while the 53C710 was attempting to go to the VMEbus MPU Notification 53C710 Interrupt Status 53C710 DMA Status Register 53C710 DMA Interrupt Status Register MC2 chip SCSI Error Status Register FFF4202C Comments 53C710 interrupt ...

Page 75: ...en initiated to when a VMEbus grant has been obtained The global bus timer measures the time from when a VMEbus cycle begins to when it completes Normally these timers should be set to quite different values An example of one MVME172 accessing another MVME172 illustrates the use of these timers When the processor or another local bus master initiates an access to the VMEbus it first waits until an...

Page 76: ...ally this is also set to 256 µsec When the memory has the data available a transfer acknowledge signal TA is given This translates into a DTACK signal on the VMEbus which is then translated into a TA signal to the first requesting processor and the transfer is complete If the VMEbus global timer expires on a legitimate transfer the VMEbus to local bus controller in the VMEchip2 may become confused...

Page 77: ...t guaranteed indivisible and may cause illegal VMEbus cycles Lock cycles caused by MMU table walks do not cause illegal VMEbus cycles and they are not guaranteed indivisible Illegal Access to IP Modules from External VMEbus Masters When a device other than the local MVME172 is operating as VMEbus master access by that device to the local IP modules is subject to restrictions Access to the Industry...

Page 78: ...1 60 Computer Group Literature Center Web Site Board Description and Memory Maps 1 ...

Page 79: ...Features Local Bus to VMEbus Interface Programmable local bus map decoder Programmable short standard and extended VMEbus addressing Programmable AM codes Programmable 16 bit and 32 bit VMEbus data width Software enabled write posting mode Write post buffer one cache line or one four byte Automatically performs dynamic bus sizing for VMEbus cycles Software configured VMEbus access timers Local bus...

Page 80: ...BLT mode only 32 bit Local to VMEbus DMA Controller Programmable 16 bit 32 bit and 64 bit VMEbus data width Programmable short standard and extended VMEbus addressing Programmable AM code Programmable local bus snoop enable A 16 four byte FIFO data buffer Supports up to 4 GB of data per DMA request Automatically adjusts transfer size to optimize bus utilization DMA complete interrupt DMAC command ...

Page 81: ...tration timer IACK daisy chain driver Programmable bus timer SYSRESET logic Global Control Status Register Set Four location monitors Global control of locally detected failures Global control of local reset Four global attention interrupt bits A chip ID and revision register Four 16 bit dual ported general purpose registers Interrupt Handler All interrupts are level programmable All interrupts ar...

Page 82: ... capabilities Addressing capabilities A16 A24 A32 Data transfer capabilities D08 D16 D32 The local bus slave includes six local bus map decoders for accessing the VMEbus The first four map decoders are general purpose programmable decoders while the other two are fixed and are dedicated for I O decoding The first four map decoders compare local bus address lines A31 through A16 with a 16 bit start...

Page 83: ...ONTROL DATA CONTROL ADDRESS CONTROL DATA CONTROL CONTROL DATA CONTROL ADDRESS DATA CONTROL ADDRESS DATA CONTROL ADDRESS DATA CONTROL ADDRESS DATA CONTROL ADDRESS LOCAL BUS LOCAL BUS SLAVE FIFO VMEBUS MASTER VMEBUS DATA DATA DATA DATA DATA DATA CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL CONTROL FIFO ADDRESS CONTROL FIFO GCSR DATA CONTROL ADDRESS DATA CONTROL ADDRESS CONTROL LOCAL BUS T...

Page 84: ...one cache line four four bytes Write posting should only be enabled when bus errors are not expected If a bus error is returned on a write posted cycle the local processor is interrupted if the interrupt is enabled The address of the error is not saved Normal memory never returns a bus error on a write cycle However some VMEbus ECC memory cards perform a read modify write operation and therefore m...

Page 85: ...signal after 64 µs 1 ms or 32 ms The VMEchip2 includes a software controlled VMEbus write post timer and it starts ticking when a data transfer to the VMEbus is write posted The timer stops ticking once the chip has started the data transfer on the VMEbus If this does not happen before the timer times out the chip aborts the write posted cycle and send an interrupt to the local bus interrupter If ...

Page 86: ...ation is complete the DWB pin is negated the DWB bit in the LCSR is negated and the bus is not being held by a lock cycle The requester releases the bus as follows 1 When the chip is configured in the release when done RWD mode the requester releases the bus when the above conditions are satisfied 2 When the chip is configured in the release on request ROR mode the requester releases the bus when ...

Page 87: ...fer by asserting DTACK The chip then requests control of the local bus and independently accesses the local resource after it has been granted the local bus The write posting pipeline is two deep in the non block transfer mode and 16 deep in the block transfer mode To significantly improve the access time of the slave when it responds to a VMEbus block read cycle the VMEchip2 contains a 16 four by...

Page 88: ...nction with the local bus master the VMEbus master and a 16 four byte FIFO buffer The DMA controller has a 32 bit local address counter 32 bit table address counter a 32 bit VMEbus address counter a 32 bit byte counter and control and status registers The Local Control and Status Register LCSR provides software with the ability to control the operational modes of the DMAC Software can program the ...

Page 89: ...ally adjusts the size of individual data transfers until 64 bit transfers D64 BLT mode 32 bit transfers D32 mode or 16 bit transfers D16 mode can be executed Based on the address of the first byte the DMAC transfers single byte double byte or a mixture of both and then continues to execute transfer cycles based on the programmed data width Based on the address of the last byte the DMAC transfers s...

Page 90: ...maintain mastership for a specific amount of time and then after relinquishing it refrain from requesting it for another specific amount of time No Address Increment DMA Transfers During normal memory to memory DMA transfers the DMA controller is programmed to increment the local bus and VMEbus address This allows a block of data to be transferred between VMEbus memory and local bus memory In some...

Page 91: ...efine the transfer size and byte lanes During D16 transfers the VMEbus address line VA 1 toggles If the VMEbus port size is D64 then VA 2 1 LWORD and DS 1 0 are used to define the transfer size and byte lanes Local bus address LA 3 0 and SIZ 1 0 are used to define the transfer size and byte lanes on local bus During local bus transfers LA 3 2 count The DMA controller internally increments the VMEb...

Page 92: ...tion process the DMAC requester executes an early release of the bus If it is about to release the bus and it is executing a VMEbus cycle the requester releases BBSY before its associated VMEbus master completes the cycle This allows the arbiter to arbitrate any pending requests and grant the bus to the next requester at the same time that the DMAC completes its cycle Tick and Watchdog Timers The ...

Page 93: ...tick timer interrupt is enabled by the local bus interrupter The overflow counter can be cleared by writing a one to the overflow clear bit Tick timer one or two can be programmed to generate a pulse on the VMEbus IRQ1 interrupt line at the tick timer period This provides a broadcast interrupt function which allows several VME boards to receive an interrupt at the same time In certain applications...

Page 94: ...ed environment The VMEbus interrupter has an additional feature not defined in the VMEbus specification The VMEchip2 supports a broadcast mode on the IRQ1 signal line When this feature is used the normal IRQ1 interrupt to the local bus interrupter should be disabled and the edge sensitive IRQ1 interrupt to the local bus interrupter should be enabled All boards in the system which are not participa...

Page 95: ...on timer preventing a bus lockup when no requester assumes control of the bus after the arbiter has issued a grant Using a control bit this timer can be enabled or disabled When enabled it assumes control of the bus by driving the BBSY signal after 256 µsecs releasing it after satisfying the requirements of the VMEbus specification and then re arbitrating any pending bus requests IACK Daisy Chain ...

Page 96: ...o initiate a local reset operation The local reset driver is enabled even when the chip is not the system controller A local reset may be generated by the RESET switch a power up reset a watch dog time out a VMEbus SYSRESET or a control bit in the GCSR Local Bus Interrupter and Interrupt Handler There are 31 interrupt sources in the VMEchip2 VMEbus ACFAIL ABORT switch VMEbus SYSFAIL write post bus...

Page 97: ... sensitive interrupters connected to the output of the tick timers The DMAC interrupter is an edge sensitive interrupter connected to the DMAC The GCSR SIG3 0 interrupters are edge sensitive interrupters connected to the output of the signal bits in the GCSR The location monitor interrupters are edge sensitive interrupters connected to the location monitor bits in the GCSR The software 7 0 interru...

Page 98: ...for the Local Control and Status Registers LCSR in the VMEchip2 The local bus map decoder for the LCSR is included in the VMEchip2 The base address of the LCSR is FFF40000 and the registers are 32 bits wide Byte two byte and four byte read operations are permitted however byte and two byte write operations are not permitted Byte and two byte write operations return a TEA signal to the local bus Re...

Page 99: ...bit is a read only status bit R W This bit is readable and writable W AC This bit can be set and it is automatically cleared This bit can also be read C Writing a one to this bit clears this bit or another bit This bit reads zero S Writing a one to this bit sets this bit or another bit This bit reads zero P The bit is affected by powerup reset S The bit is affected by SYSRESET L The bit is affecte...

Page 100: ...G ADDRESS 4 MASTER ADDRESS TRANSLATION ADDRESS 4 VMEchip2 LCSR Base Address FFF40000 OFFSET 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 MAST D16 EN MAST WP EN MAST D16 EN MAST WP EN MASTER AM 3 MASTER AM 4 GCSR GROUP SELECT GCSR BOARD SELECT MAST 4 EN MAST 3 EN MAST 2 EN MAST 1 EN TICK 2 1 TICK IRQ ...

Page 101: ...LAVE ADDRESS TRANSLATION SELECT 2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 IO2 EN IO2 WP EN IO2 S U IO2 P D IO1 EN IO1 D16 EN IO1 WP EN IO1 S U 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 MASTER AM 2 MASTER AM 1 ROM SIZE ROM BANK B SPEED ROM BANK A SPEED DMA TBL INT DMA LB SNP MODE DMA INC VME DMA INC LB DMA D64 BLK DMA BLK DMA AM 5 DMA AM 4 DMA WRT DMA D16 DMA AM 3 DM...

Page 102: ...PE IRQ IRQ1E IRQ TIC2 IRQ TIC1 IRQ VME IACK IRQ DMA IRQ SIG3 IRQ SIG2 IRQ SIG1 IRQ SIG0 IRQ LM1 IRQ LM0 IRQ ABORT IRQ LEVEL SYS FAIL IRQ LEVEL MST WP ERROR IRQ LEVEL VME IACK IRQ LEVEL DMA IRQ LEVEL SIG 3 IRQ LEVEL SIG 2 IRQ LEVEL SW7 IRQ LEVEL SW6 IRQ LEVEL SW5 IRQ LEVEL SW4 IRQ LEVEL SPARE IRQ LEVEL VME IRQ 7 IRQ LEVEL VME IRQ 6 IRQ LEVEL VME IRQ 5 IRQ LEVEL VECTOR BASE REGISTER 0 VECTOR BASE RE...

Page 103: ... IRQ 0 CLR IRQ 15 CLR IRQ 14 CLR IRQ 13 CLR IRQ 12 CLR IRQ 11 CLR IRQ 10 CLR IRQ 9 CLR IRQ 8 SET IRQ 15 SET IRQ 14 SET IRQ 13 SET IRQ 12 SET IRQ 11 SET IRQ 10 SET IRQ 9 SET IRQ 8 SW7 IRQ SW6 IRQ SW5 IRQ SW4 IRQ SW3 IRQ SW2 IRQ SW1 IRQ SW0 IRQ SPARE VME IRQ7 VME IRQ6 VME IRQ5 VME IRQ4 VME IRQ3 VME IRQ2 VME IRQ1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 GPIOO P ERROR IRQ LEVEL IRQ1E IRQ LEVEL TIC TIMER ...

Page 104: ...odifier select register and attribute register The addresses and bit definitions of these registers are shown in the following tables The VMEbus slave map decoders described in this section are disabled by local reset SYSRESET or power up reset Caution must be used when enabling the map decoders or when modifying their registers after they are enabled The safest time to enable or modify the map de...

Page 105: ...anslation is not desired then the address translation registers should be programmed to zero The address translation address register and the address translation select register operate in the following way If a bit in the address translation select register is set then the corresponding local bus address line is driven from the corresponding bit in the address translation address register If the ...

Page 106: ... attribute register The snoop bits in the attribute register are driven on to the local bus when the VMEbus to local bus interface is local bus master VMEbus Slave Ending Address Register 1 This register is the ending address register for the first VMEbus to local bus map decoder VMEbus Slave Starting Address Register 1 This register is the starting address register for the first VMEbus to local b...

Page 107: ...nslation Address Offset Register 1 This register is the address translation address register for the first VMEbus to local bus map decoder It should be programmed to the local bus starting address When the adder is engaged this register is the offset value ADR SIZ FFF40004 16 bits of 32 BIT 31 16 NAME Ending Address Register 2 OPER R W RESET 0 PS ADR SIZ FFF40004 16 bits of 32 BIT 15 0 NAME Starti...

Page 108: ... between the VMEbus starting and ending addresses If the segment size is between the sizes shown in the table below assume the larger size ADR SIZ FFF40008 16 bits of 32 BIT 15 0 NAME Address Translation Select Register 1 OPER R W RESET 0 PS Segment Size Address Translation Select Value Segment Size Address Translation Select Value 64KB FFFF 32MB FE00 128KB FFFE 64MB FC00 256KB FFFC 128MB F800 512...

Page 109: ...he address translation select register value is based on the segment size the difference between the VMEbus starting and ending addresses If the segment size is between the sizes shown in the table below assume the larger size ADR SIZ FFF4000C 16 bits of 32 BIT 31 16 NAME Address Translation Address Offset Register 2 OPER R W RESET 0 PS ADR SIZ FFF4000C 16 bits of 32 BIT 15 0 NAME Address Translat...

Page 110: ... is low write posting is disabled for the address range defined by the second VMEbus slave map decoder SNP2 These bits control the snoop enable lines to the local bus for the address range defined by the second VMEbus slave map decoder The snooping functions are 0 Snoop enabled 1 Snoop inhibited ADDER2 When this bit is high the adder is used for address translation When this bit is low the adder i...

Page 111: ...ccess cycles When this bit is low the second map decoder does not respond to VMEbus program access cycles BLK When this bit is high the second map decoder responds to VMEbus block access cycles When this bit is low the second map decoder does not respond to VMEbus block access cycles D64 When this bit is high the second map decoder responds to VMEbus D64 block access cycles When this bit is low th...

Page 112: ...d to VMEbus A32 access cycles USR When this bit is high the second map decoder responds to VMEbus user non privileged access cycles When this bit is low the second map decoder does not responded to VMEbus user access cycles SUP When this bit is high the second map decoder responds to VMEbus supervisory access cycles When this bit is low the second map decoder does not respond to VMEbus supervisory...

Page 113: ...bit is low write posting is disabled for the address range defined by the first VMEbus slave map decoder SNP1 These bits control the snoop enable lines to the local bus for the address range defined by the first VMEbus slave map decoder The snooping functions are 0 Snoop enabled 1 Snoop inhibited ADDER1 When this bit is high the adder is used for address translation When this bit is low the adder ...

Page 114: ...ogram access cycles When this bit is low the first map decoder does not respond to VMEbus program access cycles BLK When this bit is high the first map decoder responds to VMEbus block access cycles When this bit is low the first map decoder does not respond to VMEbus block access cycles D64 When this bit is high the first map decoder responds to VMEbus D64 block access cycles When this bit is low...

Page 115: ...base address registers The local bus to VMEbus interface allows onboard local bus masters access to off board VMEbus resources The address of the VMEbus resources as viewed from the local bus is controlled by the local bus slave map decoders which are part of the local bus to VMEbus interface Four of the six local bus to VMEbus map decoders are programmable while the two I O map decoders are fixed...

Page 116: ...port write posting while others do not The VMEbus area in question may be mapped to two local bus addresses one with write posting enabled and one with write posting disabled The address translation registers allow local bus address bits A31 through A16 to be modified The address translation register should be programmed with the translated address and the address translation select register shoul...

Page 117: ...er provides support for the other I O map of the VMEbus This decoder maps the local bus address range F0000000 to F0FFFFFF to the A24 map of the VMEbus and the address range F1000000 to FF7FFFFF to the A32 map of the VMEbus The transfer size is always D16 This segment may be enabled using the enable bit Write posting may be enabled using the write post enable bit The local bus map decoders should ...

Page 118: ... address register for the second local bus to VMEbus map decoder Local Bus Slave VMEbus Master Starting Address Register 2 This register is the starting address register for the second local bus to VMEbus map decoder ADR SIZ FFF40014 16 bits of 32 BIT 15 0 NAME Starting Address Register 1 OPER R W RESET 0 PS ADR SIZ FFF40018 16 bits of 32 BIT 31 16 NAME Ending Address Register 2 OPER R W RESET 0 P...

Page 119: ...rting address register for the third local bus to VMEbus map decoder Local Bus Slave VMEbus Master Ending Address Register 4 This register is the ending address register for the fourth local bus to VMEbus map decoder ADR SIZ FFF4001C 16 bits of 32 BIT 31 16 NAME Ending Address Register 3 OPER R W RESET 0 PS ADR SIZ FFF4001C 16 bits of 32 BIT 15 0 NAME Starting Address Register 3 OPER R W RESET 0 P...

Page 120: ...ister for the fourth local bus to VMEbus bus map decoder Local Bus Slave VMEbus Master Address Translation Select Register 4 This register is the address translation select register for the fourth local bus to VMEbus bus map decoder ADR SIZ FFF40020 16 bits of 32 BIT 15 0 NAME Starting Address Register 4 OPER R W RESET 0 PS ADR SIZ FFF40024 16 bits of 32 BIT 31 16 NAME Address Translation Address ...

Page 121: ... not support block transfers the block transfer address modifier codes should not be used WP When this bit is high write posting is enabled to the segment defined by map decoder 4 When this bit is low write posting is disabled to the segment defined by map decoder 4 D16 When this bit is high D16 data transfers are performed to the segment defined by map decoder 4 When this bit is low D32 data tran...

Page 122: ...t support block transfers the block transfer address modifier codes should not be used WP When this bit is high write posting is enabled to the segment defined by map decoder 3 When this bit is low write posting is disabled to the segment defined by map decoder 3 D16 When this bit is high D16 data transfers are performed to the segment defined by map decoder 3 When this bit is low D32 data transfe...

Page 123: ... not support block transfers the block transfer address modifier codes should not be used WP When this bit is high write posting is enabled to the segment defined by map decoder 2 When this bit is low write posting is disabled to the segment defined by map decoder 2 D16 When this bit is high D16 data transfers are performed to the segment defined by map decoder 2 When this bit is low D32 data tran...

Page 124: ...s not support block transfers the block transfer address modifier codes should not be used WP When this bit is high write posting is enabled to the segment defined by map decoder 1 When this bit is low write posting is disabled to the segment defined by map decoder 1 D16 When this bit is high D16 data transfers are performed to the segment defined by map decoder 1 When this bit is low D32 data tra...

Page 125: ...the group address and the board address Once enabled the GCSR register should not be reprogrammed unless the VMEchip2 is VMEbus master GCSR Group These bits define the group portion of the GCSR address These bits are compared with VMEbus address lines A8 through A15 The recommended group address for the MVME172 is D2 ADR SIZ FFF4002C 8 bits of 32 BIT 31 24 NAME GCSR Group Address Register 4 OPER R...

Page 126: ... the GCSR board address register disables the map decoder The map decoder is enabled when the board address is not F GCSR Board These bits define the board number portion of the GCSR address These bits are compared with VMEbus address lines A4 through A7 The GCSR is enabled by values 0 through E The address XXFY in the VMEbus A16 space is reserved for the location monitors LM0 through LM3 Note XX ...

Page 127: ...n this bit is high the second local bus to VMEbus map decoder is enabled When this bit is low the second local bus to VMEbus map decoder is disabled EN3 When this bit is high the third local bus to VMEbus map decoder is enabled When this bit is low the third local bus to VMEbus map decoder is disabled EN4 When this bit is high the fourth local bus to VMEbus map decoder is enabled When this bit is ...

Page 128: ...the VMEbus short I O segment When this bit is low D32 data transfers are performed to the VMEbus short I O segment I1EN When this bit is high the VMEbus short I O map decoder is enabled When this bit is low the VMEbus short I O map decoder is disabled I2PD When this bit is high the VMEchip2 drives a program address modifier code when the F page is accessed When this bit is low the VMEchip2 drives ...

Page 129: ...isabled to the local bus F page I2EN When this bit is high the F page F0000000 through FF7FFFFF map decoder is enabled The F0 page is defined as A24 D16 on the VMEbus while the F1 FE pages are defined as A32 D16 When this bit is low the F page is disabled ROM Control Register This function is not used on the MVME172 ADR SIZ FFF4002C BIT 7 6 5 4 3 2 1 0 NAME SIZE BSSPD ASPD OPER R W R W R W RESET 0...

Page 130: ...f data may be transferred with one DMAC command Larger transfers can be accomplished using the command chaining mode In the command chaining mode a singly linked list of commands is built in local memory and the table address register in the DMAC is programmed with the starting address of the list of commands The DMAC control register is programmed and the DMAC is enabled The DMAC executes command...

Page 131: ...local bus snoop operation The format of the control word is the same as the lower 16 bits of the control register The command packet also includes a local bus address a VMEbus address a byte count and a pointer to the next command packet in the list The end of a command is indicated by setting bit 0 or 1 of next command address The command packet format is shown in Table 2 2 DMAC Registers This se...

Page 132: ...ntrol the snoop signal lines on the local bus when the DMAC is table walking 0 Snoop inhibited 1 Snoop enabled ROM0 This VMEchip2 bit is not used on the MVME172 Its function is performed by the ROM0 bit in the PROM Access Time Control Register in the MC2 chip Refer to Chapter 3 WAIT RMW This function is not used on the MVME172 ADR SIZ FFF40030 8 bits 6 used of 32 BIT 23 22 21 20 19 18 17 16 NAME W...

Page 133: ... 1 The request level is 1 2 The request level is 2 3 The request level is 3 LVRWD When this bit is high the requester operates in the release when done mode When this bit is low the requester operates in the release on request mode LVFAIR When this bit is high the requester operates in the fair mode When this bit is low the requester does not operate in the fair mode In the fair mode the requester...

Page 134: ...es bus master and the new level takes effect If the VMEchip2 is bus master when the level is changed the new level does not take effect until the bus has been released and re requested at the old level The requester always requests the VMEbus at level 3 the first time following a SYSRESET 0 VMEbus request level 0 1 VMEbus request level 1 2 VMEbus request level 2 3 VMEbus request level 3 DRELM Thes...

Page 135: ...t is high the DMAC halts at the end of a command when the DMAC is operating in the command chaining mode When this bit is low the DMAC executes the next command in the list DMAC Control Register 2 bits 8 15 This portion of the control register is loaded by the processor or by the DMAC when it loads the command word from the command packet Because this register is loaded from the command packet in ...

Page 136: ...er is incremented during DMA transfers When this bit is low the counter is not incremented This bit should normally be set high In special situations such as transferring data to or from a FIFO it may be desirable to not increment the counter SNP These bits control the snoop signal lines on the local bus when the DMAC is local bus master and it is not accessing the command table 0 Snoop inhibited ...

Page 137: ...difier bits 2 5 and address modifier bits 0 and 1 are provided by the DMAC to indicate a block transfer Block transfer mode should not be set in the address modifier codes The special block transfer bits should be set to enable block transfers If non block cycles are required to reach a 32 or 64 bit boundary bits 0 and 1 are used during these cycles BLK These bits control the block transfer modes ...

Page 138: ... is set the DMAC executes D16 block transfers DMAC Local Bus Address Counter In the direct mode this counter is programmed with the starting address of the data in local bus memory DMAC VMEbus Address Counter In the direct mode this counter is programmed with the starting address of the data in VMEbus memory ADR SIZ FFF40038 32 bits BIT 31 0 NAME DMAC Local Bus Address Counter OPER R W RESET 0 PS ...

Page 139: ...t of commands This register gets reloaded by the DMAC with the starting address of the current command The last command in a list should have bits 0 and 1 set in the next command pointer VMEbus Interrupter Control Register ADR SIZ FFF40040 32 bits BIT 31 0 NAME DMAC Byte Counter OPER R W RESET 0 PS ADR SIZ FFF40044 32 bits BIT 31 0 NAME Table Address Counter OPER R W RESET 0 PS ADR SIZ FFF40048 8 ...

Page 140: ...only status bit IRQC This bit is VMEbus interrupt clear bit When this bit is set high the VMEbus interrupt is removed This feature is only used when the IRQ1 broadcast mode is used Normal VMEbus interrupts should never be cleared This bit always reads 0 and writing a 0 to this bit has no effect IRQ1S These bits control the function of the IRQ1 signal line on the VMEbus 0 The IRQ1 signal from the i...

Page 141: ...tatus indicated a parity error during a DRAM data transfer This bit is cleared by writing a one to the MCLR bit in this register This bit is not defined for MVME172 implementation MLBE When this bit is set the MPU received a TEA and additional status was not provided This bit is cleared by writing a one to the MCLR bit in this register MCLR Writing a one to this bit clears the MPU status bits 7 8 ...

Page 142: ...were no errors or the DMAC has finished executing command because the halt bit was set This bit is cleared when the DMAC is enabled VME When this bit is set the DMAC received a VMEbus BERR during a data transfer This bit is cleared when the DMAC is enabled TBL When this bit is set the DMAC received an error on the local bus while it was reading commands from the command packet Additional informati...

Page 143: ...t is cleared by a writing a one to the MCLR bit in this register Programming the Tick and Watchdog Timers The VMEchip2 has two 32 bit tick timers and one watchdog timer This section provides addresses and bit level descriptions of the prescaler tick timer watchdog timer registers and various other timer registers VMEbus Arbiter Time out Control Register This register controls the VMEbus arbiter ti...

Page 144: ... are removed a BERR signal is sent to the VMEbus The global time out timer is disabled when the VMEchip2 is not system controller 0 8 µs 1 64 µs 2 256 µs 3 The timer is disabled TIME ON These bits define the maximum time the DMAC spends on the VMEbus 0 16 µs 4 256 µs 1 32 µs 5 512 µs 2 64 µs 6 1024 µs 3 128 µs 7 When done or no data TIME OFF These bits define the minimum time the DMAC spends off t...

Page 145: ...cess time out value When a transaction is headed to the VMEbus and the VMEchip2 is not the current VMEbus master the access timer begins timing If the VMEchip2 has not received bus mastership before the timer times out and the transaction is not write posted a TEA signal is sent to the local bus If the transaction is write posted a write post error interrupt is sent to the local bus interrupter 0 ...

Page 146: ... 25 MHz the prescaler value is E7 and at 32 MHz it is E0 Non integer local bus clocks introduce an error into the specified times for the various counters and timers This is most notable in the tick timers The tick timer clock can be derived by the following equation tick timer clock B clock 256 prescaler value If the prescaler is not correctly programmed the bus timers do not generate their speci...

Page 147: ... T compare register value T µs When programming the tick timer for periodic interrupts the counter should be cleared to zero by software and then enabled If the counter does not initially start at zero the time to the first interrupt may be longer or shorter than expected Remember the rollover time for the counter is 71 6 minutes Tick Timer 1 Counter This is the tick timer 1 counter When enabled i...

Page 148: ...compare register value T µs When programming the tick timer for periodic interrupts the counter should be cleared to zero by software and then enabled If the counter does not initially start at zero the time to the first interrupt may be longer or shorter than expected Remember the rollover time for the counter is 71 6 minutes Tick Timer 2 Counter This is the tick timer 2 counter When enabled it i...

Page 149: ...RS This bit is set by a powerup reset It is cleared by a write to the CPURS bit BRFLI When this status bit is high the BRDFAIL signal pin on the VMEchip2 is asserted When this status bit is low the BRDFAIL signal pin on the VMEchip2 is not asserted The BRDFAIL pin may be asserted by an external device the BDFLO bit in this register or a watchdog time out SFFL When this status bit is high the SYSFA...

Page 150: ...g timer has timed out and the watchdog reset enable WDRSE bit in this register is high an LRESET signal is generated on the local bus WDBFE When this bit is high and the watchdog timer has timed out the VMEchip2 asserts the BRDFAIL signal pin When this bit is low the watchdog timer does not contribute to the BRDFAIL signal on the VMEchip2 WDTO When this status bit is high a watchdog time out has o...

Page 151: ...ter does not increment COC When this bit is high the counter is reset to zero when it compares with the compare register When this bit is low the counter is not reset COVF The overflow counter is cleared when a one is written to this bit OVF These bits are the output of the overflow counter The overflow counter is incremented each time the tick timer sends an interrupt to the local bus interrupter...

Page 152: ...scaler Counter The VMEchip2 has a 32 bit prescaler that provides the clocks required by the various timers in the chip Access to the prescaler is provided for test purposes The counter is described here because it may be useful in other applications The lower 8 bits of the prescaler counter increment to FF at the local bus clock rate and then they are loaded from the prescaler adjust register When...

Page 153: ...e unique for each interrupter There are two base registers one for the first 16 interrupters and one for the next 8 interrupters The VMEbus interrupters provide their own vectors A summary of the interrupts is shown in Table 2 3 The status bit of an interrupter is affected by the enable bit If the enable bit is low the status bit is also low Interrupts may be polled by setting the enable bit and p...

Page 154: ...s VMEbus IRQ1 External Lowest VMEbus IRQ2 External VMEbus IRQ3 External VMEbus IRQ4 External VMEbus IRQ5 External VMEbus IRQ6 External VMEbus IRQ7 External Spare Y7 Software 0 Y8 Software 1 Y9 Software 2 YA Software 3 YB Software 4 YC Software 5 YD Software 6 YE Software 7 YF GCSR LM0 X0 GCSR LM1 X1 GCSR SIG0 X2 GCSR SIG1 X3 GCSR SIG2 X4 GCSR SIG3 X5 ...

Page 155: ...ion later in this chapter for recommended Vector Base Register values DMAC X6 VMEbus Interrupter Acknowledge X7 Tick Timer 1 X8 Tick Timer 2 X9 VMEbus IRQ1 Edge Sensitive XA Not used on MVME172 XB VMEbus Master Write Post Error XC VMEbus SYSFAIL XD Not used on MVME172 XE VMEbus ACFAIL XF Highest Table 2 3 Local Bus Interrupter Summary Continued Interrupt Vector Priority for Simultaneous Interrupts...

Page 156: ...cal interrupt is not being generated The interrupt status bits are TIC1 Tick timer 1 interrupt TIC2 Tick timer 2 interrupt VI1E VMEbus IRQ1 edge sensitive interrupt PE Not used on MVME172 MWP VMEbus master write post error interrupt SYSF VMEbus SYSFAIL interrupt AB Not used on MVME172 ACF VMEbus ACFAIL interrupt ADR SIZ FFF40068 8 bits of 32 BIT 31 30 29 28 27 26 25 24 NAME ACF AB SYSF MWP PE VI1E...

Page 157: ...atus bit is low a local interrupt is not being generated The interrupt status bits are LM0 GCSR LM0 interrupt LM1 GCSR LM1 interrupt SIG0 GCSR SIG0 interrupt SIG1 GCSR SIG1 interrupt SIG2 GCSR SIG2 interrupt SIG3 GCSR SIG3 interrupt DMA DMAC interrupt VIA VMEbus interrupter acknowledge interrupt ADR SIZ FFF40068 8 bits of 32 BIT 23 22 21 20 19 18 17 16 NAME VIA DMA SIG3 SIG2 SIG1 SIG0 LM1 LM0 OPER...

Page 158: ...pt status bit is low a local interrupt is not being generated The interrupt status bits are SW0 Software 0 interrupt SW1 Software 1 interrupt SW2 Software 2 interrupt SW3 Software 3 interrupt SW4 Software 4 interrupt SW5 Software 5 interrupt SW6 Software 6 interrupt SW7 Software 7 interrupt ADR SIZ FFF40068 8 bits of 32 BIT 15 14 13 12 11 10 9 8 NAME SW7 SW6 SW5 SW4 SW3 SW2 SW1 SW0 OPER R R R R R ...

Page 159: ... status bit is low a local interrupt is not being generated The interrupt status bits are VME1 VMEbus IRQ1 Interrupt VME2 VMEbus IRQ2 Interrupt VME3 VMEbus IRQ3 Interrupt VME4 VMEbus IRQ4 Interrupt VME5 VMEbus IRQ5 Interrupt VME6 VMEbus IRQ6 Interrupt VME7 VMEbus IRQ7 Interrupt SPARE Not used ADR SIZ FFF40068 8 bits of 32 BIT 7 6 5 4 3 2 1 0 NAME SPARE VME7 VME6 VME5 VME4 VME3 VME2 VME1 OPER R R R...

Page 160: ...f necessary edge sensitive interrupters should be cleared to remove any old interrupts and then enabled ETIC1 Enable tick timer 1 interrupt ETIC2 Enable tick timer 2 interrupt EVI1E Enable VMEbus IRQ1 edge sensitive interrupt EPE Not used on MVME172 EMWP Enable VMEbus master write post error interrupt ESYSF Enable VMEbus SYSFAIL interrupt EAB Not used on MVME172 EACF Enable VMEbus ACFAIL interrupt...

Page 161: ...from being set If necessary edge sensitive interrupters should be cleared to remove any old interrupts and then enabled ELM0 Enable GCSR LM0 interrupt ELM1 Enable GCSR LM1 interrupt ESIG0 Enable GCSR SIG0 interrupt ESIG1 Enable GCSR SIG1 interrupt ESIG2 Enable GCSR SIG2 interrupt ESIG3 Enable GCSR SIG3 interrupt EDMA Enable DMAC interrupt EVIA VMEbus interrupter acknowledge interrupt ADR SIZ FFF40...

Page 162: ...om being set If necessary edge sensitive interrupters should be cleared to remove any old interrupts and then enabled ESW0 Enable software 0 interrupt ESW1 Enable software 1 interrupt ESW2 Enable software 2 interrupt ESW3 Enable software 3 interrupt ESW4 Enable software 4 interrupt ESW5 Enable software 5 interrupt ESW6 Enable software 6 interrupt ESW7 Enable software 7 interrupt ADR SIZ FFF4006C 8...

Page 163: ... from being set If necessary edge sensitive interrupters should be cleared to remove any old interrupts and then enabled EIRQ1 Enable VMEbus IRQ1 interrupt EIRQ2 Enable VMEbus IRQ2 interrupt EIRQ3 Enable VMEbus IRQ3 interrupt EIRQ4 Enable VMEbus IRQ4 interrupt EIRQ5 Enable VMEbus IRQ5 interrupt EIRQ6 Enable VMEbus IRQ6 interrupt EIRQ7 Enable VMEbus IRQ7 interrupt SPARE SPARE ADR SIZ FFF4006C 8 bit...

Page 164: ...SSW7 Set software 7 interrupt Interrupt Clear Register bits 24 31 This register is used to clear the edge sensitive interrupts An interrupt is cleared by writing a one to its clear bit The clear bits are defined below CTIC1 Clear tick timer 1 interrupt CTIC2 Clear tick timer 2 interrupt ADR SIZ FFF40070 8 bits of 32 BIT 15 14 13 12 11 10 9 8 NAME SSW7 SSW6 SSW5 SSW4 SSW3 SSW2 SSW1 SSW0 OPER S S S ...

Page 165: ...ar the edge sensitive interrupts An interrupt is cleared by writing a one to its clear bit The clear bits are defined below CLM0 Clear GCSR LM0 interrupt CLM1 Clear GCSR LM1 interrupt CSIG0 Clear GCSR SIG0 interrupt CSIG1 Clear GCSR SIG1 interrupt CSIG2 Clear GCSR SIG2 interrupt CSIG3 Clear GCSR SIG3 interrupt CDMA Clear DMA controller interrupt CVIA Clear VMEbus interrupter acknowledge interrupt ...

Page 166: ...errupt CSW5 Clear software 5 interrupt CSW6 Clear software 6 interrupt CSW7 Clear software 7 interrupt Interrupt Level Register 1 bits 24 31 This register is used to define the level of the abort interrupt and the ACFAIL interrupt AB LEVEL Not used on MVME172 ACF LEVEL These bits define the level of the ACFAIL interrupt ADR SIZ FFF40074 8 bits of 32 BIT 15 14 13 12 11 10 9 8 NAME CSW7 CSW6 CSW5 CS...

Page 167: ...SFAIL interrupt Interrupt Level Register 1 bits 8 15 This register is used to define the level of the VMEbus IRQ1 edge sensitive interrupt and the level of the external parity error interrupt IRQ1E LEVEL These bits define the level of the VMEbus IRQ1 edge sensitive interrupt PE LEVEL Not used on MVME172 ADR SIZ FFF40078 8 bits 6 used of 32 BIT 23 22 21 20 19 18 17 16 NAME SYSF LEVEL WPE LEVEL OPER...

Page 168: ...terrupt Level Register 2 bits 24 31 This register is used to define the level of the DMA controller interrupt and the VMEbus acknowledge interrupt DMA LEVEL These bits define the level of the DMA controller interrupt VIA LEVEL These bits define the level of the VMEbus interrupter acknowledge interrupt ADR SIZ FFF40078 8 bits 6 used of 32 BIT 7 6 5 4 3 2 1 0 NAME TICK2 LEVEL TICK1 LEVEL OPER R W R ...

Page 169: ... interrupt Interrupt Level Register 2 bits 8 15 This register is used to define the level of the GCSR SIG0 interrupt and the GCSR SIG1 interrupt SIG0 LEVEL These bits define the level of the GCSR SIG0 interrupt SIG1 LEVEL These bits define the level of the GCSR SIG1 interrupt ADR SIZ FFF4007C 8 bits 6 used of 32 BIT 23 22 21 20 19 18 17 16 NAME SIG3 LEVEL SIG2 LEVEL OPER R W R W RESET 0 PSL 0 PSL ...

Page 170: ...terrupt Interrupt Level Register 3 bits 24 31 This register is used to define the level of the software 6 interrupt and the software 7 interrupt SW6 LEVEL These bits define the level of the software 6 interrupt SW7 LEVEL These bits define the level of the software 7 interrupt ADR SIZ FFF4007C 8 bits 6 used of 32 BIT 7 6 5 4 3 2 1 0 NAME LM1 LEVEL LM0 LEVEL OPER R W R W RESET 0 PSL 0 PSL ADR SIZ FF...

Page 171: ... 5 interrupt Interrupt Level Register 3 bits 8 15 This register is used to define the level of the software 2 interrupt and the software 3 interrupt SW2 LEVEL These bits define the level of the software 2 interrupt SW3 LEVEL These bits define the level of the software 3 interrupt ADR SIZ FFF40080 8 bits 6 used of 32 BIT 23 22 21 20 19 18 17 16 NAME SW5 LEVEL SW4 LEVEL OPER R W R W RESET 0 PSL 0 PS...

Page 172: ...l Register 4 bits 24 31 This register is used to define the level of the VMEbus IRQ7 interrupt and the spare interrupt The VMEbus level 7 IRQ7 interrupt may be mapped to any local bus interrupt level VIRQ7 LEVEL These bits define the level of the VMEbus IRQ7 interrupt SPARE LEVELNot used on the MVME172 ADR SIZ FFF40080 8 bits 6 used of 32 BIT 7 6 5 4 3 2 1 0 NAME SW1 LEVEL SW0 LEVEL OPER R W R W R...

Page 173: ...IRQ6 interrupt Interrupt Level Register 4 bits 8 15 This register is used to define the level of the VMEbus IRQ3 interrupt and the VMEbus IRQ4 interrupt The VMEbus level 3 IRQ3 interrupt and the VMEbus level 4 IRQ4 interrupt may be mapped to any local bus interrupt level VIRQ3 LEVEL These bits define the level of the VMEbus IRQ3 interrupt VIRQ4 LEVEL These bits define the level of the VMEbus IRQ4 ...

Page 174: ...he interrupt base vectors VBR 1 These bits define the interrupt base vector 1 VBR 0 These bits define the interrupt base vector 0 Note Refer to Table 2 3 Local Bus Interrupter Summary for further information A suggested setting for the Vector Base Register for the VMEchip2 is VBR0 6 VBR1 7 i e setting the Vector Base Register at address FFF40088 to 67xxxxxx This produces a Vector Base0 of 60 corre...

Page 175: ...the status of the ABORT switch When this bit is high the ABORT switch is depressed When this bit is low the ABORT switch is not depressed ACFL This bit indicates the status of the ACFAIL signal line on the VMEbus When this bit is high the ACFAIL signal line is active When this bit is low the ACFAIL signal line is not active SYSFL This bit indicates the status of the SYSFAIL signal line on the VMEb...

Page 176: ...Status and Control Register GPIOI1 Not used GPIOI2 Not used GPIOI3 Not used I O Control Register 3 This function is not used on the MVME172 ADR SIZ FFF40088 8 bits of 32 BIT 15 14 13 12 11 10 9 8 NAME GPIOO3 GPIOO2 GPIOO1 GPIOO0 GPIOI3 GPIOI2 GPIOI1 GPIOI0 OPER R W R W R W R W R R R R RESET 0 PSL 0 PS 0 PS 0 PS X X X X ADR SIZ FFF40088 8 bits of 32 BIT 7 6 5 4 3 2 1 0 NAME GPI7 GPI6 GPI5 GPI40 GPI...

Page 177: ...access the local bus a deadlock is created The VMEchip2 detects this condition and requests the local bus master to give up the local bus and retry the cycle This allows the VMEbus master to complete the cycle to the local bus If the VMEchip2 receives VMEbus mastership the local master has not returned from the retry and this bit is high VMEchip2 drives VMEbus BBSY for the minimum time about 90 ns...

Page 178: ...h the VME LED on the MVME172 is lit when local bus reset is asserted or the VMEchip2 is driving local bus busy When this bit is low the VME LED on the MVME172 is lit when local bus reset is asserted the VMEchip2 is driving local bus busy or the VMEchip2 is driving the VMEbus address strobe DISSRAM When this bit is high the SRAM decoder in the VMEchip2 is disabled When this bit is low the SRAM deco...

Page 179: ...he group are cleared The signal interrupts SIG0 SIG3 should be used to signal individual boards The location monitors are located in the VMEbus short I O space and the specific address is determined by the VMEchip2 group address The location monitors LM0 LM3 are located at addresses XXF1 XXF3 XXF5 and XXF7 respectively A location monitor cycle on the VMEbus is generated by a read or write to VMEbu...

Page 180: ...ear register The board control register allows a VMEbus master to reset the local bus prevent the VMEchip2 from driving the SYSFAIL signal line and detect if the VMEchip2 wants to drive the SYSFAIL signal line The six general purpose registers can be read and written from both the local bus and the VMEbus These registers are provided to allow local bus masters to communicate with VMEbus masters Th...

Page 181: ...e 2 shows the bits defined by this table Line 3 defines the name of the register or the name of the bits in the register Line 4 defines the operations possible on the register bits as follows Line 5 defines the state of the bit following a reset as defined below R This bit is a read only status bit R W This bit is readable and writable S R Writing a one to this bit sets it Reading it returns its c...

Page 182: ...2 11 10 9 8 7 6 5 4 3 2 1 0 0 0 Chip Revision Chip ID 2 4 LM3 LM2 LM1 LM0 SIG3 SIG2 SIG1 SIG0 RST ISF BF SCON SYSF L X X X 4 8 General Purpose Control and Status Register 0 6 C General Purpose Control and Status Register 1 8 10 General Purpose Control and Status Register 2 A 14 General Purpose Control and Status Register 3 C 18 General Purpose Control and Status Register 4 E 1C General Purpose Con...

Page 183: ...p2 ID register The ID for the VMEchip2 is 10 VMEchip2 LM SIG Register This register is the VMEchip2 location monitor register and the interrupt register ADR SIZ Local Bus FFF40100 VMEbus XXY0 8 bits BIT 15 8 NAME VMEchip2 Revision Register OPER R RESET 01 PS ADR SIZ Local Bus FFF40100 VMEbus XXY0 8 bits BIT 7 0 NAME VMEchip2 ID Register OPER R RESET 10 PS ADR SIZ Local Bus FFF40104 VMEbus XXY2 8 b...

Page 184: ...er or the CSIG2 bit in the local interrupt clear register SIG3 The SIG3 bit is set when a VMEbus master writes a one to it When the SIG3 bit is set an interrupt is sent to the local bus interrupter The SIG3 bit is cleared when the local processor writes a one to the SIG3 bit in this register or the CSIG3 bit in the local interrupt clear register LM0 This bit is cleared by an LM0 cycle on the VMEbu...

Page 185: ...s bit is low the Board Fail signal is inactive When this bit is set the VMEchip2 drives SYSFAIL if the inhibit SYSFAIL bit is not set ISF When this bit is set the VMEchip2 is prevented from driving the VMEbus SYSFAIL signal line When this bit is cleared the VMEchip2 is allowed to drive the VMEbus SYSFAIL signal line RST This bit allows a VMEbus master to reset the local bus Refer to the note on lo...

Page 186: ...hardware specification General Purpose Register 1 This register is a general purpose register that allows a local bus master to communicate with a VMEbus master The function of this register is not defined by the hardware specification ADR SIZ Local Bus FFF40108 VMEbus XXY4 16 bits BIT 15 0 NAME General Purpose Register 0 OPER R W RESET 0 PS ADR SIZ Local Bus FFF4010C VMEbus XXY6 16 bits BIT 15 0 ...

Page 187: ...e hardware specification General Purpose Register 3 This register is a general purpose register that allows a local bus master to communicate with a VMEbus master The function of this register is not defined by the hardware specification ADR SIZ Local Bus FFF40110 VMEbus XXY8 16 bits BIT 15 0 NAME General Purpose Register 2 OPER R W RESET 0 PS ADR SIZ Local Bus FFF40114 VMEbus XXYA 16 bits BIT 15 ...

Page 188: ...hardware specification General Purpose Register 5 This register is a general purpose register that allows a local bus master to communicate with a VMEbus master The function of this register is not defined by the hardware specification ADR SIZ Local Bus FFF40118 VMEbus XXYC 16 bits BIT 15 0 NAME General Purpose Register 4 OPER R W RESET 0 PS ADR SIZ Local Bus FFF4011C VMEbus XXYE 16 bits BIT 15 0 ...

Page 189: ...nterface with bus sizing Flash interface with bus sizing SRAM controller supporting several configurations DRAM controller supporting several configurations Four Zilog serial interfaces implemented with Z85230 SCC device NCR 53C710 SCSI Coprocessor interface Intel 82596CA LAN Coprocessor interface Four 32 bit tick timers Interrupt support for ABORT switch LAN SCSI SCC DRAM and Timers Local bus acc...

Page 190: ... 500 Series modules The Flash and PROM memory map locations can be swapped based upon a jumper J11 pins 7 and 8 GPI3 input to the initialization PAL The initialization device was discussed in the previous section This enables the MVME172 to execute reset code from either the PROM or Flash The MC2 chip executes multiple cycles to the eight bit Flash PROM devices so that byte word or longword access...

Page 191: ... is described in the following sections MPU Port and MPU Channel Attention The MC2 chip allows the MC68060 bus master to communicate directly with the Intel 82596CA LAN Coprocessor by providing a map decoder and required control and timing logic Two types of direct access are feasible with the 82596CA MPU Port and MPU Attention MPU Port access enables the MPU to write to an internal 32 bit 82596CA...

Page 192: ...l Register Transfer Types TT1 TT0 with the value of 00 Transfer Modifiers TM2 TM0 with the value of 101 Transfer Start Read Size Transfer in progress LANC Bus Error The 82596CA does not provide a way to terminate a bus cycle with an error indication Bus error are processed in the following way The 82596CA interface logic monitors all bus cycles initiated by the 82596CA and if a bus error is indica...

Page 193: ...nterrupt is enabled and a low level is detected on the 53C710 IRQ pin SRAM Memory Controller The SRAM base address and size are programmable The SRAM controller is designed to operate with 100 ns devices The size of the SRAM is initialized in the DRAM SRAM Options Register when the MVME172 is reset SRAM performance at 25 MHz is 5 3 3 3 for read and write cycle SRAM performance at 33 MHz is 6 4 4 4...

Page 194: ...pts from the first Z85230 have priority over those from the second Z85230 The MC2 chip supports as many as four Z85230 devices There are two Z85230s on the MVME172 Refer to the Board Level Hardware Description in your MVME172 installation and use manual The Table 3 1 DRAM Performance Clock Budget Operating Conditions 4 2 2 2 Non interleaved read 25 MHz without TEA on parity error 4 1 1 1 Interleav...

Page 195: ...iming There are two modes of operation for these timers free running and clear on compare In the free running mode the timers have a resolution of 1 µs and roll over after the count reaches the maximum value FFFFFFFF The terminal count period for the timers is 71 6 minutes When the counter is enabled in the clear on compare mode it increments every 1 µs until the counter value matches the value in...

Page 196: ...out value is selectable by software for 8 µsec 64 µsec 256 µsec or infinite The local bus timer does not operate during VMEbus bound cycles VMEbus bound cycles are timed by the VMEbus access timer and the VMEbus global timer Refer to the section on Example of the Proper Use of Bus Timers in Chapter 1 for more information The access timer logic is duplicated in the VMEchip2 and MC2 chip ASIC Becaus...

Page 197: ...r 1 Control 18 Tick Timer 4 Interrupt Control Tick Timer 3 Interrupt Control Tick Timer 2 Interrupt Control Tick Timer 1 Interrupt Control 1C DRAM Parity Error Interrupt Control SCC Interrupt Control Tick Timer 4 Control Tick Timer 3 Control 20 DRAM Space Base Address Register SRAM Space Base Address Register 24 DRAM Space Size DRAM SRAM Options SRAM Space Size Reserved 28 LANC Error Status Reserv...

Page 198: ...er bit This bit reads zero The possible states of the bits after local and power up reset are as defined below P The bit is affected by power up reset L The bit is affected by local reset X The bit is not affected by reset 0 The bit is always 0 1 The bit is always 1 40 Bus Clock PROM Access Time Control Flash Access Time Control ABORT Switch Interrupt Control 44 RESET Switch Control Watchdog Timer...

Page 199: ...current value of the chip revision is 01 This register is read only It ignores a write but ends the cycle with TA i e the cycle terminates without exceptions ADR SIZ FFF42000 8 bits BIT 31 30 29 28 27 26 25 24 NAME ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 OPER R R R R R R R R RESET 1 PL 0 PL 0 PL 0 PL 0 PL 1 PL 0 PL 0 PL ADR SIZ FFF42000 8 bits BIT 23 22 21 20 19 18 17 16 NAME RV7 RV6 RV5 RV4 RV3 RV2 RV1 R...

Page 200: ... use devices slower than 270 ns 9 CLK cycles at 32 MHz MIEN Master Interrupt Enable When this bit is high interrupts from and via the MC2 chip are allowed to reach the MPU When it is low all interrupts from the MC2 chip are disabled Also when the bit is low all interrupt acknowledge cycles to the MC2 chip are passed on via the IACKOUT pin This bit is cleared by a reset PPC PowerPC interrupt mode W...

Page 201: ...e least significant four bits encode the interrupt source during the acknowledge cycle The exception to this is that after reset occurs the interrupt vector passed is 0f which remains in effect until a write is generated to the vector base register A normal read access to the vector base register yields the value 0f if the read happens before it has been initialized A normal read access yields all...

Page 202: ...P2 chip and then the VMEchip2 ASIC Note The Z85230 controllers have an integrated interrupt vector register which is separate from the vector generation found on the MC2 chip The Z85230 also supports a scheme where the base register value is changed based upon the interrupt requested During the interrupt acknowledge cycle interrupts from the first Z85230 have priority over those from the second Z8...

Page 203: ...er is incremented If the clear on compare mode is enabled the counter is also cleared For periodic interrupts the following equation should be used to calculate the compare register value for a specific period T T µs Compare Register When programming the tick timer for periodic interrupts the counter should be cleared to zero by software and then enabled If the counter does not initially start at ...

Page 204: ...mer 1 Counter Tick Timer 2 Compare Register ADR SIZ FFF42004 32 bits BIT 31 0 NAME Tick Timer 1 Compare Register OPER R W RESET 0 P ADR SIZ FFF42008 32 bits BIT 31 0 NAME Tick Timer 1 Counter OPER R W RESET X ADR SIZ FFF4200C 32 bits BIT 31 0 NAME Tick Timer 2 Compare Register OPER R W RESET 0 P ...

Page 205: ...generate the 1 MHz clock for the four tick timers This register is read only It increments to ff at the processor frequency then it is loaded from the Prescaler Clock Adjust Register ADR SIZ FFF42010 32 bits BIT 31 0 NAME Tick Timer 2 Counter OPER R W RESET X ADR SIZ FFF42014 8 bits BIT 31 24 NAME LSB Prescaler Count OPER R RESET X ...

Page 206: ...fied times for the tick timers The tick timer clock can be derived by the following equation Tick clock processor clock 256 Prescaler Value The maximum clock frequency for the tick timers is the processor clock divided by two The value FF is not allowed to be programmed into this register If a write with the value of FF occurs to this register the cycle terminates correctly but the register remain...

Page 207: ...nter is cleared when a one is written to this bit OVF3 OVF0 These bits are the output of the overflow counter The overflow counter is incremented each time the tick timer sends an interrupt to the local bus interrupter The overflow counter can be cleared by writing a one to COVF ADR SIZ FFF42014 8 bits BIT 15 14 13 12 11 10 9 8 NAME OVF3 OVF2 OVF1 OVF0 COVF COC CEN OPER R R R R R C R W R W RESET 0...

Page 208: ...ick Timer 2 Interrupt Control Register ADR SIZ FFF42018 8 bits BIT 31 30 29 28 27 26 25 24 NAME INT IEN ICLR IL2 IL1 IL0 OPER R R R R W C R W R W R W RESET 0 0 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL ADR SIZ FFF42018 8 bits BIT 23 22 21 20 19 18 17 16 NAME INT IEN ICLR IL2 IL1 IL0 OPER R R R R W C R W R W R W RESET 0 0 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL ADR SIZ FFF4201A 8 bits BIT 15 14 13 12 11 10 9 8 NAME INT ...

Page 209: ...s register This bit is always read as zero IEN When this bit is set high the interrupt is enabled The interrupt is disabled when this bit is low INT When this bit is high a Tick Timer interrupt is being generated at the level programmed in IL2 IL0 if nonzero This bit is edge sensitive and can be cleared by writing a logic 1 into the ICLR control bit ADR SIZ FFF4201B 8 bits BIT 7 6 5 4 3 2 1 0 NAME...

Page 210: ...riting a logic 1 to this bit clears the DRAM parity error detection interrupt This clears the INT bit in this register This bit is always read as zero IEN This bit set to a one enables the parity error interrupt If this bit is set to a one and the PAREN and PARINT bits are set to 01 or 11 and a parity error occurs an interrupt is generated at the level programmed in the IL2 IL0 bits The PAREN and ...

Page 211: ...reflects the state of the INT pin from either Z85230 controller qualified by the IEN bit When this bit is high an SCC controller interrupt is being generated at the level programmed in IL2 IL0 When the interrupt is cleared in the Z85230 INT returns to zero During the interrupt acknowledge cycle interrupts from the first Z85230 have priority over those from the second Z85230 ADR SIZ FFF4201C 8 bits...

Page 212: ...VF The overflow counter is cleared when a one is written to this bit OVF3 OVF0 These bits are the output of the overflow counter The overflow counter is incremented each time the tick timer sends an interrupt to the local bus interrupter The overflow counter can be cleared by writing a one to COVF ADR SIZ FFF4201C 8 bits BIT 15 14 13 12 11 10 9 8 NAME OVF3 OVF2 OVF1 OVF0 COVF COC CEN OPER R R R R ...

Page 213: ... FFF42024 bits 20 16 to determine the size of the SRAM and DRAM DRAM Space Base Address Register B31 B20 B31 B20 are compared to local bus address signals A31 A20 for memory reference cycles If they compare a DRAM cycle is initiated Note that there is linkage between the Base Address Register and its associated Size Register The Size Register masks the least significant address signals for the com...

Page 214: ...or a particular memory size The following table defines their encoding Note that the table specifies the allowed bit combinations for DZ2 DZ0 Any other combinations generate unpredictable results DZ2 DZ0 are set equal to the DZ2 DZ0 bits of the DRAM SRAM Options Register Note that changing DZ2 DZ0 so that the DRAM architecture changes between interleaved and non interleaved relocates the data DZ2 ...

Page 215: ... the contents of a factory programmed resident device SZ1 SZ0 SZx bits indicate the size of the SRAM array Software must initialize the SRAM Space Size Register FFF42024 bits 9 8 based on the value of SZ1 SZ0 Table 3 4 DRAM Size Control Bit Encoding DZ2 DZ0 Memory Size 0 Not defined for MVME172 1 Not defined for MVME172 2 Not defined for MVME172 3 Not defined for MVME172 4 4 MByte non interleaved ...

Page 216: ... used F0 set to a 1 indicates that four 28F020 256K x 8 Flash memory devices are used Table 3 5 DRAM Size Control Bit Encoding DZ2 DZ0 DRAM Configuration 0 Not defined for MVME172 1 Not defined for MVME172 2 Not defined for MVME172 3 Not defined for MVME172 4 4 MByte non interleaved 5 8 MByte non interleaved 6 DRAM is not present 7 16 MByte interleaved Table 3 6 SRAM Size Control Bit Encoding SZ1 ...

Page 217: ... SZ0 Any other combinations generate unpredictable results SZ1 SZ0 are set equal to the SZ1 SZ0 bits of the DRAM SRAM Options Register SZ1 SZ0 are programmable to facilitate diagnostic software Note For an MVME172 with 128 KB of SRAM the software must program SZ1 SZ0 1 512 KB Therefore the SRAM contents will repeat in the memory map ADR SIZ FFF42024 8 bits BIT 15 14 13 12 11 10 9 8 NAME SEN SZ1 SZ...

Page 218: ...ives TEA if the source of the error is local time out then LTO is set and EXT and PRTY are cleared If the source of the TEA is due to an error in going to the VMEbus then EXT is set and the other two status bits are cleared If the source of the error is DRAM parity check error then PRTY is set and the other two status bits are cleared If the source of the error is none of the above conditions then...

Page 219: ...by the IEN bit When this bit is high a LANC INT interrupt is being generated at the level programmed in IL2 IL0 E L Edge or Level When this bit is high the interrupt is edge sensitive The interrupt is level sensitive when this bit is low PLTY Polarity When this bit is low interrupt is activated by a rising edge high level of the LANC INT pin When this bit is high interrupt is activated by a fallin...

Page 220: ... the INT status bit This bit is always read as zero IEN Interrupt Enable When this bit set high the interrupt is enabled The interrupt is disabled when this bit is low INT Interrupt Status When this bit is high a LANC Bus Error interrupt is being generated at the level programmed in IL2 IL0 SC0 Snoop Control 0 Snoop enabled 1 Snoop disabled ADR SIZ FFF42028 8 bits BIT 7 6 5 4 3 2 1 0 NAME SC1 SC0 ...

Page 221: ...T is set and the other two status bits are cleared If the source of the error is DRAM parity check error then PRTY is set and the other two status bits are cleared If the source of the error is none of the above conditions then all three bits are cleared Writing a 1 to bit 24 SCLR also clears all three bits General Purpose Inputs Register The contents of a PAL and the state of an 8 position jumper...

Page 222: ...72 Local Bus Memory Map The jumper for V11 is located at J21 pins 7 8 on the 200 300 Series or J28 pins 9 10 on the 400 500 Series for GPI3 Refer to your MVME172 installation and use manual for jumper pin definitions Caution Removing the jumper from J28 pins 9 10 on the 400 500 Series module will cause the reset code to execute from EPROM as described in the MVME172 installation and use manual V15...

Page 223: ...processor and local bus Refer to the following table for the bit definitions No plans to productize this combination V1 V1 set to a one indicates that the VMEchip2 ASIC is not present V1 set to a zero indicates that a VMEbus interface is present If V1 0 the MC2 chip reset logic and local bus access timer are inhibited V2 V2 set to a one indicates that the SCSI interface is not present V2 set to a ...

Page 224: ...served for internal use only SCSI Interrupt Control Register IL2 IL0 Interrupt Level These three bits select the interrupt level for the SCSI processor Level 0 does not generate an interrupt IEN Interrupt Enable When this bit is set high the interrupt is enabled The interrupt is disabled when this bit is low INT Interrupt Status This status bit reflects the state of the INT pin from the SCSI proce...

Page 225: ...aintain this relative position in the memory map Refer to the sections on tick timer one and two in this chapter for a description of the tick timers Tick Timer 3 Compare Register Tick Timer 3 Counter ADR SIZ FFF42030 32 bits BIT 31 0 NAME Tick Timer 3 Compare Register OPER R W RESET 0 P ADR SIZ FFF42034 32 bits BIT 31 0 NAME Tick Timer 3 Counter OPER R W RESET X ...

Page 226: ...ue programmed in this register to control the refresh timer so that the DRAMs are refreshed every 15 6 microseconds After power up this register is initialized to 10 for 16 MHz ADR SIZ FFF42038 32 bits BIT 31 0 NAME Tick Timer 4 Compare Register OPER R W RESET 0 P ADR SIZ FFF4203C 32 bits BIT 31 0 NAME Tick Timer 4 Counter OPER R W RESET X ADR SIZ FFF42040 8 bits BIT 31 30 29 28 27 26 25 24 NAME B...

Page 227: ...n be changed by software to adjust for a specific speed ET2 ET0 PROM access time is controlled by the state of ET2 ET0 The following table defines the ET2 ET0 encoding note that for the MVE172 whose bus frequency is 1 2 the processor frequency only the 33MHz column applies ADR SIZ FFF42040 8 bits BIT 23 22 21 20 19 18 17 16 NAME ROM0 ET2 ET1 ET0 OPER R R R R W R R W R W R W RESET 0 0 0 1 PL 0 1 PL...

Page 228: ...emory space FWEN set to a 0 inhibits writes to the Flash memory but the cycle completes without exception FT2 FT0 Flash memory access time is controlled by the state of FT2 FT0 The following table defines the FT2 FT0 encoding for the MVE172 whose bus frequency is 1 2 the processor frequency only the 33MHz column applies ADR SIZ FFF42040 8 bits BIT 15 14 13 12 11 10 9 8 NAME FWEN FT2 FT1 FT0 OPER R...

Page 229: ...lways read as zero IEN When this bit set high the interrupt is enabled The interrupt is disabled when this bit is low INT When this bit is high an interrupt is being generated for the ABORT switch Therefore the interrupt is level sensitive to the presence of the INT bit The interrupt is at the level programmed in IL2 IL0 ABS The ABORT switch status set to a one indicates that the ABORT switch is p...

Page 230: ...hip asserts the BRDFAIL signal pin This signal is wired or to the VMEchip2 board fail pin It controls the board fail FAIL LED on the MVME172 CPURS When this bit is set high the power up reset status bit is cleared This bit is always read zero PURS This bit is set by a power up reset It is cleared by a write to the CPURS bit BRFLI When this status bit is high the BRDFAIL signal pin on the MC2 chip ...

Page 231: ... a watchdog time out does not cause a reset WDBFE When this bit is high and the watchdog timer has timed out the MC2 chip asserts the BRDFAIL signal pin When this bit is low the watchdog timer does not contribute to the BRDFAIL signal on the MC2 chip WDTO When this status bit is high a watchdog time out has occurred When this status bit is low a watchdog time out has not occurred This bit is clear...

Page 232: ...r in both the VMEchip2 and the MC2 chip WDTO These bits define the watchdog time out period LBTO These bits define the local bus time out value The timer begins timing when TS is asserted on the local bus If TA or TEA is not asserted before the timer times out a TEA ADR SIZ FFF42044 8 bits BIT 15 14 13 12 11 10 9 8 NAME LBTO WDTO OPER R W R W R W RESET 0 0PL 0 PL Bit Encoding Time out Bit Encoding...

Page 233: ...ter controls the parity checking mode and DRAM enable for non ECC applications RAMEN This bit enables the access of the DRAM The DRAM should be enabled after the DRAM Space Base Address Register is enabled and the ROM0 bit has been cleared The DRAM Space Base Address Register is located at FFF42020 bits 31 16 and the ROM0 bit is located at FFF42040 bit 20 ADR SIZ FFF42048 8 bits BIT 31 30 29 28 27...

Page 234: ...occurs Note that CHECKED cycles lengthen the DRAM accesses by one clock tick WWP Setting WWP to a one causes inverted parity to be written to the DRAM This is used for diagnostic software MPU Status Register This logic is duplicated in the VMEchip2 at location FFF40048 bits 11 10 9 and 7 The duplication is to enable No VMEbus Interface operation PAREN PARINT MPU Alternate 0 0 NONE NONE 0 1 INTERRU...

Page 235: ...ated a parity error during a DRAM data transfer This bit is cleared by writing a one to the MCLR bit in this register This bit is used with the No VMEbus Interface option and is duplicated in the VMEchip2 at address FFF40048 bit 9 MLBE When this bit is set the MPU received a TEA and additional status was not provided This bit is cleared by writing a one to the MCLR bit in this register This bit is...

Page 236: ... to Writes to this register must be 32 bits LSB7 0 The least significant bits of the 32 bit prescaler These bits are read only They are duplicated in the memory map in the MC2 chip at FFF42014 MSB31 8 The most significant bits of the prescaler Note that for the No VMEbus Interface option the 32 bit Prescaler Count Register is located at FFF40064 in addition to FFF4204C This means that this registe...

Page 237: ...t double size IndustryPack cycles Supports four DMA channels one per IndustryPack interface or two channels on IP_a and IP_c Supports a programmable clock for strobe generation to the IndustryPack interface Provides dynamic bus sizing for accesses to IndustryPack Memory Space Fixed base address for IndustryPack I O ID spaces Programmable base address size for IndustryPack Memory Space Thirteen Int...

Page 238: ...d IndustryPack d IP_d The naming convention for double size IndustryPack population of these positions is IndustryPack a b IP_ab and IndustryPack c d IP_cd A double size IndustryPack can occupy positions A and B or it can occupy positions C and D Note The 200 300 Series MVME172 does not implement interfaces to IP_c and IP_d although these interfaces are documented in Chapter 4 and the physical con...

Page 239: ...nd 32 bit IndustryPack widths The four DMA channels can operate concurrently Each DMA controller has a 32 bit local address counter a 32 bit table address counter a 24 bit byte counter control registers status registers and a 24 bit IP address counter The data path for each DMA controller passes through a FIFO which is eight locations deep and four bytes wide sDMA transfers and byte count paramete...

Page 240: ...al access to the local bus The other method is to set the arbitration priority to one of four states In this case the priority is constant with one DMA channel having the highest priority and the other three having the second third and fourth highest priority Note that the IP specification supports a DMA burst where the DMA cycles can be executed back to back The DMA arbiter logic will not release...

Page 241: ... data path However there are two functions where the latency time affects performance One of them is when a local bus master such at the MC68060 accesses an IndustryPack resource such as reading back to back memory locations One to two IP clock cycles of overhead is associated with this function The other is when arbitration logic must resolve inputs from both clock domains to determine which Indu...

Page 242: ...cal bus slave and a memory or I O space location on an IndustryPack It assumes a zero wait state acknowledge reply from the IndustryPack 4 Burst mode sDMA is not supported when both bus frequencies are 32 MHz 5 Because the specified band width assumes a zero wait state IndustryPack cycle it would be difficult to achieve the stated bandwidths for an IP bus frequency of 32 MHz Table 4 1 IP2 Chip Clo...

Page 243: ...se the polarity of the programmable clock output The programmable clock output s programmable frequency range is from approximately 4 Hz to 16 MHz The programmable clock logic also includes local bus interrupt control Error Reporting The following paragraphs describe the IP2 chip error reporting Error Reporting as a Local Bus Slave The IP2 chip does not have the ability to assert the TEA signal as...

Page 244: ...cknowledged it waits for IACKIN to be asserted then it performs an interrupt acknowledge cycle to the appropriate IndustryPack in order to obtain the vector number It then passes the vector number on to the local bus master and asserts TA to terminate the cycle When the local bus master acknowledges an interrupt if the IP2 chip determines that it is not the source of the interrupt being acknowledg...

Page 245: ...ID Space D16 64B FFF580C0 FFF580FF IP_a ID Space Repeated D16 64B FFF58100 FFF5817F IP_b I O Space D16 128B FFF58180 FFF581BF IP_b ID Space D16 64B FFF581C0 FFF581FF IP_b ID Space Repeated D16 64B FFF58200 FFF5827F IP_c I O Space D16 128B FFF58280 FFF582BF IP_c ID Space D16 64B FFF582C0 FFF582FF IP_c ID Space Repeated D16 64B FFF58300 FFF5837F IP_d I O Space D16 128B FFF58380 FFF583BF IP_d ID Spac...

Page 246: ... IP2 chip CSR registers is shown in Table 4 3 The CSR registers can be accessed as bytes words or longwords They should not be accessed as lines They are shown in the table as bytes and the bits in most of the following register descriptions are labeled as bits 7 through 0 R This bit is a read only status bit R W This bit is readable and writable R C This status bit is cleared by writing a one to ...

Page 247: ...d_BASE25 d_BASE24 0B IP_d MEM BASE LOWER d_BASE23 d_BASE22 d_BASE21 d_BASE20 d_BASE19 d_BASE18 d_BASE17 d_BASE16 0C IP_a MEM SIZE a_SIZE23 a_SIZE22 a_SIZE21 a_SIZE20 a_SIZE19 a_SIZE18 a_SIZE17 a_SIZE16 0D IP_b MEM SIZE b_SIZE23 b_SIZE22 b_SIZE21 b_SIZE20 b_SIZE19 b_SIZE18 b_SIZE17 b_SIZE16 0E IP_c MEM SIZE c_cSIZE23 c_SIZE22 c_SIZE21 c_SIZE20 c_SIZE19 c_SIZE18 c_SIZE17 c_SIZE16 0F IP_d MEM SIZE d_...

Page 248: ...BTD c_MEN 1B IP_d GENERAL CONTROL d_ERR 0 d_RT1 d_RT0 d_WIDTH1 d_WIDTH0 d_BTD d_MEN 1C RESERVED 0 0 0 0 0 0 0 0 1D IP CLOCK 0 0 0 0 0 0 0 IP32 1E DMA ARBITRATION CONTROL 0 0 0 0 0 ROTAT PRI1 PRI0 1F IP RESET 0 0 0 0 0 0 0 RES Table 4 3 IP2 Chip Memory Map Control and Status Registers Continued IP2 Chip Base Address FFFBC000 Register Offset Register Name Register Bit Names D7 D6 D5 D4 D3 D2 D1 D0 ...

Page 249: ...BA6 LBA5 LBA4 LBA3 LBA2 LBA1 LBA0 2C DMA_a IP ADDR 0 0 0 0 0 0 0 0 2D DMA_a IP ADDR IPA23 IPA22 IPA21 IPA20 IPA19 IPA18 IPA17 IPA16 2E DMA_a IP ADDR IPA15 IPA14 IPA13 IPA12 IPA11 IPA10 IPA9 IPA8 2F DMA_a IP ADDR IPA7 IPA6 IPA5 IPA4 IPA3 IPA2 IPA1 IPA0 30 DMA_a BYTE CNT 0 0 0 0 0 0 0 0 31 DMA_a BYTE CNT BCNT23 BCNT22 BCNT21 BCNT20 BCNT19 BCNT18 BCNT17 BCNT16 32 DMA_a BYTE CNT BCNT15 BCNT14 BCNT13 B...

Page 250: ...MA_b LB ADDR LBA7 LBA6 LBA5 LBA4 LBA3 LBA2 LBA1 LBA0 44 DMA_b IP ADDR 0 0 0 0 0 0 0 0 45 DMA_b IP ADDR IPA23 IPA22 IPA21 IPA20 IPA19 IPA18 IPA17 IPA16 46 DMA_b IP ADDR IPA15 IPA14 IPA13 IPA12 IPA11 IPA10 IPA9 IPA8 47 DMA_b IP ADDR IPA7 IPA6 IPA5 IPA4 IPA3 IPA2 IPA1 IPA0 48 DMA_b BYTE CNT 0 0 0 0 0 0 0 0 49 DMA_b BYTE CNT BCNT23 BCNT22 BCNT21 BCNT20 BCNT19 BCNT18 BCNT17 BCNT16 4a DMA_b BYTE CNT BCN...

Page 251: ...LBA6 LBA5 LBA4 LBA3 LBA2 LBA1 LBA0 5C DMA_c IP ADDR 0 0 0 0 0 0 0 0 5D DMA_c IP ADDR IPA23 IPA22 IPA21 IPA20 IPA19 IPA18 IPA17 IPA16 5E DMA_c IP ADDR IPA15 IPA14 IPA13 IPA12 IPA11 IPA10 IPA9 IPA8 5F DMA_c IP ADDR IPA7 IPA6 IPA5 IPA4 IPA3 IPA2 IPA1 IPA0 60 DMA_c BYTE CNT 0 0 0 0 0 0 0 0 61 DMA_c BYTE CNT BCNT23 BCNT22 BCNT21 BCNT20 BCNT19 BCNT18 BCNT17 BCNT16 62 DMA_c BYTE CNT BCNT15 BCNT14 BCNT13 ...

Page 252: ...LBA12 LBA11 LBA10 LBA9 LBA8 73 DMA_d LB ADDR LBA7 LBA6 LBA5 LBA4 LBA3 LBA2 LBA1 LBA0 74 DMA_d IP ADDR 0 0 0 0 0 0 0 0 75 DMA_d IP ADDR IPA23 IPA22 IPA21 IPA20 IPA19 IPA18 IPA17 IPA16 76 DMA_d IP ADDR IPA15 IPA14 IPA13 IPA12 IPA11 IPA10 IPA9 IPA8 77 DMA_d IP ADDR IPA7 IPA6 IPA5 IPA4 IPA3 IPA2 IPA1 IPA0 78 DMA_d BYTE CNT 0 0 0 0 0 0 0 0 79 DMA_d BYTE CNT BCNT23 BCNT22 BCNT21 BCNT20 BCNT19 BCNT18 BCN...

Page 253: ...with TA Caution This register reads zero on some IP2 chips It should read 1 The workaround for this is to test the MC2 chip Revision Register 80 Programmable Clock INT CON TROL 0 IRE INT IEN ICLR IL2 IL1 IL0 81 Programmable Clock GEN CONTROL PLTY PLS 0 EN CLR PS2 PS1 PS0 82 Programmable Clock TIMER T15 T14 T13 T12 T11 T10 T9 T8 83 Programmable Clock TIMER T7 T6 T5 T4 T3 T2 T1 T0 ADR SIZ FFFBC000 8...

Page 254: ...upt vector passed is 07 which remains in effect until a write is generated to the Vector Base Register Note Note that this register does not affect the vector supplied during an interrupt acknowledge cycle for any of the eight IndustryPack IRQ s Caution For some versions of the IP2 chip this register is write only There is NO known workaround for this error This register does return the correct va...

Page 255: ...gisters for IP_a control access for double size ab and those for IP_c control accesses for double size cd For each of the four sets of registers BASE31 BASE16 are compared to MC68060 address signals 31 16 respectively The IP2 chip can address the IndustryPacks only at even multiples of their size Consequently any bits that are set within SIZE23 SIZE16 mask the value programmed into BASE23 BASE16 r...

Page 256: ...1 0 NAME 04 a_BASE31 a_BASE30 a_BASE29 a_BASE28 a_BASE27 a_BASE26 a_BASE25 a_BASE24 NAME 05 a_BASE23 a_BASE22 a_BASE21 a_BASE20 a_BASE19 a_BASE18 a_BASE17 a_BASE16 OPER R W R W R W R W R W R W R W R W RESET 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R ADR SIZ FFFBC006 and FFFBC007 8 bits each BIT 7 6 5 4 3 2 1 0 NAME 06 b_BASE31 b_BASE30 b_BASE29 b_BASE28 b_BASE27 b_BASE26 b_BASE25 b_BASE24 NAME 07 b_BASE23 b_...

Page 257: ...rs which control IP_c and IP_d are not used on the 200 300 Series MVME172 ADR SIZ FFFBC008 and FFFBC009 8 bits each BIT 7 6 5 4 3 2 1 0 NAME 08 c_BASE31 c_BASE30 c_BASE29 c_BASE28 c_BASE27 c_BASE26 c_BASE25 c_BASE24 NAME 09 c_BASE23 c_BASE22 c_BASE21 c_BASE20 c_BASE19 c_BASE18 c_BASE17 c_BASE16 OPER R W R W R W R W R W R W R W R W RESET 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R ADR SIZ FFFBC00A and FFFBC00B...

Page 258: ...IZE22 a_SIZE21 a_SIZE20 a_SIZE19 a_SIZE18 a_SIZE17 a_SIZE16 NAME 0D b_SIZE23 b_SIZE22 b_SIZE21 b_SIZE20 b_SIZE19 b_SIZE18 b_SIZE17 b_SIZE16 NAME 0E c_SIZE23 c_SIZE22 c_SIZE21 c_SIZE20 c_SIZE19 c_SIZE18 c_SIZE17 c_SIZE16 NAME 0F d_SIZE23 d_SIZE22 d_SIZE21 d_SIZE20 d_SIZE19 d_SIZE18 d_SIZE17 d_SIZE16 OPER R W R W R W R W R W R W R W R W RESET 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Size Bits Address Lines t...

Page 259: ...d for the corresponding IndustryPack IRQ The interrupt is at the level programmed in IL2 IL0 E L When this bit is high the interrupt is edge sensitive When the bit is low the interrupt is level sensitive ADR SIZ FFFBC010 through FFFBC017 8 bits each BIT 7 6 5 4 3 2 1 0 NAME 10 a0_PLTY a0_E L a0_INT a0_IEN a0_ICLR a0_IL2 a0_IL1 a0_IL0 NAME 11 a1_PLTY a1_E L a1_INT a1_IEN a1_ICLR a1_IL2 a1_IL1 a1_IL...

Page 260: ...EN a_MEN b_MEN c_MEN d_ MEN enable the local bus to perform read write accesses to their corresponding IndustryPack memory space when set and disable such accesses when cleared When a double size IndustryPack is used in ab a_MEN should be set and the WIDTH and MEN control bits in the IP_b General Control Register should be cleared When a double size IndustryPack is used in cd c_MEN should be set a...

Page 261: ...because they are the only cycles which can occur back to back When BTD is set to a zero the IndustryPack interface will start the next cycle as soon as possible Note The default BTD setting is to insert the additional one clock period delay between read cycles WIDTH1 The IP2 chip assumes the memory space data bus WIDTH0 width of each of IP_a IP_b IP_c and IP_d to be the value decoded from its cont...

Page 262: ... This may help with some devices on IndustryPacks that require dead time between cycles Each recovery timer s counter starts incrementing at the assertion of its IPACK signal and continues to increment until it matches the value encoded from its two recovery timer control bits When it reaches that value the recovery time has expired and a new cycle can be generated to the IndustryPack The recovery...

Page 263: ... size only or if they are restricted to double size longword only and the double size accesses are not interspersed with ID accesses Note that memory accesses do not affect nor are they affected by this behavior a_ERR This bit reflects the state of the ERROR signal from the IP_a interface b_ERR This bit reflects the state of the ERROR signal from the IP_b interface c_ERR This bit reflects the stat...

Page 264: ... are jumpered then the IP clock source is set to 8 MHz For this setting IP32 control bit must be a zero If pins 3 and 2 are jumpered then the IP clock source is set to be synchronous with the MC68060 local bus clock This clock may be 25 MHz 30 MHz or 32 MHz depending on the model For this setting IP32 control bit must be a one Note For some early versions of the 200 300 Series MVME172 J11 is facto...

Page 265: ...ignment is defined by the following tables ADR SIZ FFFBC01E 8 bits BIT 7 6 5 4 3 2 1 0 NAME 0 0 0 0 0 ROTAT PRI1 PRI0 OPER R R R R R R W R W R W RESET 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R PRI1 PRI0 Priority with one DMA channel at IP sockets a b c d Highest Next Highest Next Lowest Lowest 00 DMA_a DMA_b DMA_c DMA_d 01 DMA_b DMA_c DMA_d DMA_a 10 DMA_c DMA_d DMA_a DMA_b 11 DMA_d DMA_a DMA_b DMA_c PRI1 PR...

Page 266: ...serted until software clears RES Note The MVME172 does not comply with the IP specification regarding reset The MVME172 does not monitor Vcc and assert reset if Vcc is below a certain threshold The IPRESET signal to the IP bus is asserted when the there is a cold power up reset This reset will be asserted until the power supplies are stable ADR SIZ FFFBC01F 8 bits BIT 7 6 5 4 3 2 1 0 NAME 0 0 0 0 ...

Page 267: ...the DMACs interrupts are enabled Multiple DMAC commands can be automatically invoked using the command chaining mode In the command chaining mode a singly linked list of commands is built in local memory and the table address register in the DMAC is programmed with the starting address of the list of commands The DMAC control register 1 is programmed and the DMAC is enabled The DMAC executes comma...

Page 268: ...ning mode is used the list of commands must be in local not IP 32 bit memory and the entries must be aligned to a 16 byte boundary That is the address which is loaded into the DMA table address counter must have bits three through zero set to a zero This is true for the initial value which is loaded by the processor or the subsequent values which are loaded by the command chaining logic If they ar...

Page 269: ...cted then the DMA controller associated with IP_b cannot be used If A_CH1 bit is set in the DMA controller register associated with IP_b and both channel A and B operate in the SDMA mode then the DMA channels associated with IP_a and IP_b can both be used if the data width for channel A and B are set equal This case allows the DMA channel that normally re sponds to IP_b DMAreq_0 pin to respond to ...

Page 270: ...cket Additional information is provided in bit 6 DLBE This bit is cleared when DMAC is enabled DLBE When this bit is set DMAC received a TEA TEA is transfer error acknowledge signal on the MC68060 local bus It indicates that a time out occurred This bit is cleared when DMAC is enabled A DMAC interrupt will be generated if interrupts are enabled CHANI When this bit is set the INTE bit in the DMA Co...

Page 271: ...a logic 1 to this bit clears the DINT status bit DIEN When DIEN is set the interrupt is enabled When DIEN is cleared the interrupt is disabled DINT When this bit is high an interrupt will be generated for a DMAC if the DIEN bit is set to a one The interrupt is at the level programmed in DL2 DL0 The DINT bit is set when one of the following bits are set in the Status Register DLBE IPEND CHANI IPTO ...

Page 272: ...lationships between the DMA channels board architecture which require the initialization of certain bits for each pair of DMA channels before the DEN bits can be set That is if DMA channels a and b are going to be used concurrently DMA Control Register 1 should be initialized for both channels before ether channel is enabled This is also true for DMA channels c and d Refer to the section on the DM...

Page 273: ...register set Note that DMACa register set is always associated with DMA request 0 from Industry Pack a and DMACc register set is always associated with DMA request 0 from Industry Pack c Therefore these bit positions are not defined for these two register sets Refer to the section on the Enable DMA Function for information and restrictions on the operation of A_CH1 and C_CH1 WIDTH1 WIDTH bits spec...

Page 274: ...mation and restrictions on the operation of the ADMA control bit DTBL DMAC operates in the direct mode when this bit is low and it operates in the command chaining mode when this bit is high DHALT When this bit is high DMA halts at the end of a command when DMA is operating in the command chaining mode When this bit is low DMA executes the next command in the list Software must be careful not to c...

Page 275: ... to a one will enable the watchdog time out function for DMA cycles on the IP bus The time out period is fixed at approximately 1 msec If a time out does occur the IP bus cycle is terminated and the IPTO bit is set in the DMA Status Register Note that the IndustryPack interface in the IP2 chip ASIC will wait indefinitely if the ENTO bit is cleared and a DMA cycle on the IP bus is not acknowledged ...

Page 276: ...ode and it is only modified when DMA loads its control register from the control word in the command packet When this bit in the command packets is set an interrupt is sent to the local bus interrupter when the command in the packet has been executed The local bus is interrupted if DMA s interrupt is enabled DMA Local Bus Address Counter In the direct mode this counter is programmed with the start...

Page 277: ... this chapter The registers which control IP_c and IP_d are not used on the 200 300 Series MVME172 Note For sDMA operations the IndustryPack Counter must be cleared before the DMAC is enabled DMA Byte Counter In the direct mode this counter is programmed with the number of bytes of data to be transferred For sDMA operations if the port width is 16 bits then the byte count must be initialized to an...

Page 278: ...o a zero If the Table Address Counter is initialized with a value where the four least significant bits are not a zero the logic will interpret it as a halt condition and the command chaining process will not start Therefore the entry in the last command packet which is loaded into the Table Address Counter should have one or more of these address bits set to a one to halt the command chaining pro...

Page 279: ...iting a logic 1 to this bit clears the INT status bit This bit always reads as 0 IEN When IEN is set the programmable clock interrupt is enabled When IEN is cleared the interrupt is disabled INT When this bit is high an interrupt is being generated for the programmable clock at the level programmed in IL2 IL0 IRE This bit controls which action of the programmable clock output causes interrupts ADR...

Page 280: ...errupt and general control registers to zero These registers include the pre scaler and timer counters Note that these registers will remain cleared until the CLR bit is set to a zero EN When the EN bit is set the programmable clock is enabled When it is cleared the programmable clock is suspended EN performs its function by ADR SIZ FFFBC081 8 bits BIT 7 6 5 4 3 2 1 0 NAME PLTY PLS 0 EN CLR PS2 PS...

Page 281: ...mer counter increments until it matches the value contained in this register at which time it rolls over and resumes counting The effect is that the frequency of the programmable clock output is the frequency of the pre scaler output the value in this register 1 For example if the PLS bit is cleared PLS2 0 are 000 and the timer register contains 0001 then the programmable clock output frequency is...

Page 282: ...AD 15 0 IPBD 15 0 during the select state these only apply to memory accesses IPA 6 1 is the value on signal pins IPA 6 1 and IPA 0 is the value inferred by IPBS1 where IPA 0 is 0 if IPBS1 is asserted and 1 if IPBS1 is negated 8 Bit Memory Space This example is for IP_a where the IP_a memory space is programmed with a base address of 00000000 a size of 4MB and a port width of 8 bits The relationsh...

Page 283: ... IP_a memory space is programmed with a base address of 00000000 a size of 8MB and a port width of 16 bits The relationship of the IndustryPack address to the local bus address is IPA LBA LBA IPA Comments 00000000 000000 00000001 000001 00000002 000002 00000003 000003 007FFFFC 7FFFFC 007FFFFD 7FFFFD 007FFFFE 7FFFFE 007FFFFF 7FFFFF ...

Page 284: ...ionship of the IndustryPack address to the local bus address is IPA 22 1 LBA 23 2 and IPA 0 LBA 0 LBA IPA Comments 00000000 000000 IP_b or ab 00000001 000001 IP_b 00000002 000000 IP_a 00000003 000001 IP_a 00000004 000002 IP_b or ab 00000005 000003 IP_b 00000006 000002 IP_a 00000007 000003 IP_a 00000008 000004 IP_b or ab 00FFFFFB 7FFFFD IP_a 00FFFFFC 7FFFFE IP_b or ab 00FFFFFD 7FFFFF IP_b 00FFFFFE ...

Page 285: ...or IP_a I O space The relationship of the IndustryPack address to the local bus address is IPA 6 0 LBA 6 0 Note that IPA 22 7 do not pertain to I O space LBA IPA 6 0 Comments FFF58000 0000000 FFF58001 0000001 FFF58002 0000010 FFF58003 0000011 FFF5807C 1111100 FFF5807D 1111101 FFF5807E 1111110 FFF5807F 1111111 ...

Page 286: ...ess to the local bus address is IPA 6 1 LBA 7 2 and IPA 0 LBA 0 Note that IPA 22 7 do not pertain to I O space LBA IPA 6 0 Comments FFF58400 000000 IP_b or ab FFF58401 000001 IP_b FFF58402 000000 IP_a FFF58403 000001 IP_a FFF58404 000010 IP_b or ab FFF58405 000011 IP_b FFF584FC 111110 IP_b or ab FFF584FD 111111 IP_b FFF584FE 111110 IP_a FFF584FF 111111 IP_a ...

Page 287: ...is for IP_a ID space The relationship of the IndustryPack address to the local bus address is IPA 5 0 LBA 5 0 Note that IPA 22 6 do not pertain to ID space LBA IPA 5 0 Comments FFF58080 000000 FFF58081 000001 FFF58082 000010 FFF58083 000011 FFF580BC 111100 FFF580BD 111101 FFF580BE 111110 FFF580BF 111111 ...

Page 288: ...refers to local bus address signals 1 and 0 LD refers to the local data bus IPA refers to IndustryPack address signals 2 1 0 The IP2 chip implements dynamic bus sizing for memory space accesses whose local bus size is greater than the port width of the IndustryPack that is being accessed Because of this the IP2 chip performs 1 2 or 4 IP memory space cycles for each local bus cycle The IPA column i...

Page 289: ...XD 7 0 5 7 IPXD 7 0 IPXD 7 0 LWORD 0 1 3 5 7 IPXD 7 0 IPXD 7 0 IPXD 7 0 IPXD 7 0 16 Bits BYTE 0 0 IPXD 15 8 1 1 IPXD 7 0 2 2 IPXD 15 8 3 3 IPXD 7 0 WORD 0 2 0 IPXD 15 8 IPXD 7 0 2 IPXD 15 8 IPXD 7 0 LWORD 0 0 2 IPXD 15 8 IPXD 7 0 IPXD 15 8 IPXD 7 0 32 Bits BYTE 0 0 IPBD 15 8 1 1 IPBD 7 0 2 0 IPAD 15 8 3 1 IPAD 7 0 WORD 0 2 0 IPBD 15 8 IPBD 7 0 0 IPAD 15 8 IPAD 7 0 LWORD 0 0 IPBD 15 8 IPBD 7 0 IPAD...

Page 290: ...efers to the local data bus IPXD refers to the IP_a data bus IPAD when accessing IP_a or IP_c It refers to the IP_b data bus IPBD when accessing IP_b or IP_d SPACE LBSIZE LBA IPA LD 31 24 LD 23 16 LD 15 8 LD 7 0 IP_a b c or _d I O or ID BYTE 0 0 IPXD 15 8 1 1 IPXD 7 0 2 2 IPXD 15 8 3 3 IPXD 7 0 WORD 0 2 0 IPXD 15 8 IPXD 7 0 2 IPXD 15 8 IPXD 7 0 LWORD 0 0 IPXD 15 8 IPXD 7 0 IP_ab or _cd I O Only BY...

Page 291: ... accesses sustained for burst writes Allows 4 1 1 1 memory accesses sustained for burst reads 5 1 1 1 with BERR on or when FSTRD is cleared Supports byte two byte four byte and cache line read or write transfers Programmable base address for DRAM Built in refresh timer and refresh controller ECC Single Bit Error Detect and Correct Software enabled Interrupt on Single Bit Error Address and Syndrome...

Page 292: ...finds a single bit error in the memory array it corrects it This prevents soft single bit errors from becoming double bit errors Performance The MCECC pair is specifically designed to provide maximum performance for cache line burst cycles to and from the MC68060 bus This is done by providing a four way interleave between the 32 bit MC68060 data bus and the 128 bit 144 with check bits DRAM This pe...

Page 293: ... caching scheme on the local bus by always providing 32 bits of valid data during DRAM read cycles regardless of the number of bytes requested by the local bus master for the cycle It also supports cache coherency by monitoring the snoop control signal lines on the local bus and behaving appropriately based on their value When the snoop control signal lines SC1 SC0 indicate that snooping is inhibi...

Page 294: ... asserts TA or TEA before MI is negated then the MCECC pair never starts the DRAM read cycle For a write cycle the MCECC pair always waits for MI to be negated before it begins a write cycle to the DRAM If another local bus slave asserts TA or TEA before MI is negated then the MCECC pair never starts the DRAM write cycle ECC The MCECC pair performs single bit error correction and double bit error ...

Page 295: ...s taken by the MCECC pair for different error situations Single Bit Error Cycle Type Burst Read or Non Burst Read Correct the Data that is driven to the local MC68060 bus Do not correct the Data in DRAM Note that the DRAM is not corrected until the next scrub of that address which happens only if scrubbing is enabled Terminate the cycle normally Assert TA to the local bus Log the error if one has ...

Page 296: ...to the local bus Log the error if one has not already been logged Notify the local MPU via interrupt if so enabled Double Bit Error Cycle Type Non Burst Write Do not perform the write portion of the cycle This causes the location to continue to indicate non correctable error when accessed Terminate the cycle normally Assert TA to the local bus Log the error if one has not already been logged Notif...

Page 297: ...is connected it freezes the address of the error and the syndrome bits associated with the data that is in error Each MCECC performs this logging function independently of the other Once an MCECC has logged an error it does not log any new errors that occur until the ERRLOG control status bit has been cleared by software Scrub The MCECC pair contains programmable registers and circuitry that provi...

Page 298: ...requests and provides grants to the requesting entities as follows Priority is highest to lowest refresher local bus and scrubber When no requests are pending the arbiter defaults to providing a local bus grant for fast response to local bus cycles Although the arbiter operates on a priority basis it also performs a pseudo round robin algorithm in order to prevent starving any of the requesting en...

Page 299: ...the values that are written to the CSRs in the upper MCECC the one that connects to D16 D31 to the lower MCECC the one that connects to D0 D15 Hence Software only needs to write to the control registers in the upper MCECC This duplicating function can be disabled by software for test purposes Some effort has gone into making the register map for the first eight registers of the MCECC pair look as ...

Page 300: ...hould only perform read and write cycles to the control and status registers in the upper MCECC Hardware takes care of duplicating the information to the lower MCECC The following descriptions show the upper MCECC bit positions Upper MCECC bit positions 31 24 correspond to lower MCECC bit positions 15 8 The base address of the CSRs is hard coded to the address FFF43000 for the MCECC pair on the fi...

Page 301: ...yndrome registers These registers contain information specific to each MCECC and the DRAMs which it controls and as such should be treated separately The base address of the CSRs is hard coded to the address FFF43000 for the MCECC pair on the first mezzanine board and FFF43100 for the MCECC pair on the second mezzanine board 10 DUMMY 1 0 0 0 0 0 0 0 0 14 BASE ADDRESS BAD31 BAD30 BAD29 BAD28 BAD27 ...

Page 302: ...10 SBPD9 SBPD8 2C SCRUB PERIOD SBPD7 SBPD6 SBPD5 SBPD4 SBPD3 SBPD2 SBPD1 SBPD07 30 CHIP PRESCALE CPS7 CPS6 CPS5 CPS4 CPS3 CPS2 CPS1 CPS0 34 SCRUB TIME ON OFF SRDIS 0 STON2 STON1 STON0 STOFF2 STOFF1 SRDIS 38 SCRUB PRESCALE 0 0 SPS21 SPS20 SPS19 SPS18 SPS17 SPS16 3C SCRUB PRESCALE SPS15 SPS14 SPS13 SPS12 SPS11 SPS10 SPS9 SPS85 40 SCRUB PRESCALE SPS7 SPS6 SPS5 SPS4 SPS3 SPS2 SPS1 SPS0 44 SCRUB TIMER ...

Page 303: ... SBE 60 ERROR ADDRESS EA31 EA30 EA29 EA28 EA27 EA26 EA25 EA24 64 ERROR ADDRESS EA23 EA22 EA21 EA20 EA19 EA18 EA17 EA16 68 ERROR ADDRESS EA15 EA14 EA13 EA12 EA11 EA10 EA9 EA8 6C ERROR ADDRESS EA7 EA6 EA5 EA4 07 0 0 0 70 ERROR SYNDROME S7 S6 S5 S4 S3 S2 S1 S0 74 DEFAULTS1 WRHDIS STATCOL FSTRD SELI1 SELI0 RSIZ2 RSIZ1 RSIZ0 78 DEFAULTS2 FRC_OPN XY_FLIP REFDIS TVECT NOCACHE RESST2 RESST1 RESST0 Table 5...

Page 304: ...80 for MEMC040 value 81 for MCECC Chip Revision Register The Chip Revision Register is hard wired to reflect the revision level of the MCECC ASIC The current value of this register is 00 Writes to this register are ignored however the MCECC pair always terminates the cycles properly with TA Difference from MEMC040 none between corresponding revisions of the two parts ADR SIZ 1st FFF43000 2nd FFF43...

Page 305: ...zed by the reset serial bit stream on the MCECC ADR SIZ 1st FFF43008 2nd FFF43108 8 bits BIT 31 30 29 28 27 26 25 24 NAME 0 0 FSTRD RB4 RB3 MSIZ2 MSIZ1 MSIZ0 OPER R R R R R R R R RESET X X X X X X X X MSIZ2 MSIZ1 MSIZ0 Memory Size 0 0 0 4MB using one 144 bit wide block of 256Kx4 DRAMs 0 0 1 8MB using two 144 bit wide block of 256Kx4 DRAMs 0 1 0 16MB using one 144 bit wide block of 1Mx4 DRAMs 0 1 1...

Page 306: ...this bit indicates that DRAM reads are operating at full speed When 0 it indicates that DRAM read accesses are slowed by one clock cycle to accommodate slower DRAM devices Difference from MEMC040 NONE except that it is an input pin on the MEMC040 while it is a register bit that is initialized by the reset serial bit stream on the MCECC Dummy Register 0 Dummy Register 0 is hard wired to all zeros W...

Page 307: ...s in Register 7 the next register to form BAD31 BAD22 which defines the base address of the memory For larger memory sizes the lower significant bits are ignored Difference from MEMC040 none The bit assignments for the Base Address Register are ADR SIZ 1st FFF43010 2nd FFF43110 8 bits BIT 31 30 29 28 27 26 25 24 NAME 0 0 0 0 0 0 0 0 OPER R R R R R R R R RESET X X X X X X X X ADR SIZ 1st FFF43014 2...

Page 308: ...EBEN causes DRAM accesses to be delayed by one clock This delay is incurred when the access is a local bus or scrub read and the FSTRD bit is set Difference from MEMC040 bit PAREN for MEMC040 bit NCEBEN for MCECC both accomplish basically the same thing enabling TEA assertion for non correctable errors NCEIEN When NCEIEN is set the logging of a non correctable error causes the INT signal pin to pu...

Page 309: ...sserted before starting a DRAM cycle in response to a local bus cycle to DRAM that has LOCKL asserted Clearing the SWAIT bit causes the MCECC pair to start a DRAM read even before LOCKOK is asserted during a local bus cycle that has LOCKL asserted As with MI the MCECC pair still waits for LOCKOK to be asserted before enabling its data onto the local data bus and asserting TA TEA SWAIT should norma...

Page 310: ...egister to control the Prescaler Counter The Prescaler Counter increments to FF and then it is loaded with the two s compliment of the value in the BCLK Frequency Register This produces a 1 MHz clock that is used by the refresh timer and the scrubber When the BCLK Frequency Register is correctly programmed with the BCLK frequency the DRAMs are refreshed approximately once every 15 6 microseconds A...

Page 311: ...ets a chance to check for the single bit error at that location This can be avoided by disabling scrubbing and making sure that all previous scrubs have completed before performing the test Also note that writing bad checkbits can set the ERRLOG bit in the Error Logger Register The writing of checkbits causes the MCECC to perform a read modify write to DRAM If the location to which check bits are ...

Page 312: ... cycle or scrub cycle It is intended to be used with the zero fill function Refer to the section on Initialization at the end of this chapter This bit should be cleared for normal system operation DERC DISABLE ERROR CORRECTION when set to one disables the MCECC from correcting single bit errors Specifically read data is presented to the local MC68060 data bus unaltered from the DRAM array Less tha...

Page 313: ...il software sets the SCRBEN bit If software has not cleared the SCRBEN bit then when the amount of time indicated in the Scrub Period SBPD Register expires the MCECC scrubs the DRAM array again It continues to perform scrubs of the entire DRAM array at the frequency indicated in the SBPD Register The scrubber does not start a new scrub once the SCRBEN bit is cleared The time between scrubs is appr...

Page 314: ...the value programmed into the Scrub Period Register The scrub period can be programmed from once every four seconds to once every 36 hours This register contains bits 15 8 of the Scrub Period Register Scrub Period Register Bits 7 0 This register contains bits 7 0 of the Scrub Period Register ADR SIZ 1st FFF43028 2nd FFF43128 8 bits BIT 31 30 29 28 27 26 25 24 NAME SBPD15 SBPD14 SBPD13 SBPD12 SBPD1...

Page 315: ... Time Off Register STOFF2 STOFF0 STOFF2 STOFF0 control the amount of time that the scrubber refrains from requesting use of the DRAM each time it gives it up during a scrub They control the off time as follows ADR SIZ 1st FFF43030 2nd FFF43130 8 bits BIT 31 30 29 28 27 26 25 24 NAME CPS7 CPS6 CPS57 CPS4 CPS3 CPS2 CPS1 CPS0 OPER R W R W R W R W R W R W R W R W RESET 0 P 0 P 0 P 0 P 0 P 0 P 0 P 0 P ...

Page 316: ...CLK cycles 0 1 0 Request DRAM after 32 BCLK cycles 0 1 1 Request DRAM after 64 BCLK cycles 1 0 0 Request DRAM after 128 BCLK cycles 1 0 1 Request DRAM after 256 BCLK cycles 1 1 0 Request DRAM after 512 BCLK cycles 1 1 1 Request DRAM never STON2 STON1 STON0 Scrubber Time On 0 0 0 Keep DRAM for 1 memory cycle 0 0 1 Keep DRAM for 16 BCLK cycles 0 1 0 Keep DRAM for 32 BCLK cycles 0 1 1 Keep DRAM for 6...

Page 317: ...rocess Scrub Prescaler Counter Bits 21 16 The Scrub Prescaler Counter uses the 1MHz clock as an input to create the 5 Hz clock that is used for the scrub period Writes to this address update the scrub prescaler Reads to this address yield the value in the scrub prescaler The ability to read and write to the scrub prescaler is provided for test purposes Programming this counter is not recommended T...

Page 318: ...ter at which time it clears and resumes incrementing Writes to this address update the Scrub Timer Counter reads to this address yield its value The ability to read and write this register is provided for test purposes Programming this counter is not recommended This register reflects the current value in the Scrub Timer Counter bits 15 8 ADR SIZ 1st FFF4303C 2nd FFF4313C 8 bits BIT 31 30 29 28 27...

Page 319: ...d the value in the Scrub Address Counter The ability to read and write this counter is provided for test purposes Note that if scrubbing is in process the Scrub Time On Time Off Register should be set for the minimum time on and the maximum time off during any writes to this register This register reflects the current value in the Scrub Address Counter bits 26 24 ADR SIZ 1st FFF43044 2nd FFF43144 ...

Page 320: ...27 26 25 24 NAME 0 0 0 0 0 SAC26 SAC25 SAC24 OPER R W R W R W R W R W R W R W R W RESET X X X X X 0 PLS 0 PLS 0 PLS ADR SIZ 1st FFF43050 2nd FFF43150 8 bits BIT 31 30 29 28 27 26 25 24 NAME SAC23 SAC22 SAC21 SAC20 SAC19 SAC18 SAC17 SAC16 OPER R W R W R W R W R W R W R W R W RESET 0 PLS 0 PLS 0 PLS 0 PLS 0 PLS 0 PLS 0 PLS 0 PLS ADR SIZ 1st FFF43054 2nd FFF43154 8 bits BIT 31 30 29 28 27 26 25 24 NA...

Page 321: ...TIPLE BIT ERROR is set when the last error logged was due to a multiple bit error It is cleared when a 1 is written to the ERRLOG bit The syndrome code is meaningless if MBE is set ERA This bit provides status for a function that is not currently used in the MCECC ADR SIZ 1st FFF43058 2nd FFF43158 8 bits BIT 31 30 29 28 27 26 25 24 NAME SAC7 SAC6 SAC5 SAC4 0 0 0 0 OPER R W R W R W R W R R R R RESE...

Page 322: ...RRLOG When set ERRLOG indicates that a single or a double bit error has been logged by this MCECC and that no more is logged until it is cleared The bit can only be set by logging an error and cleared by writing a one to it When ERRLOG is cleared the MCECC is ready to log a new error Note that because hardware duplicates control register writes to both MCECCs clearing ERRLOG in one MCECC clears it...

Page 323: ...t was on bits 7 4 of the local MC68060 bus at the last logging of an error ADR SIZ 1st FFF43064 2nd FFF43164 8 bits BIT 31 30 29 28 27 26 25 24 NAME EA23 EA22 EA21 EA20 EA19 EA18 EA17 EA16 OPER R R R R R R R R RESET 0 PLS 0 PLS 0 PLS 0 PLS 0 PLS 0 PLS 0 PLS 0 PLS ADR SIZ 1st FFF43068 2nd FFF43168 8 bits BIT 31 30 29 28 27 26 25 24 NAME EA15 EA14 EA13 EA12 EA11 EA10 EA9 EA8 OPER R R R R R R R R RES...

Page 324: ...s Register 1 It is not recommended that non test software write to this register RSIZ2 RSIZ0 RSIZ2 RSIZ0 determine the size of the DRAM array that is assumed by the MCECC They control the size as follows ADR SIZ 1st FFF43070 2nd FFF43170 16 bits BIT 31 30 29 28 27 26 25 24 NAME S7 S6 S5 S4 S3 S2 S1 S0 OPER R R R R R R R R RESET 0 PLS 0 PLS 0 PLS 0 PLS 0 PLS 0 PLS 0 PLS 0 PLS ADR SIZ 1st FFF43074 2...

Page 325: ...ream FSTRD The FSTRD control bit determines the speed at which DRAM reads occur When it is 1 DRAM reads happen at full speed When it is 0 DRAM reads are slowed by one RSIZ2 RSIZ1 RSIZ0 DRAM Array Size 0 0 0 4MB using one 144 bit wide block of 256Kx4 DRAMs 0 0 1 8MB using two 144 bit wide blocks of 256Kx4 DRAMs 0 1 0 16MB using one 144 bit wide block of 1Mx4 DRAMs 0 1 1 32MB using two 144 bit wide ...

Page 326: ...ch the value of the STATCOL bit in the reset serial bit stream WRHDIS This bit controls a function that is not currently used in the MCECC Defaults Register 2 It is not recommended that non test software write to this register RESST2 RESST0 These general purpose read write bits are initialized by power up soft or local reset to match the RESST2 RESST0 bits from the reset serial bit stream NOCACHE ...

Page 327: ...the opposite internal set of cache latches is selected This bit should be used with caution and is for test vector coverage improvement FRC_OPN When FRC_OPN is set the internal DRAM read latches are forced continuously open This bit should be used with caution and is for test vector coverage improvement Initialization Most DRAM vendors require that the DRAMs be subjected to some number of access c...

Page 328: ...ub Time On Time Off Register for the maximum rate and to do write cycles by setting the SRDIS bit setting all of the STON bits and clearing all of the STOFF bits Write B8 to offset 34 7 Enable scrubbing by setting the SCRBEN bit in the Scrub Control Register Set bit 27 of offset 24 8 Ensure that the zero fill has started by waiting for the SCRB bit in the Scrub Control Register to be set Wait for ...

Page 329: ...t BANK A corresponds to A3 A2 00 BANK B to A3 A2 01 BANK C to A3 A2 10 and BANK D to A3 A2 11 Bank in Error Bit in Error Syndrome Code BANK D BIT 0 16 8C BANK D BIT 1 17 0D BANK D BIT 2 18 0E BANK D BIT 3 19 F4 BANK D BIT 4 20 15 BANK D BIT 5 21 16 BANK D BIT 6 22 26 BANK D BIT 7 23 25 BANK D BIT 8 24 19 BANK D BIT 9 25 1A BANK D BIT 10 26 1C BANK D BIT 11 27 E9 BANK D BIT 12 28 2A BANK D BIT 13 2...

Page 330: ... 9 25 86 BANK C BIT 10 26 07 BANK C BIT 11 27 7A BANK C BIT 12 28 8A BANK C BIT 13 29 0B BANK C BIT 14 30 13 BANK C BIT 15 31 92 Bank in Error Bit in Error Syndrome Code BANK B BIT 0 16 C8 BANK B BIT 1 17 D0 BANK B BIT 2 18 E0 BA3K B BIT 3 19 4F BANK B BIT 4 20 51 BANK B BIT 5 21 61 BANK B BIT 6 22 62 BANK B BIT 7 23 52 BANK B BIT 8 24 91 BANK B BIT 9 25 A1 BANK B BIT 10 26 C1 BANK B BIT 11 27 9E ...

Page 331: ...4 BANK A BIT 8 24 64 BANK A BIT 9 25 68 BANK A BIT 10 26 70 BANK A BIT 11 27 A7 BANK A BIT 12 28 A8 BANK A BIT 13 29 B0 BANK A BIT 14 30 31 BANK A BIT 15 31 29 Bank in Error Bit in Error Syndrome Code UPPER LOWER CHECKBITS BIT 0 01 UPPER LOWER CHECKBITS BIT 1 02 UPPER LOWER CHECKBITS BIT 2 04 UPPER LOWER CHECKBITS BIT 3 08 UPPER LOWER CHECKBITS BIT 4 10 UPPER LOWER CHECKBITS BIT 5 20 UPPER LOWER C...

Page 332: ...5 42 Computer Group Literature Center Web Site MCECC 5 ...

Page 333: ... Center via phone or fax at the numbers listed under Product Literature at MCG s World Wide Web site Table A 1 Motorola Computer Group Documents Document Title Motorola Publication Number MVME172 VME Embedded Controller Installation and Use VME172LXA IH 400 500 Series MVME172 VME Embedded Controller Installation and Use VME172FXA IH MVME172Bug Diagnostics Manual V172DIAA UM Debugging Package for M...

Page 334: ... edition of the manual Manufacturers Documents For additional information refer to the following table for manufacturers data sheets or user s manuals and related specifications As an additional help a source for the listed document is also provided Please note that in many cases the information is preliminary and the revision levels of the documents are subject to change without notice Table A 2 ...

Page 335: ... Data Interchange EIA 232 D Electronic Industries Association Engineering Department 2001 Eye Street N W Washington D C 20006 ANSI EIA 232 D Standard VME64 Specification IndustryPack Logic Interface Specification Revision 1 0 VITA VMEbus International Trade Association 7825 E Gelding Drive Suite 104 Scottsdale AZ 85260 3415 ANSI VITA 1 1994 ANSI VITA 4 1995 Versatile Backplane Bus VMEbus The Insti...

Page 336: ...A 4 Related Documentation A ...

Page 337: ... up Tick Timer Step Register and Address Action and Reference 1 Prescaler Control Register FFF4004C If not already initialized by the debugger initialize as follows Prescaler Register 256 Bclock MHz This gives a 1 MHz clock to the tick timers Bclock is the bus clock rate such as 25 MHz 256 25 E7 2 Tick Timer 1 Compare Register FFF40050 For periodic interrupts set the Compare Register value Period ...

Page 338: ...ference 5 Vector Base Register FFF40088 8 of 32 bits If not already initialized by the debugger set interrupt base register 0 by writing to bits 28 31 Refer to the Vector Base Register description and to Table 2 3 Local Bus Interrupter Summary in Chapter 2 6 Interrupt Level Register 1 bits 0 7 FFF40078 8 of 32 bits Write desired level of Tick Timer 1 interrupt to bits 0 2 7 Local Bus Interrupter E...

Page 339: ... in Chapter 2 from which you can determine the actual interrupt vector given on a Tick Timer 1 interrupt Lower the MC68060 mask so the interrupt level you programmed is accepted The interrupt handler itself should include the following steps 2 through 5 2 Confirm the Tick Timer 1 interrupt occurred by reading the status of bit 24 of the Interrupter Status Register at FFF40068 A high indicates an i...

Page 340: ...VMEchip2 Tick Timer 1 Periodic Interrupt Example B 4 Computer Group Literature Center Web Site B ...

Page 341: ...ter VMEbus 2 13 address modifier 2 32 2 35 select bits 2 33 2 36 address modifier codes 2 43 2 44 2 59 address modifier register 2 38 address range devices 1 9 local bus 2 39 address space decoding 1 12 address translation registers 2 27 2 38 address translation select register 2 27 2 38 addressing capabilities 2 4 2 9 2 11 addressing local bus to IP 4 46 alternate address register 2 10 arbiter ti...

Page 342: ...1 Chip ID Register 5 14 Chip ID Register IP2 chip 4 17 Chip Prescaler Counter 5 25 Chip Revision Register 5 14 Chip Revision Register IP2 chip 4 17 clear on compare mode 2 15 clock programming IP2 chip 4 43 clocks VMEchip2 counters and timers 2 68 command chaining mode DMAC 2 12 2 52 command packets DMAC 2 53 configuration bytes data structure 1 43 cycle type burst write 5 6 cycle types 5 4 D data...

Page 343: ...Error Interrupt Control Register 3 22 performance 3 6 size control bit encoding 3 27 3 28 Space Base Address Register 3 25 Space Size Register 3 26 DRAM SRAM Options Register 3 27 DTACK 2 9 Dummy Register 0 5 16 Dummy Register 1 5 17 DWB pin 2 8 E ECC 5 4 edge sensitive interrupters 2 18 edge sensitive interrupts 2 75 ending address register 2 27 2 38 EPROM socket 1 3 EPROM Flash interface 3 2 EPR...

Page 344: ...gramming 2 103 GCSR VMEchip2 2 20 2 101 General Control Registers IP2 chip 4 24 general description IP2 chip 4 2 MCECC 5 2 General Purpose I O pins 2 97 Inputs Register 3 33 Readable Jumpers Header 1 5 Register 0 2 108 Register 1 2 108 Register 2 2 109 Register 3 2 109 Register 4 2 110 Register 5 2 110 general purpose registers 2 102 Global Control and Status Registers GCSR 2 20 2 101 global reset...

Page 345: ...72 1 1 VMEchip2 2 1 IP Clock Register IP2 chip 4 28 IP RESET Register IP2 chip 4 30 IP to local bus data routing 4 52 IP_a IP_ab Memory Base Address Registers 4 20 IP_b Memory Base Address Registers 4 20 IP_c IP_cd Memory Base Address Registers 4 21 IP_d Memory Base Address Registers 4 21 IP2 chip 4 1 Control and Status Registers memory map 1 29 features 4 1 functional description 4 2 introduction...

Page 346: ... 2 41 Starting Address Register 1 2 40 Starting Address Register 2 2 40 Starting Address Register 3 2 41 Starting Address Register 4 2 42 local bus timer 3 8 local bus to IndustryPack addressing 4 46 local bus to VMEbus DMA controller VMEchip2 2 10 Enable Control Register 2 49 I O Control Register 2 50 interface 1 9 2 4 interface VMEchip2 2 4 map decoders programming 2 37 requester 2 7 requester r...

Page 347: ... 5 10 SCSI 1 39 time of day clock 1 42 VMEbus 1 46 VMEchip2 GCSR 1 26 2 104 VMEchip2 LCSR 1 22 2 22 Z85230 SCC register 1 37 memory map of the MC2 chip registers 3 8 memory mezzanine board serial number 1 45 Memory Size Registers IP2 chip 4 21 memory space 16 bit IP_a 4 47 32 bit IP_ab 4 48 8 bit IP_a 4 46 memory space accesses IP 4 52 microprocessor 1 3 MIEN 2 75 2 97 3 12 Miscellaneous Control R...

Page 348: ...Echip2 GCSR 2 101 VMEchip2 LCSR 2 20 programming the DMA controllers 4 31 programming the programmable clock 4 43 programming the tick timers 3 15 PROM Access Time Control Register 3 39 PROM Decoder SRAM and DMA Control Register 2 54 PROM EPROM sockets 1 3 PROM Flash interface 3 2 PWB number 1 45 R redundant functions VMEchip2 MC2 chip 1 8 refresh 5 8 register definitions LCSR 2 20 registers local...

Page 349: ...31 slave map decoder registers 2 26 slave map decoders VMEbus 2 26 snoop 2 34 snoop control 4 2 snoop control bits 2 54 snoop control register 2 32 snoop enable 2 28 2 32 2 35 snoop signal lines 2 58 snooping definition 1 48 2 10 software 7 0 interrupters 2 19 software interrupts 1 3 software support considerations 1 47 specifications 1 4 MCECC 5 3 speed board 1 44 SRAM 1 3 memory controller 3 5 s...

Page 350: ...2 66 time of day clock 1 3 memory map 1 40 1 42 time out local bus 1 48 period 2 17 VMEbus access 1 49 time out period watchdog 2 67 timers 1 3 timers VMEbus 2 7 transfer mode VMEbus 2 12 Transfer Type TT signals 1 9 transition boards 1 2 triple or greater bit error cycle type burst read or non burst read 5 6 cycle type non burst write 5 6 cycle type scrub 5 7 V V11 control bit MC2 chip 1 11 3 34 ...

Page 351: ... Control Register 2 2 32 VMEbus system controller VMEchip2 2 17 VMEbus timer 2 18 VMEbus to local bus interface 1 9 2 9 VMEchip2 ASIC 1 2 block diagram 2 5 Board Status Control Register 2 107 functional blocks 2 4 GCSR programming model 2 101 ID Register 2 105 introduction 2 1 LM SIG Register 2 105 local BERR 1 49 memory map LCSR Summary 2 22 periodic interrupt example B 1 programming model 2 20 R...

Page 352: ...Index IN 12 Computer Group Literature Center Web Site I N D E X ...

Page 353: ...r s Reference Guide MVME172 Embedded Controller Programmer s Reference Guide 34 pages 1 8 spine 36 84 pages 3 16 1 4 spine 86 100 pages 5 16 spine 102 180 pages 3 8 1 2 spine 182 308 pages 5 8 1 1 8 spine 2 lines allowed ...

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