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A-12

Configure and Environment Commands

A

Master Enable #4 [Y/N]

N

Do not set up and enable the Master 
Address Decoder #4. 

Master Starting Address #4

00000000

Base address of the VMEbus resource 
that is accessible from the local bus. 
This will be the local bus address. 
Default is $0. 

Master Ending Address #4

00000000

Ending address of the VMEbus 
resource that is accessible from the 
local bus. This will be the local bus 
address. Default is $0. 

Master Address Translation 
Address #4

00000000

This register will allow the VMEbus 
address and the local address to be 
different. The value in this register is 
the base address of the VMEbus 
resource that is associated with the 
starting and ending address selection 
from the previous questions. Default 
is $0. 

Master Address Translation Select 
#4

00000000

This register deÞnes which bits of the 
Translation Address are signiÞcant. A 
logical one "1" indicates signiÞcant 
address bits, logical zero "0" is non-
signiÞcant. The non-signiÞcant bits 
will come from the local bus address 
that accesses the VMEbus. Normally, 
MS bits will be set, down to the size of 
memory to be accessed. Default is $0. 

Master Control #4

00

Works the same as Slave Control #1. 
Default is $00. 

Short I/O (VMEbus A16) Enable 
[Y/N]

Y

Yes, Enable the Short I/O Address 
Decoder. 

Short I/O (VMEbus A16) Control

01

Works the same as Slave Control #1. 
Default is $01. 

Table A-1.  ENV Command Parameters (Continued)

ENV Parameter and Options

Default

Meaning of Default

Summary of Contents for MVME167 Series

Page 1: ...MVME167 Single Board Computer Installation Guide MVME167IG D4 ...

Page 2: ...r written permission of Motorola Inc It is possible that this publication may contain reference to or information about Motorola products machines and programs programming or services that are not announced in your country Such references or information must not be construed to mean that Motorola intends to announce such Motorola products programming or services in your country Restricted Rights L...

Page 3: ...s supply additional capability to an existing compatible system or work in a lab environment for experimental purposes Anyone using this manual should have a basic knowledge of computers and digital logic Assembly Item Board Description MVME167 001B 25MHZ 4MB Parity MVME167 002B 25MHZ 8MB Parity MVME167 003B 25MHZ 16MB Parity MVME167 004B 25MHZ 32MB Parity MVME167 031B 33MHZ 4MB ECC MVME167 032B 3...

Page 4: ...l or other qualiÞed maintenance personnel may remove equipment covers for internal subassembly or component replacement or any internal adjustment Do not replace components with power cable connected Under certain conditions dangerous voltages may exist even with the power cable removed To avoid injuries always disconnect power and discharge circuits before touching them Do Not Service or Adjust A...

Page 5: ...All other products mentioned in this document are trademarks or registered trademarks of their respective holders Copyright Motorola 1997 All Rights Reserved Printed in the United States of America March 1997 European Notice Board products with the CE marking comply with the EMC Directive 89 336 EEC Compliance with this directive implies conformity to the following European Norms EN55022 CISPR 22 ...

Page 6: ......

Page 7: ...nal Manuals for this Board 1 6 Other Applicable Motorola Publications 1 6 Non Motorola Peripheral Controllers Publications Bundle 1 7 Applicable Non Motorola Publications 1 8 This Chapter Covers 2 1 General Description 2 1 Onboard Memory Mezzanine Module 2 2 SCSI Mass Storage Interface 2 2 Serial Ports 2 3 Parallel Printer Port 2 3 Ethernet Transceiver Interface 2 3 167Bug Firmware 2 4 Features 2 ...

Page 8: ...rnet Interface 2 21 SCSI Interface 2 22 Local Resources 2 23 Programmable Tick Timers 2 23 Watchdog Timer 2 23 Software Programmable Hardware Interrupts 2 23 Local Bus Timeout 2 23 Memory Maps 2 24 Local Bus Memory Map 2 24 Normal Address Range 2 24 VMEbus Memory Map 2 28 VMEbus Accesses to the Local Bus 2 28 VMEbus Short I O Memory Map 2 28 This Chapter Covers 3 1 Unpacking the Equipment 3 1 Over...

Page 9: ... the System 3 24 Initializing the Real Time Clock 3 24 Examining and or Changing Environmental Parameters 3 24 Programming the PCCchip2 and VMEchip2 3 25 System Considerations 3 26 Backplane Power Connections 3 26 Memory Address Ranges 3 26 DRAM Addressing 3 26 Global Bus Timeout 3 26 Multiple Module Cage Configuration 3 27 GCSR Location Monitor Register 3 27 Ethernet LAN 12 Vdc Fuse 3 27 SCSI Bus...

Page 10: ...put Output Inquiry 4 15 IOP Physical I O to Disk 4 15 IOT I O Teach 4 15 IOC I O Control 4 15 BO Bootstrap Operating System 4 15 BH Bootstrap and Halt 4 16 Disk I O via 167Bug System Calls 4 16 Controller Command Packets 4 16 Default 167Bug Controller and Device Parameters 4 17 Disk I O Error Codes 4 18 Network I O Support 4 19 Intel 82596 LAN Coprocessor Ethernet Driver 4 19 UDP IP Protocol Modul...

Page 11: ... the Program from Disk 5 11 Calling System Utilities from User Programs 5 11 Preserving the Debugger Operating Environment 5 11 167Bug Vector Table and Workspace 5 12 Examples 5 13 Hardware Functions 5 13 Exception Vectors Used by 167Bug 5 13 Example Trace one instruction using debugger 5 15 Exception Vector Tables 5 15 Using 167Bug Target Vector Table 5 15 Creating a New Vector Table 5 16 167Bug ...

Page 12: ...t ConÞgurations B 2 IOT Command Parameters for Supported Floppy Types B 4 Network Controller Modules Supported C 1 Introduction E 1 Levels of Implementation E 3 Signal Adaptations E 4 Sample ConÞgurations E 4 Proper Grounding E 7 ...

Page 13: ...neral Block Diagram 2 7 MVME167 Switches Headers Connectors Fuses and LEDs 3 6 Typical Internal SCSI and Serial Port Connections 3 17 Using MVME712A AM and MVME712B 3 21 Typical Transition Module Peripheral Port Connectors 3 22 ...

Page 14: ...ings for Optional J8 SRAM Backup Power Source Select Header 3 12 MVME167 Preparation Procedure 3 13 Chassis Preparation Slot Selection Procedure 3 14 MVME167 Installation Procedure 3 15 Peripheral Connections 3 18 Transition Module and Adapter Board Installation Overview 3 19 Peripheral Connection Procedures 3 20 Installation Completion Procedure 3 23 System Startup Overview 3 23 RTC Initializatio...

Page 15: ...A general Board Level Hardware Description in Chapter 2 Hardware Preparation and Installation instructions in Chapter 3 Debugger General Information in Chapter 4 Debugger monitor commands and other information about Using the 167Bug Debugger in Chapter 5 Other information needed for startup and troubleshooting of the MVME167 CISC Single Board Computer including Ð Configure and Environment Commands...

Page 16: ...umber twelve and Ò 12Ó is the decimal number eighteen Unless otherwise specified all address references are in hexadecimal Signal Name Conventions An asterisk follows signal names for signals which are level or edge significant dollar speciÞes a hexadecimal character percent speciÞes a binary number ampersand speciÞes a decimal number Term Indicates level signiÞcant The signal is true or valid whe...

Page 17: ...w that they represent Data and Address Size Definitions Data and address sizes are defined as follows Term Indicates Assertion and assert The signal is active or true Negation and negate The signal is inactive or false Name Size Numbered SigniÞcance Called Byte 8 bits 0 through 7 bit 0 is the least signiÞcant byte Two byte 16 bits 0 through 15 bit 0 is the least signiÞcant word Four byte 32 bits 0...

Page 18: ...False Bit State Definitions True and False indicate whether a bit enables or disables the function it controls Bit Value Descriptions In all tables the terms 0 and 1 are used to describe the actual value that should be written to the bit or the value that it yields when read Term Describes Control bit The bit can be set and cleared under software control Status bit The bit reßects a speciÞc condit...

Page 19: ...be furnished along with the particular document Each Motorola Computer Group manual publication number is suffixed with characters which represent the revision level of the document such as Ò D2Ó the second revision of a manual a supplement bears the same number as a manual but has a suffix such as Ò D2A1Ó the first supplement to the second edition of the manual Document Set for MVME167 0xx Board ...

Page 20: ...e UserÕs Manual Motorola Publication Number Description MVME167IG D MVME167 Single Board Computer Installation Guide this manual SIMVME167 D MVME167 Single Board Computer Support Information The SIMVME167 manual contains the connector interconnect signal information parts lists and the schematics for the MVME167 Motorola Publication Number Description MVME712M MVME712M Transition Module and P2 Ada...

Page 21: ...0 SCSI I O Processor ProgrammerÕs Guide CL CD2400 2401 Cirrus Logic CD2401 Serial Controller UserÕs Manual UM95SCC0100 Zilog Z85230 Serial Communications Controller UserÕs Manual 290218 Intel Networking Components Data Manual 290435 Intel i28F008 Flash Memory Data Sheet 290245 Intel i28F020 Flash Memory Data Sheet 292095 Intel i28F008SA Software Drivers Application Note 292099 Intel i28F008SA Auto...

Page 22: ...Documents 15 Inverness Way East Englewood CO 80112 5704 CL CD2400 2401 Four Channel Multi Protocol Communications Controller Data Sheet order number 542400 003 Cirrus Logic Inc 3100 West Warren Ave Fremont CA 94538 82596CA Local Area Network Coprocessor Data Sheet order number 290218 and 82596 User s Manual order number 296853 Intel Corporation Literature Sales P O Box 58130 Santa Clara CA 95052 8...

Page 23: ...cators Memory maps General Description The MVME167 based on the MC68040 microprocessor is a high functionality VMEbus based solution for scientific and industrial embedded controller applications It features Onboard memory expansion mezzanine module with 4 8 16 32 64 or 128 MB of onboard DRAM SCSI bus interface with DMA Four serial ports with EIA 232 D interface Centronics parallel printer port Et...

Page 24: ...64 or 128MB ECC Ð Two mezzanine boards may be stacked to provide 256MB of onboard RAM ECC or 64 MB parity The stacked configuration requires two VMEbus slots The DRAM is four way interleaved to efficiently support cache burst cycles The parity mezzanines are only supported on 25 MHz main boards A functional description of the Onboard DRAM starts on page 2 15 SCSI Mass Storage Interface The MVME167...

Page 25: ...le parallel printer port or as a general parallel I O port A functional description of the Printer Port interface starts on page 2 20 Ethernet Transceiver Interface The Ethernet transceiver interface is located on the MVME167 and the industry standard connector is located on the MVME712X transition module A functional description of the Ethernet Interface starts on page 2 21 Serial Port Function S...

Page 26: ...accepts commands from the system console terminal 167Bug can also operate in a System Mode which includes choices from a service menu Features MC68040 Microprocessor 4 8 16 32 64MB of 32 bit DRAM with parity protection or 4 8 16 32 64 128 256MB of 32 bit DRAM with ECC protection Four 44 pin PLCC ROM sockets organized as two banks of 32 bits 128KB Static RAM with optional battery backup as a factor...

Page 27: ...inter port Ð Ethernet transceiver interface with DMA VMEbus interface Ð VMEbus system controller functions Ð VMEbus interface to local bus A24 A32 D8 D16 D32 and D8 D16 D32 D64BLT BLT Block Transfer Ð Local bus to VMEbus interface A16 A24 A32 D8 D16 D32 Ð VMEbus interrupter Ð VMEbus interrupt handler Ð Global CSR for interprocessor communications Ð DMA for fast local memory VMEbus transfers A16 A2...

Page 28: ...A typical 4 5 A max at 25 MHz with 32MB parity DRAM 5 0 A typical 6 5 A max at 33 MHz with 128MB ECC DRAM 12 Vdc 5 100 mA maximum 1 0 A max with offboard LAN transceiver 12 Vdc 5 100 mA maximum Operating temperature 0û to 55û C at point of entry of forced air approximately 490 LFM Storage temperature 40û to 85û C Relative humidity 5 to 90 non condensing Physical dimensions Double high VMEboard PC ...

Page 29: ...tion to the SCSI bus serial ports Ethernet and printer Adapters I O on the MVME167 is connected to the VMEbus P2 connector The main board is connected to the transition modules through a P2 adapter board and cables Figure 2 1 MVME167 General Block Diagram DRAM EPROM VMEbus bd068 9209 128KB STATIC RAM MK48T08 BBRAM CLOCK PCCchip2 PRINTER PORT MC68040 82596CA LAN ETHERNET 53C710 SCSI CD2401 SCC SERI...

Page 30: ...nual as MVME712X unless separately specified Transition modules and adapter boards are covered in the MVME712M Transition Module and P2 Adapter Board User s Manual and the MVME712 12 MVME712 13 MVME712A MVME712AM and MVME712B Transition Modules and LCP2 Adapter Board User s Manual ASICs The MVME167 board features several Application Specific Integrated Circuits ASICs including VMEchip2 PCCchip2 ME...

Page 31: ...A VMEbus to from local bus non DMA programmed access interface A VMEbus interrupter A VMEbus system controller A VMEbus interrupt handler A VMEbus requester PCCchip2 ASIC The PCCchip2 ASIC provides two tick timers and the interface to the LAN chip SCSI chip Serial port chip Printer port BBRAM Table 2 2 Bus Transfers Transfer type Can be Processor to VMEbus D8 D16 or D32 VMEchip2 DMA to the VMEbus ...

Page 32: ...ry Controller ASIC The MCECC memory controller ASIC provides the programmable interface for the ECC protected DRAM mezzanine board Functional Description The major functional blocks of the MVME167 covered in this section are Front panel switches and LED indicators Data bus structure MC68040 CPU EPROM SRAM Onboard DRAM Battery backed up RAM and clock VMEbus interface I O interfaces Local resources ...

Page 33: ...ED Name Color Description FAIL Red The FAIL LED lights when the BRDFAIL signal line is active STAT Yellow The STAT LED lights when the MC68040 is halted RUN Green The RUN LED lights when the local bus TIP signal line is low This indicates one of the local bus masters is executing a local bus cycle SCON Green The SCON LED lights when the MVME167 is the VMEbus system controller LAN Green The LAN LED...

Page 34: ... lowest is 1 82596CA LAN highest 2 CD2401 serial through the PCCchip2 3 53C710 SCSI 4 VMEbus 5 MPU lowest In general any master can access any slave however not all combinations pass the Òcommon sense testÓ Refer to the Single Board Computers Programmer s Reference Guide and to the user s guide for each device to determine its port size data bus connection and any restrictions that apply when acce...

Page 35: ...local bus reset Ð This allows the MC68040 to access the stack pointer and execution address following a reset Programmable EPROM features Map decoder Access time When accessible at address 0 Static RAM The MVME167 includes 128KB of 32 bit wide 100 ns static RAM SRAM which Supports 8 16 and 32 bit wide accesses Allows the debugger operation and execution of limited diagnostics without the DRAM mezz...

Page 36: ...ust be replaced within 30 seconds If your MVME167 is equipped with SRAM battery backup when the main board power fails the DS1210S selects the battery as the power source Each time the board is powered the DS1210S checks the power source allowing software to provide an early warning to avoid data loss If the voltage of the backup source is less than two volts the second memory access cycle is bloc...

Page 37: ...e Do not heat or incinerate Do not apply solder directly Do not use different models Do not charge Always check proper polarity To remove the battery from the module carefully pull the battery from the socket Data will be lost if a new battery is not installed within 30 seconds Before installing a new battery ensure that the battery pins are clean Note the battery polarity and press the battery in...

Page 38: ...acked configuration requires two VMEboard slots DRAM Programming Considerations The DRAM map decoder can be programmed to accommodate different base address es and sizes of mezzanine boards The onboard DRAM is disabled by a local bus reset and must be programmed before the DRAM can be accessed Most DRAM devices require some number of access cycles before the DRAMs are fully operational Ð Normally ...

Page 39: ...ection 8KB of RAM A battery The clock provides Seconds minutes hours day date month and year in BCD 24 hour format Automatic corrections for 28 29 leap year and 30 day months No interrupts are generated by the clock The MK48T08 is an 8 bit device however the interface provided by the PCCchip2 supports 8 16 and 32 bit accesses to the MK48T08 Refer to the MK48T08 data sheet for detailed programming ...

Page 40: ...ule such as the MVME712X should be used to convert the I O connector pinout to industry standard connectors The I O interface configuration headers are located on the MVME167 and the MVME712X transition module The I O on the MVME167 is connected to the VMEbus P2 connector The MVME712X transition module is connected to the MVME167 through cables and a P2 adapter board Serial Port Interface The CD24...

Page 41: ...gramming Considerations The MVME167 board hardware ties the DTR signal from the CD2401 to the pin labeled RTS at connector P2 Likewise RTS from the CD2401 is tied to DTR on P2 Therefore when programming the CD2401 assert DTR when you want RTS and RTS when you want DTR The interface provided by the PCCchip2 allows the 16 bit CD2401 to appear at contiguous addresses Accesses to the CD2401 must be 8 ...

Page 42: ...t selection In addition to the 8 bits of data there are two control pins and five status pins When used as a parallel printer port these pins function as follows Each of the status pins can generate an interrupt to the MPU in any of the following programmable conditions high level low level high to low transition low to high transition Status Pins Printer Acknowledge ACK Printer Fault FAULT Printe...

Page 43: ...standard connector is located on the MVME712X transition module Every MVME167 is assigned an Ethernet Station Address The address is 08003E2xxxxx where xxxxx is the unique 5 nibble number assigned to the board i e every MVME167 has a different value for xxxxx Each module has the Ethernet Station Address displayed on a label attached to the VMEbus P2 connector In addition the six bytes including th...

Page 44: ...ives streaming tape drives and other mass storage devices The SCSI interface is implemented using the NCR 53C710 SCSI I O controller Support functions for the 53C710 are provided by the PCCchip2 Refer to the 53C710 user s guide for detailed programming information SCSI Termination Because this board has no provision for SCSI termination you must ensure that the SCSI bus is terminated properly If t...

Page 45: ...e programmed time or it times out The watchdog timer can be programmed to generate a SYSRESET signal local reset signal or board fail signal if it times out Software Programmable Hardware Interrupts Eight software programmable hardware interrupts are provided by the VMEchip2 These interrupts allow software to create a hardware interrupt Local Bus Timeout The MVME167 provides a timeout function for...

Page 46: ...edge codes Normal Address Range The memory map of devices that respond to the normal address range is shown in the following tables The normal address range is defined by the Transfer Type TT signals on the local bus On the MVME167 Transfer Types 0 1 and 2 define the normal address range Table 2 5 on page 2 25 is the entire map from 00000000 to FFFFFFFF Many areas of the map are user programmable ...

Page 47: ...s 1 Onboard EPROM appears at 00000000 003FFFFF following a local bus reset The EPROM appears at 0 until the ROM0 bit is cleared in the VMEchip2 The ROM0 bit is located at address FFF40030 bit 20 The EPROM must be disabled at 0 before the DRAM is enabled The VMEchip2 and DRAM map decoders are disabled by a local bus reset 2 This area is user programmable The suggested use is shown in the table The ...

Page 48: ...PCCchip2 D32 D8 4KB 1 FFF43000 FFF430FF MEMC040 MCECC 1 D8 256B 1 FFF43100 FFF431FF MEMC040 MCECC 2 D8 256B 1 FFF43200 FFF43FFF MEMC040s MCECCs repeated 3 5KB 1 6 FFF44000 FFF44FFF reserved 4KB 4 FFF45000 FFF451FF CD2401 Serial Comm Cont D16 D8 512B 1 FFF45200 FFF45DFF reserved 3KB 6 8 FFF45E00 FFF45FFF reserved 512B 8 FFF46000 FFF46FFF 82596CA LAN D32 4KB 1 7 FFF47000 FFF47FFF 53C710 SCSI D32 D8 ...

Page 49: ...he VMEchip2 must be 32 bits LCSR writes of 8 or 16 bits terminate with a TEA signal Writes to the GCSR may be 8 16 or 32 bits Reads to the LCSR and GCSR may be 8 16 or 32 bits 4 This area does not return an acknowledge signal If the local bus timer is enabled the access times out and is terminated by a TEA signal 5 This area does return an acknowledge signal 6 Size is approximate 7 Port commands t...

Page 50: ...Appendix A VMEbus Accesses to the Local Bus The VMEchip2 includes a user p87grammable map decoder for the VMEbus to local bus interface The map decoder allows you to program the starting and ending address and the modifiers the MVME167 responds to VMEbus Short I O Memory Map The VMEchip2 includes a user programmable map decoder for the GCSR The GCSR map decoder allows you to program the starting a...

Page 51: ...als for each model Refer to the userÕs manual you received with your MVME712X Unpacking the Equipment Note If the shipping carton is damaged upon receipt request that the carrier s agent be present during unpacking and inspection of the equipment Unpack the equipment from the shipping carton Refer to the packing list and verify that all items are present Save the packing material for storing and r...

Page 52: ...PROM devices are properly installed in their sockets Checking the 167Bug EPROMs 3 7 ConÞgure adapters and MVME712X transition modules The userÕs manual you received with your MVME712X module Install remove jumpers on headers Jumper Settings 3 7 2 Prepare the chassis Preparing the MVME167 for Installation 3 13 Turn power off to chassis and peripherals The userÕs manual you received with your chassi...

Page 53: ...ing Peripherals 3 19 Connect and install any optional SCSI device cables You may also wish to obtain the Single Board Computer SCSI Software UserÕs Manual Connect a console terminal to the MVME712X Connect any other optional devices or equipment you will be using such as serial or parallel printers host computers etc EIA 232 D Interconnections E 1 Port Numbers 5 9 Disk Tape Controller Data B 1 6 C...

Page 54: ...so wish to obtain the Debugging Package for Motorola 68k CISC CPUs UserÕs Manual and the 167Bug Diagnostics UserÕs Manual Examine and or change environmental parameters Examining and or Changing Environmental Parameters 3 24 Setting Environment to Bug Operating System A 3 Program the PCCchip2 and VMEchip2 Memory Maps 2 24 Troubleshoot the system Troubleshooting the MVME167 Solving Startup Problems...

Page 55: ... option modifications may be necessary before installation The location of the switches jumper headers connectors and LED indicators on the MVME167 is illustrated in Figure 3 1 Option Modification The MVME167 has provisions for option modification via Software control for most options Jumper settings on headers for some options Bit settings in control registers after installation for most other op...

Page 56: ...E P2 A32 B32 C32 A1 B1 C1 19 20 J3 DS1 1 2 STAT FAIL RUN SCON LAN SCSI VME ABORT RESET J2 F2 J8 1 16 2 1 15 12V XU4 SKT 39 40 1 2 29 28 6 7 18 17 XU3 SKT 39 40 1 29 28 6 7 18 17 XU2 39 40 1 29 28 6 7 18 17 XU1 39 40 1 29 28 6 7 18 17 1 1 3 3 J6 J7 COMPONENTS ARE REMOVED FOR CLARITY 60 59 2 1 J4 60 59 2 1 J5 MEZZANINE BOARD DS2 DS3 DS4 2 2 2 1 2 J1 2 3 4 OPTIONAL F1 ...

Page 57: ...ation Be sure that physical chip orientation is correct The flatted corner of each EPROM aligns with the corresponding portion of the EPROM socket on the MVME167 User programmed EPROMs There are two spare EPROM sockets XU3 and XU4 available to carry user programmed EPROMs Jumper Settings The MVME167 has been factory tested and is shipped with the factory jumper settings described in the following ...

Page 58: ...ve TRXC4 and RTXC4 clock signals Optional header J8 selects the SRAM backup power source this is only available as an optional factory build special request General Purpose Software Readable Header J1 Each MVME167 may be configured with readable jumpers They can be read as a register at FFF40088 in the VMEchip2 LCSR The bit values are read as a one when the jumper is off and as a zero when the jum...

Page 59: ... This feature can be used in the event the user setup is corrupted or does not meet a sanity check Refer to the ENV command Appendix A for the ROM defaults This bit will be high when jumper is removed Bit 2 GPI2 5 6 Reserved for future use Bit 3 GPI3 7 8 Reserved for future use Bit 4 GPI4 9 10 Open to your application Bit 5 GPI5 11 12 Open to your application Bit 6 GPI6 13 14 Open to your applicat...

Page 60: ...t 4 can be configured to use clock signals provided by the RTXC4 and TRXC4 signal lines Headers J6 and J7 on the MVME167 configure serial port 4 to drive or receive RTXC4 and TRXC4 respectively see Table 3 5 Factory configuration is with port 4 set to receive both signals The alternative configuration sets port 4 to drive both signals Table 3 4 Settings for J2 System Controller Header Header Numbe...

Page 61: ...M Transition Module and P2 Adapter Board User s Manual for configuration of that header Table 3 5 Settings for J6 and J7 Serial Port 4 Clock Configuration Select Headers Header Number Header Description ConÞguration Jumpers J6 Serial Port 4 clock conÞguration select headers Receive RTXC4 Factory conÞguration Drive RTXC4 J7 Receive TRXC4 Factory conÞguration Drive TRXC4 J6 1 2 3 J6 1 2 3 J7 1 2 3 J...

Page 62: ...l battery backup do not remove the jumper from J8 This will disable the SRAM If your MVME167 contains optional header J8 but the optional battery is removed the jumper must be installed between pins 2 and 4 to disable the backup or between pins 1 and 2 for the factory configuration as shown in Table 3 6 Table 3 6 Settings for Optional J8 SRAM Backup Power Source Select Header Header Number Header ...

Page 63: ...n header J1 affect 167Bug operation as listed in Jumper Settings The default condition is with all eight jumpers installed A jumper installed removed on header J2 enables disables the system controller function of the MVME167 Install jumpers on headers J6 and J7 to configure serial port 4 to use clock signals provided by the TRXC4 and RTXC4 signal lines 2 ConÞgure adapters and transition modules a...

Page 64: ... Chassis Preparation Slot Selection Procedure Step Action 1 Turn all power OFF to chassis and peripherals 2 Disconnect AC power cable from source 3 Remove chassis cover as shown in the user s manual for your particular chassis or system 4 Remove the Þller panel s from the appropriate card slot s at the front and rear of the chassis if the chassis has a rear card cage If the MVME167 is conÞgured as...

Page 65: ...eft most card slot slot 1 otherwise it may be installed in any unused double height card slot Table 3 9 MVME167 Installation Procedure Step Action 1 Remove IACK and BG jumpers from backplane for the card slot that the MVME167 is to be installed in 2 Carefully slide the MVME167 into the card slot in the front of the chassis The MVME167 requires power from both P1 and P2 Be sure the module is seated...

Page 66: ... a double wide front panel MVME712X transition modules provide configuration headers and industry standard connectors for internal and external I O devices The I O on the MVME167 is connected to the VMEbus P2 connector The MVME712X transition module is connected to the MVME167 through cables and a P2 adapter board as shown in Figure 3 2 on page 3 17 Note Some cable s are not provided with the MVME...

Page 67: ...Installing the Hardware 3 17 3 Figure 3 2 Typical Internal SCSI and Serial Port Connections P1 P2 J2 J3 ENCLOSURE BOUNDARY LC P2 P2 TERMINATOR J2 P2 OR J11 MVME167 ADAPTER MVME712X ...

Page 68: ... Through Console terminals host computer systems modems or serial printers EIA 232 D serial ports on the transition module Parallel printers Centronics printer port on the transition module Optional internal modems see the userÕs manual for your transition module for details Optional modem port replacing serial port 2 on the transition module Internal SCSI drives Adapter board and transition modul...

Page 69: ...eed to do Refer to 1 Set jumpers on the transition module s and install SCSI terminators if needed on the P2 adapter board Module Preparation in the userÕs manual for your transition module and adapter board and SCSI Bus Termination on page 3 28 2 Connect and install the MVME712X transition module in the front or the rear of the chassis Installation Instructions in the userÕs manual for your trans...

Page 70: ... After powerup the baud rate of the debug port can be reconÞgured by using the Port Format PF command of the 167Bug debugger 4 Connect devices such as a host computer system and or a serial printer to the other EIA 232 D port connectors with the appropriate cables and conÞguration After powerup these ports can be reconÞgured by programming the MVME167 CD2401 Serial Controller Chip SCC or by using ...

Page 71: ...e CTS line then it must do XON XOFF handshaking If you get garbled messages and missing characters you should check the terminal to make sure XON XOFF handshaking is enabled Refer to Configuring a Port under the PF Port Format command in the Debugging Package for 68K CISC CPUs UserÕs Manual Figure 3 3 Using MVME712A AM and MVME712B P2 P2 J2 J3 P1 ENCLOSURE BOUNDARY MVME712X MVME167 J1 J3 J4 J5 J12...

Page 72: ...Module Peripheral Port Connectors PRINTER MVME 712A 12 13 SERIAL PORT 1 SERIAL PORT 2 SERIAL PORT 3 SERIAL PORT 4 CONSOLE TTY01 MVME ETHERNET 712B SCSI INTERFACE MVME 712B MVME 712A To J10 on Transition Module To J2 on Adapter Board Optional Modem Port if used MVME712M similar ...

Page 73: ... Stage What you will need to do Refer to 1 Power up the system and note that the debugger prompt appears Page 3 24 Starting Up 167Bug on page 4 6 and the MVME167Bug Debugging Package User s Manual 2 Initialize the real time clock Page 3 24 3 Examine and or change environmental parameters Page 3 24 and ConÞgure and Environment Commands on page A 1 4 Program the PCCchip2 and VMEchip2 System Consider...

Page 74: ... required to initialize the RTC depending on the mode Examining and or Changing Environmental Parameters Use the 167BugÕs ENV command to verify the NVRAM BBRAM parameters and optionally use ENV to make changes to the Environmental parameters Refer to Appendix A for the Environment parameters If 167Bug is in Board Mode 167Bug executes some self checks and displays the debugger prompt 167 Bug System...

Page 75: ...REAK key If the system has already started and failed a conÞdence test in system mode you should be in the debugger menu 2 At the 167 Bug prompt enter TIME to display the current date and time of day Select 3 from the debugger menu to get the debugger prompt 3 At the 167 Bug prompt use the SET command to initialize the RTC and to set the time and date Use the following command line structure SET M...

Page 76: ...devices in the system must be handled by the MC68040 software Refer to the memory maps in the Single Board Computer Programmer s Reference Guide as listed in Related Documentation in Chapter 1 DRAM Addressing The MVME167 contains shared onboard DRAM whose base address is software selectable Both the onboard processor and offboard VMEbus devices see this local DRAM at base physical address 00000000...

Page 77: ... accessible from any local processor as well as from the VMEbus Ethernet LAN 12 Vdc Fuse The MVME167 provides 12 Vdc power to the Ethernet LAN transceiver interface through a 1 amp fuse F2 located on the MVME167 The 12V LED lights when 12 Vdc is available The fuse is socketed and is located adjacent to diode CR1 near connector P1 If the Ethernet transceiver fails to operate check the fuse When usi...

Page 78: ...inator power If the LED flickers during SCSI bus operation the fuse should be checked Because this board has no provision for SCSI termination you must ensure that the SCSI bus is terminated properly If you use a P2 adapter the adapter has sockets R1 R2 R3 for terminating the SCSI lines using three 8 pin SIP resistor networks Storage and the Real Time Clock For storage of this product be sure the ...

Page 79: ... Memory requirements Overview of M68000 Firmware The firmware for the M68000 based 68K series of board and system level products has a common genealogy deriving from the BUG firmware currently used on all Motorola M68000 based CPU modules The M68000 firmware family provides a high degree of functionality and user friendliness and yet stresses portability and ease of maintenance This member of the ...

Page 80: ... which accepts commands from the system console terminal Command Facilities Facilities are available for loading and executing user programs under complete operator control for system evaluation 167Bug includes commands for these tasks Display and modification of memory Breakpoint and tracing capabilities A powerful assembler disassembler useful for patching programs A self test at powerup feature...

Page 81: ...iven it performs its various operations in response to user commands entered at the keyboard When you enter a command 167Bug executes the command and the 167 Bug prompt reappears However if you enter a command that causes execution of user target code e g GO then control may or may not return to 167Bug depending on the outcome of the user program If you are in With the prompt You have available Th...

Page 82: ...e necessary assembler has been used in the form of separately compiled modules containing only assembler code no mixed language modules are used Physically 167Bug is contained in two of the four 44 pin PLCC CLCC EPROMs providing 512KB 128K longwords of storage Both EPROMs are necessary regardless of how much space is actually occupied by the firmware because of the 32 bit longword oriented MC68040...

Page 83: ...ocated the first 64KB is used for 167Bug stack and static variable space and the rest is reserved as user space Whenever the MVME167 is reset the target PC is initialized to the address corresponding to the beginning of the user space and the target stack pointers are initialized to addresses within the user space with the target Interrupt Stack Pointer ISP set to the top of the user space At powe...

Page 84: ...urns to the menu Autoboot Autoboot is a software routine that is contained in the 167Bug EPROMs to provide an independent mechanism for booting an operating system Autoboot Sequence 1 The autoboot routine automatically scans for controllers and devices in a specified sequence until a valid bootable device containing a boot media is found or the list is exhausted 2 If a valid bootable device is fou...

Page 85: ... the ENV command in Appendix A for more details ROMboot There are two spare EPROM sockets XU3 and XU4 available to carry user programmed EPROMs Therefore you do not have to reprogram the 167Bug EPROMs in order to implement the ROMboot feature One use of ROMboot might be resetting SYSFAIL on an unintelligent controller module The NORB command disables the function ROMboot Sequence 1 ROMboot is conf...

Page 86: ... until a valid bootable device containing a boot media is found or the list is exhausted 2 If a valid bootable device is found a boot from that device is started The controller scanning sequence goes from the lowest controller Logical Unit Number LUN detected to the highest LUN detected Refer to Appendix C for default LUNs Requirement Optionally with the ENV command Power must have just been appli...

Page 87: ... NIOT and ENV commands These parameters allow the selection of specific boot devices systems and files and allow programming of the Boot delay Refer to the ENV command in Appendix A Restarting the System You can initialize the system to a known state in three different ways reset abort and break Each has characteristics which make it more appropriate than the others in certain situations The debug...

Page 88: ... variables including disk device and controller parameters are restored to their default states 3 The breakpoint table and offset registers are cleared 4 The target registers are invalidated 5 Input and output character queues are cleared 6 Onboard devices timer serial ports etc are reset and 7 The first two serial ports are reconfigured to their default state During WARM reset 1 The 167Bug variab...

Page 89: ... local board condition which may interrupt the processor if enabled 2 Displays the target registers on the screen reflecting the machine state at the time the ABORT switch was pressed 3 Removes any breakpoints installed in the user code and keeps the breakpoint table intact 4 Returns control to the debugger Break A ÒBreakÓ is generated by pressing and releasing the BREAK key on the console termina...

Page 90: ... configuration status Self test if system mode has completed with error MPU clock speed calculation failure After debugger initialization is done and none of the above situations have occurred the SYSFAIL line is negated This indicates to the user or VMEbus masters the state of the debugger In a multi computer configuration other VMEbus masters could view the pertinent control and status registers...

Page 91: ... operations Disk I O system calls only via one of the TRAP 15 instructions for use by user programs Defined data structures for disk parameters Parameter Tables Parameters such as the address where the module is mapped and the type and number of devices attached to the controller module are kept in tables by 167Bug Default values for these parameters are assigned at powerup and cold start reset bu...

Page 92: ...ates this into an equivalent sector specification which is then passed on to the controller to initiate the transfer If the conversion from blocks to sectors yields a fractional sector count an error is returned and no data is transferred Device Probe Function A device probe with entry into the device descriptor table is done whenever a specified device is accessed i e when system calls DSKRD DSKW...

Page 93: ... the IOI command you can view the table and clear it if necessary IOP Physical I O to Disk IOP allows you to read or write blocks of data or to format the specified device in a certain way IOP creates a command packet from the arguments you have specified and then invokes the proper system call function to carry out the operation IOT I O Teach IOT allows you to change any configurable parameters a...

Page 94: ...r information on using these and other system calls Controller Command Packets To perform a disk operation 167Bug must eventually present a particular disk controller module with a controller command packet which has been especially prepared for that type of controller module This is accomplished in the respective controller driver module DSKRD Disk read System call to read blocks from a disk into...

Page 95: ...controller module expects to be given vary from controller to controller The disk driver module for the particular hardware module board must take the standardized packet given to a trap function and create a new packet which is specifically tailored for the disk drive controller it is sent to Refer to documentation on the particular controller module for the format of its packets and for using th...

Page 96: ... to that device are rewritten according to the parameter information contained in the conÞguration area Temporary The default parameter information is written back into the tables Command IOT You can use this command to reconÞgure the parameter table manually for any controller and or device that is different from the default Temporary The default parameter information is written back into the tab...

Page 97: ... 82596 LAN Coprocessor Ethernet Driver This driver manages surrounds the Intel 82596 LAN Coprocessor Management is in the scope of the reception of packets the transmission of packets receive buffer flushing and interface initialization This module ensures that the packaging and unpackaging of Ethernet packets is done correctly in the Boot PROM UDP IP Protocol Modules The Internet Protocol IP is d...

Page 98: ... IP address the address of a server host and the name of a file to be loaded into memory and executed TFTP Protocol Module The Trivial File Transfer Protocol TFTP is a simple protocol to transfer files It is implemented on top of the Internet User Datagram Protocol UDP or Datagram so it may be used to move files between machines on different networks implementing UDP The only thing it can do is re...

Page 99: ... Status Register GCSR Method Either method can be enabled disabled by the ENV command as its Remote Start Switch Method refer to Appendix A Multiprocessor Control Register MPCR Method A remote processor can initiate program execution in the local MVME167 dual port RAM by issuing a remote GO command using the Multiprocessor Control Register MPCR The MPCR located at shared RAM location of 800 offset...

Page 100: ... The MPAR contents specify the physical address as viewed from the local processor at which execution for this processor is to begin if the MPCR contains a G or B The MPAR is organized as follows MPCR Powerup sequence 1 At powerup the debug monitor self test routines initialize RAM including the memory locations used for multi processor support 800 through 807 2 The MPCR contains 00 at powerup ind...

Page 101: ...the MPCR by a remote processor indicates that the Go Direct type of transfer is requested Ð An ASCII B in the MPCR indicates that breakpoints are to be armed before control is transferred as with the GO command In either sequence an E is placed in the MPCR to indicate that execution is underway just before control is passed to RAM Any remote processor could examine the MPCR contents 4 If the code ...

Page 102: ...th status code B described in the previous section The GCSR registers are accessed in the VMEbus short I O space Each general purpose register is two bytes wide occurring at an even address The general purpose register number 0 is at an offset of 8 local bus or 4 VMEbus from the start of the GCSR registers The local bus base address for the GCSR is FFF40100 The VMEbus base address for the GCSR dep...

Page 103: ...bugger directory you can switch to the diagnostic directory by entering the debugger command Switch Directories SD The diagnostic prompt 167 Diag should appear Table 4 1 Diagnostic Monitor Commands Prefixes Command PreÞx Description AEM Append Error Messages Mode CEM Clear Error Messages CF Test Group ConÞguration Parameters Editor DE Display Error Counters DEM Display Errors DP Display Pass Count...

Page 104: ...itch Directories SE Stop on Error Mode ST Selftest ZE Clear Zero Error Counters ZP Zero Pass Count Table 4 2 Diagnostic Utilities Command Description WL Write loop enable RL Read loop enable Table 4 1 Diagnostic Monitor Commands Prefixes Command PreÞx Description ...

Page 105: ...entation on a particular diagnostic for the correct mode Table 4 3 Diagnostic Test Groups Test Set Description RAM Local RAM Tests SRAM Static RAM Tests RTC MK48T0x Real Time Clock Tests PCC2 Peripheral Channel Controller Tests MCECC Memory Board Tests MEMC1 MC040 Memory Controller 1 ASIC Tests MEMC2 MC040 Memory Controller 2 ASIC Tests ST2401 CD2401 Serial Port Tests VME2 VME Interface ASIC VMEch...

Page 106: ...4 28 Debugger General Information 4 ...

Page 107: ...mand Lines 167Bug is command driven and performs its various operations in response to user commands entered at the keyboard When the debugger prompt 167 Bug appears on the terminal screen then the debugger is ready to accept commands Terminal Input Output Control As the command line is entered it is stored in an internal buffer Execution begins only after the carriage return is entered so that yo...

Page 108: ...eappears However if the command entered causes execution of user target code for example GO then control may or may not return to the debugger depending on what the user program does X cancel line The cursor is backspaced to the beginning of the line H backspace The cursor is moved back one position Delete key delete Performs the same function as H D redisplay The entire command line as entered so...

Page 109: ... first argument Any required arguments as specified by the command An option field set off by a semicolon to specify conditions other than the default conditions of the command The commands are shown using a modified Backus Naur form syntax The metasymbols used are boldface strings A boldface string is a literal such as a command or a program name and is to be typed just as it appears italic strin...

Page 110: ...pressed in either hexadecimal decimal octal or binary by immediately preceding them with the proper base identifier If no base identifier is specified then the numeric value is assumed to be hexadecimal del Delimiter either a comma or a space exp Expression described in detail in a following section addr Address described in detail in a following section count Count the syntax is the same as for e...

Page 111: ...or precedence Subexpressions within parentheses are evaluated first Nested parenthetical subexpressions are evaluated from the inside out Valid expression examples The total value of the expression must be between 0 and FFFFFFFF Address as a Parameter Many commands use addr as a parameter The syntax accepted by 167Bug is similar to the one accepted by the MC68040 one line assembler All control add...

Page 112: ...ess register indirect with displacement two formats accepted d An Xn or d An Xn 120 A1 D2 120 A1 D2 Address register indirect with index and displacement two formats accepted bd An Xn od C A2 A3 100 Memory indirect preindexed bd An Xn od 12 A3 D2 10 Memory indirect postindexed For the memory indirect modes Þelds can be omitted For example three of many permutations are as follows An od A1 4 bd FC1...

Page 113: ...e at which they are loaded so it is harder to correlate addresses in the listing with addresses in the loaded program The offset registers solve this problem by taking into account this difference and forcing the display of addresses in a relative address offset format Offset registers have adjustable ranges and may even have overlapping ranges The range for each offset register is set by two addr...

Page 114: ...B A0 D0 00013284 5340 SUBQ W 1 D0 00013286 12D8 MOVE B A0 A1 00013288 51C8FFFC DBF D0 13286 0001328C 4CDF0101 MOVEM L A7 D0 A0 00013290 4E75 RTS 167Bug 1 2 3 MOVE STRING SUBROUTINE 4 5 0 00000000 48E78080 MOVESTR MOVEM L D0 A0 A7 6 0 00000004 4280 CLR L D0 7 0 00000006 1018 MOVE B A0 D0 8 0 00000008 5340 SUBQ W 1 D0 9 0 0000000A 12D8 LOOP MOVE B A0 A1 10 0 0000000C 51C8FFFC MOVS DBRA D0 LOOP 11 0 ...

Page 115: ...torola 68K CISC CPUs User s Manual Port Numbers Some 167Bug commands give you the option to choose the port to be used to input or output Valid port numbers which may be used for these commands are as follows 1 MVME167 EIA 232 D Debug Terminal Port 0 or 00 PORT 1 on the MVME167 P2 connector Sometimes known as the console port it is used for interactive user input output by default 2 MVME167 EIA 23...

Page 116: ...er each source line is entered it is assembled and the object code is loaded to memory Refer to the Debugging Package for Motorola 68K CISC CPUs User s Manual for complete details of the 167Bug Assembler Disassembler Downloading an S Record Object File Another way to enter a program is to download an object file from a host system The program must be in S record format described in the Debugging P...

Page 117: ...rough it Calling System Utilities from User Programs A convenient way of doing character input output and many other useful operations has been provided so that you do not have to write these routines into the target code You can access various 167Bug routines via one of the MC68040 TRAP instructions using vector 15 Refer to the Debugging Package for Motorola 68K CISC CPUs User s Manual for detail...

Page 118: ...rs the enabling of the MMUs it does not disable translation 167Bug Vector Table and Workspace As described in Memory Requirements on page 4 5 167Bug needs 64KB of read write memory to operate With the exception of the first 1024 byte vector table area you must be extremely careful not to use the above mentioned memory areas for other purposes Refer to Memory Requirements on page 4 5 to determine h...

Page 119: ... which are initialized to interface to the debug terminal and a host If these ports are reprogrammed the terminal characteristics must be modified to suit or the ports should be restored to the debugger set characteristics prior to reinvoking the debugger Exception Vectors Used by 167Bug The exception vectors used by the debugger are listed below These vectors must reside at the specified offsets ...

Page 120: ...eated that is it reflects the system stack pointer values just before the exception occurred In this way the operation of the debugger facility through an exception is transparent to users BC TRAP 15 System calls NOTE Level 7 interrupt ABORT pushbutton NOTE Level 7 interrupt AC Fail DC FP Unimplemented Data Type Software emulation and data type conversion of ßoating point data Table 5 2 Exception ...

Page 121: ...0000000 D4 00000000 D5 00000000 D6 00000000 D7 00000000 A0 00000000 A1 00000000 A2 00000000 A3 00000000 A4 00000000 A5 00000000 A6 00000000 A7 0000FFFC 00010006 D280 ADD L D0 D1 167Bug Exception Vector Tables Notice in the preceding example that the value of the target stack pointer register A7 has not changed even though a trace exception has taken place Your program may either use the exception ...

Page 122: ...o not have to be aware of the existence of the debugger vector table It is completely transparent and you should never make any modifications to the vectors contained in it Creating a New Vector Table Your program may create a separate vector table in memory to contain its exception vectors If this is done the program must change the value of the VBR to point at the new vector table In order to us...

Page 123: ... not listed in Table 5 2 on page 5 13 This guarantees that all exceptions have an interrupt handler assigned to handle it The handler stops target code execution and displays the register contents The following is an example of a routine which builds a separate vector table and then moves the VBR to point at it BUILDX Build exception vector table BUILDX MOVEC L VBR A0 Get copy of VBR LEA 10000 A1 ...

Page 124: ...ur program saved yielding the address of the 167Bug exception vector The program then jumps to the address stored at this vector location which is the address of the 167Bug exception handler Your program must make sure that there is an exception stack frame in the stack and that it is exactly the same as the processor would have created for the particular exception before jumping to the address of...

Page 125: ...ield 4 The sign field the exponent field and at least the first digit of the mantissa field must be present any unspecified digits in the mantissa field are set to zero 5 Each field must be separated from adjacent fields by an underscore 6 All the digit positions in the sign and exponent fields must be present Integer Data Types 12 Byte 1234 Word 12345678 Longword Floating Point Data Types 1_FF_7F...

Page 126: ... have an implied integer bit always 1 Extended Precision Real This format would appear in memory as An extended precision number takes 10 bytes in memory 1 bit sign Þeld 1 binary digit 8 bit biased exponent Þeld 2 hex digits Bias 7F 23 bit fraction Þeld 6 hex digits 1 bit sign Þeld 1 binary digit 11 bit biased exponent Þeld 3 hex digits Bias 3FF 52 bit fraction Þeld 13 hex digits 1 bit sign Þeld 1...

Page 127: ... data type Entering data in this format requires the following fields An optional sign bit or One decimal digit followed by a decimal point Up to 17 decimal digits at least one must be entered An optional Exponent field that consists of An optional underscore The Exponent field identifier letter ÒEÓ An optional Exponent sign From 1 to 3 decimal digits For more information about the MC68040 floatin...

Page 128: ...ler AS addr BC Block of Memory Compare BC range del addr B W L BF Block of Memory Fill BF range del data del increment B W L BH Bootstrap Operating System and Halt BH del controller LUN del device LUN del string BI Block of Memory Initialize BI range B W L BM Block of Memory Move BM range del addr B W L BO Bootstrap Operating System BO del controller LUN del device LUN del string BR Breakpoint Ins...

Page 129: ... Execute User Program GO addr GT Go to Temporary Breakpoint GT addr HE Help HE command IOC I O Control for Disk IOC IOI I O Inquiry IOI C L IOP I O Physical Direct Disk Access IOP IOT I O TEACH for ConÞguring Disk Controller IOT A F H T IRQM Interrupt Request Mask IRQM mask LO Load S records from Host LO port addr X C T text MA Macro DeÞne Display MA name L NOMA Macro Delete NOMA name MAE Macro Ed...

Page 130: ...NBO Network Boot Operating System NBO controller LUN device LUN client IP Address server IP Address string NIOC Network I O Control NIOC NIOP Network I O Physical NIOP NIOT Network I O Teach NIOT H A NPING Network Ping NPING controller LUN del device LUN del source IP del destination IP del n packets OF Offset Registers Display Modify OF Rn A PA Printer Attach PA port NOPA Printer Detach NOPA port...

Page 131: ...ble Detach NOSYM SYMS Symbol Table Display Search SYMS symbol name S T Trace T count TA Terminal Attach TA port TC Trace on Change of Control Flow TC count TIME Display Time and Date TIME C L O TM Transparent Mode TM port del ESCAPE TT Trace to Temporary Breakpoint TT addr VE Verify S Records Against Memory VE port addr X C text VER Display Revision Version VER E WL Write Loop WL addr del data B W...

Page 132: ...5 26 Using the 167Bug Debugger 5 ...

Page 133: ...ile RAM NVRAM Refer to the MVME167 Single Board Computer User s Manual for the actual location The information block contains various elements detailing specific operation parameters of the hardware The MVME167 Single Board Computer User s Manual describes the elements within the board information block and lists the size and logical offset of each element The CNFG command does not describe the el...

Page 134: ...ngs and data strings are right justified The data strings are padded with zeroes if the length is not met In the event of corruption of the board information block the command displays a question mark for nondisplayable characters A warning message WARNING Board Information Block Checksum Error is also displayed in the event of a checksum failure Using the I option initializes the unused area of t...

Page 135: ...o insure the integrity of the NVRAM contents In the instance of BBRAM checksum failure certain default values are assumed as stated below The bug operational parameters which are kept in NVRAM are not initialized automatically on power up warm reset It is up to the Bug user to invoke the ENV command Once the ENV command is invoked and executed without error Bug default and or user modified paramet...

Page 136: ... to VMEbus to determine presence of supported controllers Negate VMEbus SYSFAIL Always Y N N Negate VMEbus SYSFAIL after successful completion or entrance into the bug command monitor Local SCSI Bus Reset on Debugger Startup Y N N Local SCSI bus is not reset on debugger startup Local SCSI Bus Negotiations Type A S N A Asynchronous Ignore CFGA Block on a Hard Disk Boot Y N Y Enable the ignorance of...

Page 137: ...ROM Boot Enable search of VMEbus Y N N VMEbus address space will not be accessed by ROMboot ROM Boot Abort Delay 0 This is the time in seconds that the ROMboot sequence will delay before starting the boot The purpose for the delay is to allow you the option of stopping the boot by use of the Break key The time value is from 0 through 255 seconds ROM Boot Direct Starting Address FF800000 First loca...

Page 138: ...e currently supported by the Bug Default is 00 Network Auto Boot Abort Delay 5 This is the time in seconds that the Network Boot sequence will delay before starting the boot The purpose for the delay is to allow you the option of stopping the boot by use of the Break key The time value is from 0 through 255 seconds Table A 1 ENV Command Parameters Continued ENV Parameter and Options Default Meanin...

Page 139: ... in size The location for these parameters is determined by setting this ENV pointer If you have used the exact same space for your own program information or commands they will be overwritten and lost Memory Search Starting Address 00000000 Where the Bug begins to search for a work page a 64KB block of memory to use for vector table stack and variables This must be a multiple of the debugger work...

Page 140: ...ugger work page modulo 10000 64KB Typically Memory Search Increment Size is the product of CPU number and size of the Bug work page Example Þrst CPU 0 0 x 10000 second CPU 10000 1 x 10000 etc Memory Search Delay Enable Y N N There will be no delay before the Bug begins its search for a work page Memory Search Delay Address FFFFCE0F The process of using the Memory Search Delay Address was implement...

Page 141: ...There are two slave address decoders They are set up as follows Slave Enable 1 Y N Y Yes Setup and enable the Slave Address Decoder 1 Slave Starting Address 1 00000000 Base address of the local resource that is accessible by the VMEbus as viewed by the VMEbus Default is the base of local memory 0 Slave Ending Address 1 01FFFFFF Ending address of the local resource that is accessible by the VMEbus ...

Page 142: ...Reference Guide Slave Enable 2 Y N Y Yes Setup and enable the Slave Address Decoder 2 Slave Starting Address 2 FFE00000 Base address of the local resource that is accessible by the VMEbus as viewed by the VMEbus Default is the base address of static RAM FFE00000 Slave Ending Address 2 FFE1FFFF Ending address of the local resource that is accessible by the VMEbus as viewed by the VMEbus Default is ...

Page 143: ...ting Address 2 00000000 Base address of the VMEbus resource that is accessible from the local bus Default is 0 Master Ending Address 2 00000000 Ending address of the VMEbus resource that is accessible from the local bus Default is 0 Master Control 2 00 Works the same as Slave Control 1 Default is 00 Master Enable 3 Y N N Do not set up and enable the Master Address Decoder 3 Master Starting Address...

Page 144: ... VMEbus resource that is associated with the starting and ending address selection from the previous questions Default is 0 Master Address Translation Select 4 00000000 This register deÞnes which bits of the Translation Address are signiÞcant A logical one 1 indicates signiÞcant address bits logical zero 0 is non signiÞcant The non signiÞcant bits will come from the local bus address that accesses...

Page 145: ... Base interrupt vector for the component speciÞed Default PCCchip2 05 VMEchip2 Vector 1 06 VMEchip2 Vector 2 07 VMEC2 GCSR Group Base Address CC SpeciÞes the group address FFFFXX00 in Short I O for this board Default CC VMEC2 GCSR Board Base Address 00 SpeciÞes the base address FFFFCCXX in Short I O for this board Default 00 VMEbus Global Time Out Code 01 This controls the VMEbus timeout when this...

Page 146: ...A 14 Configure and Environment Commands A ...

Page 147: ...ave its address changed by its onboard jumpers and or switches so that it matches Second Address and can be called up by Second CLUN Controller Type First CLUN First Address Second CLUN Second Address CISC Single Board Computer MVME167 00 MVME320 Winchester Floppy Controller 11 FFFFB000 12 FFFFAC00 MVME323 ESDI Winchester Controller 08 FFFFA000 09 FFFFA200 MVME327A SCSI Controller 02 FFFFA600 03 F...

Page 148: ...hich may be any of these Fixed direct access Removable ßexible direct access TEAC style CD ROM Sequential access MVME320 4 Devices Controller LUN Address Device LUN Device Type 11 FFFFB000 0 1 2 3 Winchester hard drive Winchester hard drive 5 1 4 DS DD 96 TPI ßoppy drive 5 1 4 DS DD 96 TPI ßoppy drive 12 FFFFAC00 MVME323 4 Devices Controller LUN Address Device LUN Device Type 8 FFFFA000 0 1 2 3 ES...

Page 149: ...quential access 3 FFFFA700 80 81 Local ßoppy drive Local ßoppy drive MVME328 14 Devices Controller LUN Address Device LUN Device Type 6 FFFF9000 00 08 10 18 20 28 30 SCSI Common Command Set CCS which may be any of these Removable ßexible direct access TEAC style CD ROM Sequential access 7 FFFF9800 16 FFFF4800 40 48 50 58 60 68 70 Same as above but these will only be available if the daughter card ...

Page 150: ...reaming tape drive 5 FFFF5100 IOT Parameter Floppy Types and Formats DSDD5 PCXT8 PCXT9 PCXT9_3 PCAT PS2 SHD Sector Size 0 128 1 256 2 512 3 1024 4 2048 5 4096 1 2 2 2 2 2 2 Block Size 0 128 1 256 2 512 3 1024 4 2048 5 4096 1 1 1 1 1 1 1 Sectors Track 10 8 9 9 F 12 24 Number of Heads 2 2 2 2 2 2 2 Number of Cylinders 50 28 28 50 50 50 50 Precomp Cylinder 50 28 28 50 50 50 50 Reduced Write Current C...

Page 151: ... 0960 0B40 1680 Number of Logical Blocks 100 in size 09F8 0500 05A0 0B40 12C0 1680 2D00 Number of Bytes in Decimal 653312 327680 368460 737280 1228800 1474560 2949120 Media Size Density 5 25 DD 5 25 DD 5 25 DD 3 5 DD 5 25 HD 3 5 HD 3 5 ED Notes 1 All numerical parameters are in hexadecimal unless otherwise noted 2 The DSDD5 type ßoppy is the default setting for the debugger IOT Parameter Floppy Ty...

Page 152: ...B 6 Disk Tape Controller Data B ...

Page 153: ...h the following debugger commands and debugger system calls The controllers are accessed via the CLUNs and DLUNs specified in the following table Debugger Commands Debugger System Calls NBH NETRD NBO NETWR NIOC NETFOPN NIOP NETFRD NIOT NETCFIG NPING NETCTRL NAB Table C 1 Network Controller Access Data Controller Type CLUN DLUN Address Interface Type MVME167 00 00 FFF46000 Ethernet MVME376 02 00 FF...

Page 154: ...FF000000 Ethernet MVME374 11 00 FF100000 Ethernet MVME374 12 00 FF200000 Ethernet MVME374 13 00 FF300000 Ethernet MVME374 14 00 FF400000 Ethernet MVME374 15 00 FF500000 Ethernet Table C 1 Network Controller Access Data Continued Controller Type CLUN DLUN Address Interface Type ...

Page 155: ... power 1 Make sure the system is plugged in 2 Check that the board is securely installed in its backplane or chassis 3 Check that all necessary cables are connected to the board per this manual 4 Check for compliance with System Considerations in Chapter 3 5 Review the Installation and Startup procedures in Chapter 3 The step by step powerup routine for your board is on page 3 17 Try it B If the L...

Page 156: ...nd power B Board jumpers may be conÞgured incorrectly Check the board jumpers per this manual C You may have invoked ßow control by pressing a HOLD or PAUSE key or by typing S Also a HOLD LED may be lit on the keyboard Press the HOLD or PAUSE key again If this does not free up the keyboard type in Q Hold down the CONTROL key and type a ÒQÓ Table D 1 Troubleshooting Steps Continued Condition Possib...

Page 157: ...ming the next step will change some parameters that may affect your system operation 4 Restart the system by Òdouble button resetÓ press the RESET and ABORT switches at the same time release RESET Þrst wait Þve seconds then release ABORT 5 If the debug prompt appears go to step IV or step V as indicated If the debug prompt does not appear go to step VI B The board may need to be reset Table D 1 Tr...

Page 158: ...nge some parameters that may affect your system operation 2 Type in env d Return This sets up the default parameters for the debugger environment 3 When prompted to Update Non Volatile RAM type in y Return 4 When prompted to Reset Local System type in y Return 5 After clock speed is displayed immediately within Þve seconds press the RETURN key Return or BREAK to exit to System Menu Then enter a 3 ...

Page 159: ...e are no errors go to step V V The debugger is in system mode and the board auto boots or the board has passed selftests A No problems Troubleshooting is done No further troubleshooting steps are required Note Even if the board passes all tests it may still be bad Selftest does not try out all functions in the board for example SCSI or VMEbus tests VI The board has failed one or more of the tests ...

Page 160: ...D 6 Troubleshooting the MVME167 Solving Startup Problems D ...

Page 161: ...pose Although handshaking is unnecessary in many applications the lines themselves remain part of many designs because they facilitate troubleshooting Table E 1 lists the standard EIA 232 D interconnections To interpret this information correctly remember that EIA 232 D was intended to connect a terminal to a modem When computers are connected to each other without modems one of them must be confi...

Page 162: ...nal to indicate that message transmission can begin When a modem is used CTS follows the off to on transition of RTS after a time delay 6 DSR DATA SET READY Output from the modem to the terminal to indicate that the modem is ready to transmit data 7 SIG GND SIGNAL GROUND Common return line for all signals at the modem interface 8 DCD DATA CARRIER DETECT Output from the modem to the terminal to ind...

Page 163: ... is illustrated in Figure E 1 22 RI RING INDICATOR Output from the modem to the terminal indicates to the terminal that an incoming call is present The terminal causes the modem to answer the phone by carrying DTR true while RI is active 23 Not used 24 TxC TRANSMIT CLOCK DTE Input to modem from terminal same function as TxC on pin 15 25 BSY BUSY Input to modem from terminal A positive EIA signal a...

Page 164: ...his signal was to inform the system that the carrier tone from the distant modem was being received This signal is frequently used by the software to display a message such as CARRIER NOT PRESENT to help the user diagnose failure to communicate Obviously if the system is designed properly to use this signal and is not connected to a modem the signal must be provided by a pullup resistor or gate as...

Page 165: ...ARDWARE TRANSPARENT MODE LOGIC 470Ω 39kΩ 39kΩ 39kΩ 470Ω 39kΩ 12V 2 1 5 6 8 7 7 1 20 2 3 4 5 6 CHASSIS GND CONNECTOR TO TERMINAL CONNECTOR TO MODEM OR HOST SYSTEM RXD TXD NC CTS DSR DCD SIG GND DTR TXD RXD RTS CTS DCD 12V 12V 12V 12V 12V GND 12V SIG GND NC cb181 9210 470Ω SERIAL PORT LS08 LS08 470Ω 470Ω 470Ω SERIAL PORT 1489A 1489A 1489A 1488 1488 1488 1489A ...

Page 166: ...DCD and DSR signals Two of these connectors wired back to back can be used In this implementation however diagnostic messages that might otherwise be generated do not occur because all the handshaking is bypassed In addition the TX and RX lines may have to be crossed since TX from a terminal is outgoing but the TX line on a modem is an incoming signal Figure E 2 Minimum EIA 232 D Connection CHASSI...

Page 167: ...e connected to different electrical outlets there may be several volts of difference in ground potential If pin 1 of each device is interconnected with the others via cable several amperes of current could result This condition may not only be dangerous for the small wires in a typical cable but may also produce electrical noise that causes errors in data transmission That is why Figure E 1 shows ...

Page 168: ...E 8 EIA 232 D Interconnections E ...

Page 169: ...on 3 19 adapters 2 7 address 5 4 as a parameter 5 5 formats 5 6 application specific integrated circuits ASICs 2 8 arguments 5 3 arithmetic operators 5 4 ASCII string 5 4 ASICs 2 8 MCECC 2 10 MEMC040 2 10 PCCchip2 2 9 VMEchip2 2 9 assembler disassembler 5 10 assertion 1 3 assertion and negation conventions 1 3 autoboot 4 6 auto strobe feature 2 21 B Backus Naur 5 3 base and top addresses 5 7 base ...

Page 170: ...1 commands prefixes diagnostic monitor 4 25 comparison of M68000 based firmware 4 4 configuration default disk tape control ler B 2 configuration hardware 3 8 Configure CNFG and Environment ENV commands A 1 Configure Board Information Block CN FG A 1 connector P2 5 9 connectors 2 7 console port 5 9 console terminal D 1 control and status bit definitions 1 4 control bit 1 4 control pins 2 20 contro...

Page 171: ...ble precision real 5 20 download 5 10 downloading an S record object file 5 10 DRAM mezzanine boards 2 2 programming considerations 2 16 DRAM dynamic RAM 2 15 DRAM base address 3 26 DTE data terminal equipment E 1 dynamic RAM DRAM 2 15 E EIA 232 D interconnections E 1 E 2 middle of the road configuration E 5 minimum connection E 6 ports 2 3 2 19 3 20 5 13 standard E 1 entering and debugging progra...

Page 172: ...4 handshaking 3 21 E 1 E 4 hard disk drive B 2 hardware functions 5 13 interrupts 2 23 preparation and installation 3 1 headers 3 8 hexadecimal character 1 2 host port 5 9 host system 5 10 I I O interfaces 2 18 initialize the real time clock 3 24 installation and startup 4 6 installation instructions 3 15 Intel 82596 LAN Coprocessor Ethernet driver 4 19 interconnections EIA 232 D E 1 implementatio...

Page 173: ...symbols 5 3 mezzanine board 2 15 stacked configuration 2 2 MK48T08 RAM and clock chip 2 17 MK48T08 see Battery Backed Up RAM BBRAM and NVRAM 2 16 modem s E 1 Motorola style byte ordering 1 4 MPAR Multiprocessor Address Regis ter 4 22 MPCR Multiprocessor Control Register Method 4 21 MPCR status codes 4 22 MPU clock speed calculation 4 12 multiple module cage configuration 3 27 Multiprocessor Addres...

Page 174: ...dure 3 2 P P1 2 7 P2 2 7 P2 adapter board 3 19 packed decimal real 5 21 parallel printer port 2 3 parallel port interface 2 20 parameter tables 4 13 4 18 parity mezzanines 2 15 PCCchip2 2 9 2 20 8 16 and 32 bit accesses to the MK48T08 2 17 peripheral connection procedures 3 20 port 0 or 00 5 9 port 1 or 01 5 9 port number s 5 3 5 9 power up the system 3 24 preserving the debugger operating envi ro...

Page 175: ...8 serial ports 2 3 Set Environment to Bug Operating Sys tem ENV A 3 settings for J6 and J7 serial port 4 clock con figuration select headers 3 11 for J6 SRAM Optional Backup Power Select Header 3 12 settings for J1 general purpose readable jumpers 3 9 J2 system controller header 3 10 setup operation parameters default in NVRAM 3 9 shielded cables 3 16 sign field 5 19 signal ground E 7 levels E 1 s...

Page 176: ...ule 4 20 tick timers 2 23 time of day clock 2 17 3 24 timeout 2 23 transfer type TT 2 24 transition module installation 3 19 transition modules 2 8 supported by MVME167 board 2 8 TRAP 15 5 11 troubleshooting steps D 1 true 1 3 True false bit state definitions 1 4 TRXC4 Transmit Receive Clock 4 3 10 3 13 TT transfer type 2 24 two byte 1 3 U UDP IP protocol modules 4 19 unpacking instructions 3 1 us...

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