Motorola MVME162P-242, Installation And Use Manual

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Hardware Preparation and Installation
1
Notes
As shown in the table, the Petra/MC2 interface supports parity
DRAM emulations up to 16MB. For sizes beyond 16MB, it is
necesary to use the MCECC memory model.
For access to the MCECC registers, you must first disable the
MC2 interface by setting S3 to 001 (Off/Off/On). Further
details on selecting the MCECC emulation can be found
under
MCECC DRAM Size (S6) .
If you modify the switch settings, you will need to execute env;d
<CR> so that the firmware recognizes the new memory defaults.
General-Purpose Readable Switch (S4 Pin 5)
Switch S4 is similar in function to the general-purpose readable jumper
headers found on earlier MVME162/172 series boards. S4 provides eight
software-readable switch segments. These switches can be read as bits in
a register (at address $FFF4202C) in the MC2 General-Purpose Inputs
register in the Petra ASIC (refer to the Programmer’s Reference Guide for
details). Bit GPI7 is associated with switch segment 1; bit GPI0 is
associated with switch segment 8. The bit values are read as a 0 when the
switch is on, and as a 1 when the switch is off. The MVME162P2 is
shipped from the factory with S4 set to all 0s (all switches set to
ON
), as
diagrammed below.
Table 1-8. MC2 DRAM Size Settings
S3
Segment 1
S3
Segment 2
S3
Segment 3
MC2 DRAM
Size
ON ON ON 1MB
OFF ON ON 4MB
OFF ON OFF 8MB
OFF OFF ON Disabled
OFF OFF OFF 16MB