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Debugger General Information

3

If the code being executed in dual-port RAM is to reenter the debug
monitor, a TRAP #15 call using function $0063 (SYSCALL .RETURN)
returns control to the monitor with a new display prompt. Note that every
time the debug monitor returns to the prompt, an R is moved into the
MPCR to indicate that control can be transferred once again to a specified
RAM location.

GCSR Method

A remote processor can initiate program execution in the local
MVME162LX dual-port RAM by issuing a remote GO command using
the VMEchip2 Global Control and Status Registers (GCSR). The remote
processor places the controller’s execution address in general purpose
registers 0 and 1 (GPCSR0 and GPCSR1). The remote processor then sets
bit 8 (SIG0) of the VMEchip2 LM/SIG register. This causes the controller
to install breakpoints and begin execution. The result is identical to the
MPCR method (with status code B) described in the previous section.

The GCSR registers are accessed in the VMEbus short I/O space. Each
general purpose register is two bytes wide, occurring at an even address.
The general purpose register number 0 is at an offset of $8 (local bus) or
$4 (VMEbus) from the start of the GCSR registers. The local bus base
address for the GCSR is $FFF40100. The VMEbus base address for the
GCSR depends on the group select value and the board select value
programmed in the Local Control and Status Registers (LCSR) of the
controller. The execution address is formed by reading the GCSR general
purpose registers in the following manner:

The address appears as:

GPCSR0 used as the upper 16 bits of the address

GPCSR1 used as the lower 16 bits of the address

GPCSR0 GPCSR1

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Summary of Contents for MVME162LX 200 Series

Page 1: ...MVME162LX 200 300 Series Embedded Controller Installation and Use V162LX2 3A IH3 ...

Page 2: ...rior written permission of Motorola Inc It is possible that this publication may contain reference to or information about Motorola products machines and programs programming or services that are not announced in your country Such references or information must not be construed to mean that Motorola intends to announce such Motorola products programming or services in your country Restricted Right...

Page 3: ...ion The information contained in this manual applies to the MVME162LX 2xx and MVME162LX 3xx 200 and 300 series models that are currently shipping as of the publication date of this manual Motorola and the Motorola symbol are registered trademarks of Motorola Inc All other products mentioned in this document are trademarks or registered trademarks of their respective holders Copyright Motorola Inc ...

Page 4: ... or other qualified maintenance personnel may remove equipment covers for internal subassembly or component replacement or any internal adjustment Do not replace components with power cable connected Under certain conditions dangerous voltages may exist even with the power cable removed To avoid injuries always disconnect power and discharge circuits before touching them Do Not Service or Adjust A...

Page 5: ...bility Generic Immunity Standard Part 1 Residential Commercial and Light Industry IEC801 2 Electromagnetic Compatibility for Industrial Process Measurement and Control Equipment Part 2 Electrostatic Discharge Requirements IEC801 3 Electromagnetic Compatibility for Industrial Process Measurement and Control Equipment Part 3 Radiated Electromagnetic Field Requirements IEC801 4 Electromagnetic Compat...

Page 6: ......

Page 7: ...am 1 11 Functional Description 1 12 Switches and LEDs 1 12 ABORT Switch 1 12 RESET Switch 1 12 Front Panel Indicators 1 13 Data Bus Structure 1 13 MC68040 or MC68LC040 CPU 1 14 MC68XX040 Cache 1 14 No VMEbus Interface Option 1 14 Memory Options 1 15 DRAM Options 1 15 SRAM Options 1 15 SRAM Batteries 1 17 EPROM and Flash Memory 1 18 Battery Backed Up RAM and Clock 1 18 VMEbus Interface and VMEchip2...

Page 8: ... Short I O Memory Map 1 49 Software Initialization 1 50 Multi MPU Programming Considerations 1 50 Local Reset Operation 1 50 EMC Compliance 1 51 CHAPTER 2 Hardware Preparation and Installation Introduction 2 1 Unpacking Instructions 2 1 Hardware Preparation 2 1 System Controller Select Header J1 2 2 General Purpose Readable Jumpers Header J11 2 4 EPROM Flash Configuration Header J12 2 5 SRAM Backu...

Page 9: ... Input Output Inquiry 3 14 IOP Physical I O to Disk 3 15 IOT I O Teach 3 15 IOC I O Control 3 15 BO Bootstrap Operating System 3 15 BH Bootstrap and Halt 3 15 Disk I O via 162Bug System Calls 3 15 Default 162Bug Controller and Device Parameters 3 17 Disk I O Error Codes 3 17 Network I O Support 3 18 Intel 82596 LAN Coprocessor Ethernet Driver 3 18 UDP IP Protocol Modules 3 18 RARP ARP Protocol Mod...

Page 10: ... 162Bug Target Vector Table 4 12 Creating a New Vector Table 4 13 162Bug Generalized Exception Handler 4 15 Floating Point Support 4 17 Single Precision Real 4 18 Double Precision Real 4 18 Extended Precision Real 4 18 Packed Decimal Real 4 19 Scientific Notation 4 19 The 162Bug Debugger Command Set 4 20 4 24 APPENDIX A Configure and Environment Commands Configure Board Information Block A 1 Set E...

Page 11: ... J15 Signals G 1 Mezzanine Connector J16 Signals G 6 Mezzanine Board Dimensions G 11 APPENDIX H Troubleshooting CPU Boards Solving Startup Problems H 1 APPENDIX I Input Output Connections IndustryPack Logic Interface Interconnections I 1 IndustryPack I O Interconnections I 4 Remote Reset LED Interconnection I 5 VME Bus Interconnection I 6 Connector P1 Interconnect Signals I 6 Connector P2 Intercon...

Page 12: ...Local I O Devices Memory Map 1 28 Table 1 6 VMEchip2 Memory Map LCSR Summary Sheet 1 of 2 1 32 Table 1 7 MCchip Register Map 1 36 Table 1 8 MCECC Internal Register Memory Map 1 37 Table 1 9 Z85230 SCC Register Addresses 1 39 Table 1 10 82596CA Ethernet LAN Memory Map 1 39 Table 1 11 53C710 SCSI Memory Map 1 40 Table 1 12 IPIC Overall Memory Map 1 41 Table 1 13 IPIC Memory Map Control and Status Re...

Page 13: ...onnector J10 Interconnect Signals F 1 Table G 1 Mezzanine Connector J15 Interconnect Signals G 1 Table G 2 Mezzanine Connector J16 Interconnect Signals G 6 Table H 1 Troubleshooting MVME162LX Boards H 1 Table I 1 IndustryPack Interconnect Signals I 1 Table I 2 Remote Reset LED interconnect Signals I 5 Table I 3 Connector P1 Interconnect Signals I 6 Table I 4 Connector P2 Interconnect Signals I 10 ...

Page 14: ...xiv ...

Page 15: ... Embedded Controller Programmer s Reference Guide Overview The MVME162LX Embedded Controller is based on the MC68040 or the MC68LC040 microprocessor The MC68040 microprocessor has a floating point math coprocessor and the MC68LC040 does not Various versions of the controller contain the following 1 or 4 MB of parity protected DRAM 4 8 16 or 32 MB of ECC protected DRAM 128 KB of SRAM with battery b...

Page 16: ... DMA transfers to the VMEbus however can be D16 D32 D16 BLT D32 BLT or D64 MBLT The MCchip ASIC provides four tick timers the interface to the LAN chip SCSI chip serial port chip BBRAM EPROM Flash DRAM and SRAM The MCECC memory controller ASIC provides the programmable interface for the ECC protected 16 MB DRAM mezzanine board The IndustryPack Interface Controller IPIC ASIC provides control and st...

Page 17: ...ssor 4 MB DRAM 128 KB SRAM 1 MB Flash memory 2 IndustryPack sites 4 serial ports SCSI 212 MC68LC040 25 MHz microprocessor 4 MB DRAM 128 KB SRAM 1 MB Flash memory 2 IndustryPack sites 4 serial ports Ethernet 213 MC68LC040 25 MHz microprocessor 4 MB DRAM 128 KB SRAM 1 MB Flash memory 2 IndustryPack sites 4 serial ports SCSI Ethernet 216 MC68LC040 25 MHz microprocessor 4 MB DRAM 128 KB SRAM 1 MB Flas...

Page 18: ...5 MHz microprocessor 16 MB ECC DRAM 128 KB SRAM 1 MB Flash memory 2 IndustryPack sites 4 serial ports Ethernet 263 MC68040 25 MHz microprocessor 16 MB ECC DRAM 128 KB SRAM 1 MB Flash memory 2 IndustryPack sites 4 serial ports SCSI Ethernet 322 MC68LC040 25 MHz microprocessor 8 MB ECC DRAM 128 KB SRAM 1 MB Flash memory 2 IndustryPack sites 4 serial ports Ethernet 323 MC68LC040 25 MHz microprocessor...

Page 19: ...nsition modules are unnecessary as the controller incorporates industry standard SCSI Ethernet and RJ45 serial connectors on its front panel Features General features of the MVME162LX Embedded Controller are shown in the following table Feature Description Models Microprocessor MC68LC040 See Table 1 1 MC68040 See Table 1 1 Memory 1 or 4 MB of parity protected DRAM See Table 1 1 4 8 16 or 32 MB of ...

Page 20: ...erfaces 2 or 4 IndustryPack Interface sites See Table 1 1 VMEbus interface Optional NOTE This option is a factory installed and cannot be added in the field VMEbus system controller All models VMEbus requester VMEbus interrupter VMEbus interrupt handler Eight software interrupts Programmable map decoders for the master and slave interfaces VMEbus to local bus interface A24 A32 D8 D16 D32 D8 D16 D3...

Page 21: ...cs Specifications Power requirements with EPROMs without IPs 5Vdc 5 3 5 A typical 4 5 A maximum 12 Vdc 5 100 mA maximum 12 Vdc 5 100 mA maximum Operating temperature 0 to 70 C exit air with forced air cooling see NOTE Storage temperature 40 to 85 C Relative humidity 5 to 90 noncondensing Physical dimensions PC board with mezzanine module only Height Depth Thickness PC board with connectors and fro...

Page 22: ...re the incoming airstream first encounters the controller under test Test software is executed as the controller is subjected to ambient temperature variations Case temperatures of critical high power density integrated circuits are monitored to ensure the component vendor s specifications are not exceeded While the exact amount of air flow required for cooling depends on the ambient air temperatu...

Page 23: ...5 12 slot VME chassis This board was loaded with one GreenSpring IP Dual P T module position a and one GreenSpring IP 488 module position b One twenty five watt load board was installed adjacent to each side of the board under test The exit air velocity was approximately 200 LFM between the controller and the IP Dual P T module Under these conditions a 10 C rise between the inlet and exit air was ...

Page 24: ...of the voltage level high or low that they represent Data and address sizes are defined as follows A byte is eight bits numbered 0 through 7 with bit 0 being the least significant A word is 16 bits numbered 0 through 15 with bit 0 being the least significant A longword is 32 bits numbered 0 through 31 with bit 0 being the least significant The terms control bit and status bit are used extensively ...

Page 25: ...nel SCSI Connector VMEchip2 VMEbus Interface IPchip IndustryPack Interface i82596CA Ethernet Controller 53C710 SCSI Coprocessor Four 32 pin EPROM Sockets Dual 85230 Serial I O Controllers FLASH 1MB MCchip MK48T08 Battery Backed 8KB 128KB SRAM Memory Array w Battery 2MB SRAM Memory Array w Battery 16MB ECC DRAM Memory Array 1 or 4MB Parity DRAM Memory Array MC68LC040 MPU 25 MHz Optional MC68040 Con...

Page 26: ...tch This interrupter is filtered to remove switch bounce RESET Switch Note For an MVME162LX without the VMEbus option no VMEchip2 the LCSR control bit is not available to reset the module In this case the watchdog timer is allowed to time out to reset the controller The RESET switch resets all onboard devices it also drives SYSRESET if the MVME162LX is operating as system controller The RESET swit...

Page 27: ...nal line is low This indicates one of the local bus masters is executing a local bus cycle Part of DS1 SCON LED green Lights when the VMEchip2 in the MVME162LX is the VMEbus system controller Part of DS2 FUSES LED green Lights when 5 Vdc 12 Vdc and 12 Vdc power is available to the LAN IP and SCSI interfaces Part of DS2 Data Bus Structure The local bus on the MVME162LX Embedded Controller is a 32 b...

Page 28: ...LX local bus masters VMEchip2 MC68XX040 53C710 SCSI controller and 82596CA Ethernet controller have programmable control of the snoop caching mode The MVME162LX local bus slaves which support MC68XX040 bus snooping are defined in the Local Bus Memory Map table later in this chapter No VMEbus Interface Option The MVME162LX can be operated as an embedded controller without the VMEbus interface To su...

Page 29: ...g Model The DRAM map decoder can be programmed to accommodate different base address es and sizes of mezzanine boards The onboard DRAM is disabled by a local bus reset and must be programmed before the DRAM can be accessed Refer to the MCchip and MCECC descriptions in the MVME162LX Embedded Controller Programmer s Reference Guide for detailed programming information Most DRAM devices require some ...

Page 30: ...em backup source may be a battery connected to the VMEbus 5V STDBY pin and the secondary source may be the onboard battery If the system source should fail or the board is removed from the chassis the onboard battery takes over Further details on SRAM configuration and specifics on SRAM performance can be found in the section on the SRAM Memory Controller in the MCchip Programming Model in the MVM...

Page 31: ...e power source for the onboard SRAM is a RAYOVAC FB1225 battery with two BR1225 type lithium cells The battery is socketed for easy removal and replacement The power source for the mezzanine SRAM is a Sanyo CR2430 battery Small capacitors are provided so that the batteries can be quickly replaced without data loss The lifetime of the batteries is very dependent on the ambient temperature of the bo...

Page 32: ...oller comes with 1 MB of flash memory and four EPROM sockets ready for the installation of EPROMs which may be ordered separately Flash memory is a single Intel 28F008SA device organized in a 1Mbit x 8 configuration The EPROM locations are standard JEDEC 32 pin DIP sockets accommodating four jumper selectable densities 128 Kbit x 8 256 Kbit X 8 512 Kbit x 8 1 Mbit x8 A jumper setting GPIO3 pins 7 ...

Page 33: ...em applications The I O functions include serial ports and optional interfaces for IndustryPack IP modules LAN Ethernet transceivers and SCSI mass storage devices I O signals are routed through industry standard connectors on the controller s front panel no adapter boards or transition modules are necessary I O connections on the controller s front panel include an optional 68 pin SCSI connector a...

Page 34: ...Ps and the MVME162LX is the IndustryPack Interface Controller IPIC ASIC Access to the IPs is provided by two 3M connectors located behind the controller s front panel Refer to the chapter on the IPIC in the MVME162LX Embedded Controller Programmer s Reference Guide for additional information on the IP interface Ethernet Interface The MVME162LX Embedded Controller uses the 82596CA controller to imp...

Page 35: ...er to the 82596CA user s guide and to the MCchip in the MVME162LX Embedded Controller Programmer s Reference Guide for additional programming information SCSI Interface The controller supports mass storage subsystems through the industry standard SCSI bus These subsystems may include hard and floppy disk drives streaming tape drives and other mass storage devices The SCSI interface is implemented ...

Page 36: ...These include tick timers software programmable hardware interrupts a watchdog timer and a local bus timeout Programmable Tick Timers Four 32 bit programmable tick timers with a 1 µs resolution are provided in the MCchip and two 32 bit programmable tick timers are provided in the optional VMEchip2 The tick timers can be programmed to generate periodic interrupts to the processor Refer to the VMEch...

Page 37: ... The MVME162LX Embedded Controller provides timeout functions in the VMEchip2 and the MCchip for the local bus When the timer is enabled and a local bus access times out a Transfer Error Acknowledge TEA signal is sent to the local bus master The timeout value is selectable by software for 8 µsec 64 µsec 256 µsec or infinite The local bus timer does not operate during VMEbus bound cycles VMEbus bou...

Page 38: ...llows the reset abort and LED functions to be extended to the control panel of the system where they are visible The serial ports on the controller are connected to four 8 pin RJ45 female connectors J17 on the front panel The two IPs connect to the controller by two pairs of 50 pin connectors The two 50 pin connectors behind the front panel are for external connections to IP signals The memory mez...

Page 39: ...mory map is split into different address spaces by the transfer type TT signals The local resources respond to the normal access and interrupt acknowledge codes Normal Address Range The memory map of devices that respond to the normal address range is shown in the following tables The normal address range is defined by the Transfer Type TT signals on the local bus On the MVME162LX Embedded Control...

Page 40: ... 7 Programmable SRAM on Mezzanine D32 2MB N 2 7 Programmable VMEbus A32 A24 D32 D16 Y N 4 Programmable IP_a Memory D32 D8 64KB 8MB Y N 2 4 Programmable IP_b Memory D32 D8 64KB 8MB Y N 2 4 FF800000 FF9FFFFF Flash EPROM D32 2MB N 1 5 FFA00000 FFBFFFFF EPROM Flash D32 2MB N 5 FFC00000 FFDFFFFF Not Decoded D32 2MB N 7 FFE00000 FFE1FFFF On Board SRAM Default D32 128KB N 7 FFE80000 FFEFFFFF Not Decoded ...

Page 41: ... Embedded Controller Programmer s Reference Guide for additional information 3 This area is user programmable The DRAM and SRAM decoder is programmed in the MCchip the local to VMEbus decoders are programmed in the VMEchip2 and the IP memory space is programmed in the IPIC 4 Size is approximate 5 Cache inhibit depends on the devices in the area mapped 6 The EPROM and Flash are dynamically sized by...

Page 42: ...56 KB 4 FFF40000 FFF400FF VMEchip2 LCSR D32 256 B 1 3 FFF40100 FFF401FF VMEchip2 GCSR D32 D8 256 B 1 3 FFF40200 FFF40FFF Reserved 3 5 KB 4 5 FFF41000 FFF41FFF Reserved 4 KB 4 FFF42000 FFF42FFF MCchip D32 D8 4 KB 1 FFF43000 FFF430FF MCECC 1 D8 256 B 1 9 FFF43100 FFF431FF MCECC 2 D8 256 B 1 9 FFF43200 FFF43FFF MCECCs repeated 3 5 KB 1 5 9 FFF44000 FFF44FFF Reserved 8 KB 4 FFF45000 FFF45800 SCC 1 Z85...

Page 43: ...erved 128 B 1 FFF58900 FFF5897F Reserved 128 B 1 FFF58980 FFF589FF Reserved 128 B 1 FFF58A00 FFF58A7F Reserved 128 B 1 FFF58A80 FFF58AFF Reserved 128 B 1 FFF58B00 FFF58B7F Reserved 128 B 1 FFF58B80 FFF58BFF Reserved 128 B 1 FFF58C00 FFF58CFF Reserved 256 B 1 FFF58D00 FFF58DFF Reserved 256 B 1 FFF58E00 FFF58EFF Reserved 256 B 1 FFF58F00 FFF58FFF Reserved 256 B 1 FFFBC000 FFFBC01F IPIC Registers D32...

Page 44: ...read the interrupt vector 4 This area does not return an acknowledge signal If the local bus timer is enabled the access times out and is terminated by a TEA signal 5 Size is approximate 6 Port commands to the 82596CA must be written as two 16 bit writes upper word first and lower word second 7 Refer to the Flash and EPROM Interface section in the MCchip description in Chapter 3 8 Not used 9 To us...

Page 45: ...d modify write operations should be used to modify a byte or a two byte of a register Each register definition includes a table with 5 lines Line 1 is the base address of the register and the number of bits defined in the table Line 2 shows the bits defined by this table Line 3 defines the name of the register or the name of the bits in the register Line 4 defines the operations possible on the re...

Page 46: ...MASTER ENDING ADDRESS 4 MASTER ADDRESS TRANSLATION ADDRESS 4 VMEchip2 LCSR Base Address FFF40000 OFFSET 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 MAST D16 EN MAST WP EN MAST D16 EN MAST WP EN MASTER AM 3 MASTER AM 4 GCSR GROUP SELECT GCSR BOARD SELECT MAST 4 EN MAST 3 EN MAST 2 EN MAST 1 EN TICK 2...

Page 47: ...DDRESS TRANSLATION SELECT 2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 IO2 EN IO2 WP EN IO2 S U IO2 P D IO1 EN IO1 D16 EN IO1 WP EN IO1 S U 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 MASTER AM 2 MASTER AM 1 ROM SIZE ROM BANK B SPEED ROM BANK A SPEED DMA TBL INT DMA LB SNP MODE DMA INC VME DMA INC LB DMA D64 BLK DMA BLK DMA AM 5 DMA AM 4 DMA WRT DMA D16 DMA AM 3 DMA AM 2...

Page 48: ...WP BERR IRQ PE IRQ IRQ1E IRQ TIC2 IRQ TIC1 IRQ VME IACK IRQ DMA IRQ SIG3 IRQ SIG2 IRQ SIG1 IRQ SIG0 IRQ LM1 IRQ LM0 IRQ ABORT IRQ LEVEL SYS FAIL IRQ LEVEL MST WP ERROR IRQ LEVEL VME IACK IRQ LEVEL DMA IRQ LEVEL SIG 3 IRQ LEVEL SIG 2 IRQ LEVEL SW7 IRQ LEVEL SW6 IRQ LEVEL SW5 IRQ LEVEL SW4 IRQ LEVEL SPARE IRQ LEVEL VME IRQ 7 IRQ LEVEL VME IRQ 6 IRQ LEVEL VME IRQ 5 IRQ LEVEL VECTOR BASE REGISTER 0 VE...

Page 49: ...3 CLR IRQ 12 CLR IRQ 11 CLR IRQ 10 CLR IRQ 9 CLR IRQ 8 SET IRQ 15 SET IRQ 14 SET IRQ 13 SET IRQ 12 SET IRQ 11 SET IRQ 10 SET IRQ 9 SET IRQ 8 SW7 IRQ SW6 IRQ SW5 IRQ SW4 IRQ SW3 IRQ SW2 IRQ SW1 IRQ SW0 IRQ SPARE VME IRQ7 VME IRQ6 VME IRQ5 VME IRQ4 VME IRQ3 VME IRQ2 VME IRQ1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 GPIOO P ERROR IRQ LEVEL IRQ1E IRQ LEVEL TIC TIMER 2 IRQ LEVEL TIC TIMER 1 IRQ LEVEL SW3 ...

Page 50: ...trol 1C DRAM Parity Error Interrupt Control SCC Interrupt Control Tick Timer 4 Control Tick Timer 3 Control 20 DRAM Space Base Address Register SRAM Space Base Address Register 24 DRAM Space Size DRAM SRAM Options SRAM Space Size Reserved 28 LANC Error Status Reserved LANC Interrupt Control LANC Bus Error Interrupt Control 2C SCSI Error Status General Purpose Inputs MVME162LX Version SCSI Interrup...

Page 51: ...RL BAD23 BAD22 RWB5 SWAIT RWB3 NCEIEN NCEBE N RAMEN 1C BCLK FREQ BCK7 BCK6 BCK5 BCK4 BCK3 BCK2 BCK1 BCK0 20 DATA CONTRL 0 0 DERC ZFILL RWCKB 0 0 0 24 SCRUB CNTRL RACOD E RADAT A HITDIS SCRB SCRBE N 0 SBEIEN IDIS 28 SCRUB PERIOD SBPD15 SBPD14 SBPD13 SBPD12 SBPD11 SBPD10 SBPD9 SBPD8 2C SCRUB PERIOD SBPD7 SBPD6 SBPD5 SBPD4 SBPD3 SBPD2 SBPD1 SBPD0 30 CHIP PRESCALE CPS7 CPS6 CPS5 CPS4 CPS3 CPS2 CPS1 CP...

Page 52: ...B ERA EALT 0 MBE SBE 60 ERROR ADDRESS EA31 EA30 EA29 EA28 EA27 EA26 EA25 EA24 64 ERROR ADDRESS EA23 EA22 EA21 EA20 EA19 EA18 EA17 EA16 68 ERROR ADDRESS EA15 EA14 EA13 EA12 EA11 EA10 EA9 EA8 6C ERROR ADDRESS EA7 EA6 EA5 EA4 0 0 0 0 70 ERROR SYNDROME S7 S6 S5 S4 S3 S2 S1 S0 74 DEFAULTS1 WRHDI S STATC OL FSTRD SELI1 SELI0 RSIZ2 RSIZ1 RSIZ0 78 DEFAULTS2 FRC_OP N XY_FLI P REFDIS TVECT NOCAC HE RESST2 R...

Page 53: ...tion register Writes to the System Configuration Pointer must be upper word first lower word second Table 1 9 Z85230 SCC Register Addresses SCC SCC Register Address SCC 1 Port B Control FFF45001 Port B Data FFF45003 Port A Control FFF45005 Port A Data FFF45007 SCC 2 Port B Control FFF45801 Port B Data FFF45803 Port A Control FFF45805 Port A Data FFF45807 Table 1 10 82596CA Ethernet LAN Memory Map ...

Page 54: ... Address is FFF47000 Big Endian Mode SCRIPTs and Little Endian Mode 00 SIEN SDID SCNTL1 SCNTL0 00 04 SOCL SODL SXFER SCID 04 08 SBCL SBDL SIDL SFBR 08 0C SSTAT2 SSTAT1 SSTAT0 DSTAT 0C 10 DSA 10 14 CTEST3 CTEST2 CTEST1 CTEST0 14 18 CTEST7 CTEST6 CTEST5 CTEST4 18 1C TEMP 1C 20 LCRC CTEST8 ISTAT DFIFO 20 24 DCMD DBC 24 28 DNAD 28 2C DSP 2C 30 DSPS 30 34 SCRATCH 34 38 DCNTL DWT DIEN DMODE 38 3C ADDER ...

Page 55: ... KB 16 MB Programmable IP_d Memory Space D16 D8 64 KB 8 MB FFF58000 FFF5807F IP_a I O Space D16 128 B FFF58080 FFF580BF IP_a ID Space D16 64 B FFF580C0 FFF580FF IP_a ID Space Repeated D16 64 B FFF58100 FFF5817F IP_b I O Space D16 128 B FFF58180 FFF581BF IP_b ID Space D16 64 B FFF581C0 FFF581FF IP_b ID Space Repeated D16 64 B FFF58200 FFF5827F IP_c I O Space D16 128 B FFF58280 FFF582BF IP_c ID Spac...

Page 56: ...0 b_BASE19 b_BASE18 b_BASE17 b_BASE16 08 IP_c MEM BASE UPPER c_BASE31 c_BASE30 c_BASE29 c_BASE28 c_BASE27 c_BASE26 c_BASE25 c_BASE24 09 IP_c MEM BASE LOWER c_BASE23 c_BASE22 c_BASE21 c_BASE20 c_BASE19 c_BASE18 c_BASE17 c_BASE16 0A IP_d MEM BASE UPPER d_BASE31 d_BASE30 d_BASE29 d_BASE28 d_BASE27 d_BASE26 d_BASE25 d_BASE24 0B IP_d MEM BASE LOWER d_BASE23 d_BASE22 d_BASE21 d_BASE20 d_BASE19 d_BASE18 ...

Page 57: ...ENERAL CONTROL c_ERR 0 c_RT1 c_RT0 c_WIDTH1 c_WIDTH0 0 c_MEN 1B IP_b GENERAL CONTROL d_ERR 0 d_RT1 d_RT0 d_WIDTH1 d_WIDTH0 0 d_MEN 1C RESERVED 0 0 0 0 0 0 0 0 1D RESERVED 0 0 0 0 0 0 0 0 1E RESERVED 0 0 0 0 0 0 0 0 1F IP RESET 0 0 0 0 0 0 0 RES Table 1 14 MK48T08 BBRAM TOD Clock Memory Map Address Range Description Size Bytes FFFC0000 FFFC0FFF User Area 4096 FFFC1000 FFFC10FF Networking Area 256 F...

Page 58: ...F3E FFFC1F45 Memory Mezzanine Serial Number 8 FFFC1F46 FFFC1F4D Serial Port 2 Personality PWB 8 FFFC1F4E FFFC1F55 Serial Port 2 Personality Serial No 8 FFFC1F56 FFFC1F5D IP_a Board ID 8 FFFC1F5E FFFC1F65 IP_a Board Serial Number 8 FFFC1F66 FFFC1F6D IP_a Board PWB 8 FFFC1F6E FFFC1F75 IP_b Board ID 8 FFFC1F76 FFFC1F7D IP_b Board Serial Number 8 FFFC1F7E FFFC1F85 IP_b Board PWB 8 FFFC1F86 FFFC1F8D IP...

Page 59: ...top BitFT Frequency Testx Unuse Table 1 16 TOD Clock Memory Map Data Bits Address D7 D6 D5 D4 D3 D2 D1 D0 Function FFFC1FF8 W R S CONTROL FFFC1FF9 ST SECONDS 00 FFFC1FFA x MINUTES 00 FFFC1FFB x x HOUR 00 FFFC1FFC x FT x x x DAY 01 FFFC1FFD x x DATE 01 FFFC1FFE x x x MONTH 01 FFFC1FFF YEAR 00 ...

Page 60: ... used by the MVME162LX board debugger 162Bug The fifth area detailed in Table 1 15 is the configuration area The sixth area the TOD clock detailed in Table 1 16 is defined by the chip hardware The data structure of the configuration bytes starts at FFFC1EF8 and is as follows struct brdi_cnfg char version 4 char serial 12 char id 16 char pwa 16 char speed 4 char ethernet 6 char fill 2 char lscsiid ...

Page 61: ...byfive blanks 4 Sixteen bytes are reserved for the printed wiring assembly PWA number assigned to this board in ASCII format This includes the 01 W prefix This is for the main logic board if more than one board is required for a set Additional boards in a set are defined by a structure for that set For example for an MVME162LX board with MC68040 SCSI Ethernet 4MB DRAM and 128 KB SRAM at revision A...

Page 62: ...re reserved for the serial number in ASCII format assigned to the optional first IndustryPack a 15 Eight bytes are reserved for the printed wiring board PWB number assigned to the optional first IndustryPack a 16 Eight bytes are reserved for the board identifier in ASCII format assigned to the optional second IndustryPack b 17 Eight bytes are reserved for the serial number in ASCII format assigned...

Page 63: ... cycles by placing the binary value 11 on TT1 TT0 It also specifies the level that is being acknowledged using TM2 TM0 The interrupt handler selects which device within that level is being acknowledged VMEbus Memory Map This section describes the mapping of local resources as viewed by VMEbus masters Default addresses for the slave master and GCSR address decoders are provided by the ENV command R...

Page 64: ...the controller s onboard registers as given in the MVME162LX Embedded Controller Programmer s Reference Guide Multi MPU Programming Considerations Good programming practice dictates that only one MPU at a time have control of the MVME162LX control registers Of particular note are Registers that modify the address map Registers that require two cycles to access VMEbus interrupt request registers Lo...

Page 65: ... processor is halted or the local bus is hung and reset is the last resort Any VMEbus access to the MVME162LX Embedded Controller while it is in the reset state is ignored If a global bus timer is enabled a bus error is generated EMC Compliance The MVME162LX Embedded Controller was tested in an EMC compliant chassis and meets the requirements for Class B equipment CE compliance mark was achieved u...

Page 66: ...1 52 Computer Group Literature Center Web Site Board Level Hardware Description 1 ...

Page 67: ...ely protected working surface Refer to the packing list and verify that all items are present Save the packing material for storing and reshipping of equipment Hardware Preparation To select the desired configuration and ensure proper operation of the controller certain option modifications may be necessary before installation The controller provides software control for many of these options Some...

Page 68: ...M Flash configuration J12 SRAM backup power source selection for onboard SRAM J13 on the MVME162LX PCB for the SRAM mezzanine J1 on the SRAM mezzanine SCSI bus termination J14 System Controller Select Header J1 The MVME162LX Embedded Controller is factory configured as a VMEbus system controller a jumper is installed across pins 1 and 2 of PCB header J1 Remove the J1 jumper if the controller is no...

Page 69: ... F1 F2 F3 F4 F5 F3 F6 P1 P2 J11 J12 15 16 15 16 1 2 1 2 A1 B1 C1 A32 B32 C32 1 2 99 100 J16 1 2 99 100 1 2 1 6 5 J13 J14 68 36 33 1 34 2 67 35 J10 15 9 8 1 J9 J3 49 50 1 2 J2 19 20 1 2 J4 49 50 1 2 S1 S2 J1 1 2 24 50 49 25 2 26 27 1 J5 24 50 49 25 2 26 27 1 J7 24 50 49 25 2 26 27 1 J6 24 50 49 25 2 26 27 1 J8 A1 B1 C1 A32 B32 C32 XU21 SKT XU21 SKT XU22 SKT XU22 SKT XU23 SKT XU23 SKT XU24 SKT XU24 ...

Page 70: ... Pins 7 8 GPI 3 are reserved to select either the Flash memory map jumper installed or the EPROM memory map jumper removed They are not user definable The address ranges for the various EPROM Flash configurations appear in the next section of this chapter The controller is shipped from the factory with J11 set to all zeros jumpers on all pins except for GPI 3 J11 15 GPI 0 GPI 1 GPI 2 GPI 6 GPI 3 G...

Page 71: ...d JEDEC 32 pin DIP sockets that accommodate four jumper selectable densities 128 Kbit x 8 256 Kbit x 8 512 Kbit x 8 1 Mbit x 8 and permit disabling of the flash memory Header J12 provides eight jumpers to configure the EPROM sockets J12 15 1 2 16 J12 15 1 2 16 J12 15 1 2 16 J12 15 1 2 16 J12 15 1 2 16 CONFIGURATION 1 128K x 8 EPROMs CONFIGURATION 2 256K x 8 EPROMs CONFIGURATION 5 1M x 8 EPROMs WIT...

Page 72: ...0 FF85FFFF EPROM C XU22 FF860000 FF87FFFF EPROM D XU21 FFA00000 FFBFFFFF On Board Flash Installed 0 FF800000 FF9FFFFF On Board Flash FFA00000 FFA1FFFF EPROM A XU24 FFA20000 FFA3FFFF EPROM B XU23 FFA40000 FFA5FFFF EPROM C XU22 FFA60000 FBA7FFFF EPROM D XU21 Table 2 2 EPROM Flash Mapping 256K x 8 EPROMs GPI 3 Address Range Device Accessed Removed 1 FF800000 FF83FFFF EPROM A XU24 FF840000 FF87FFFF EP...

Page 73: ...0 FF9FFFFF On Board Flash FFA00000 FFA7FFFF EPROM A XU24 FFA80000 FFAFFFFF EPROM B XU23 FFB00000 FFB7FFFF EPROM C XU22 FFB80000 FBF7FFFF EPROM D XU21 Table 2 4 EPROM Flash Mapping 1M x 8 EPROMs GPI 3 Address Range Device Accessed Removed 1 FF800000 FF8FFFFF EPROM A XU24 FF900000 FF9FFFFF EPROM B XU23 Not used EPROM C XU22 Not used EPROM D XU21 FFA00000 FFBFFFFF On Board Flash Installed 0 FF800000 ...

Page 74: ... GPI 3 Address Range Device Accessed Removed 1 FF800000 FF8FFFFF EPROM A XU24 FF900000 FF9FFFFF EPROM B XU23 FFA00000 FFAFFFFF EPROM C XU22 FFB00000 FFBFFFFF EPROM D XU21 Not used On Board Flash Installed 0 Not used On Board Flash FF800000 FF8FFFFF EPROM A XU24 FF900000 FF9FFFFF EPROM B XU23 FFA00000 FFAFFFFF EPROM C XU22 FFB00000 FFBFFFFF EPROM D XU21 ...

Page 75: ...ower source the onboard battery is disconnected Notes For controllers without the optional VMEbus interface without the VMEchip2 ASIC you must select the onboard battery as the backup power source Caution Removing all jumpers may temporarily disable the SRAM Do not remove all jumpers from J13 except for storage J13 Factory configuration 2 1 J13 Backup Power Disabled Primary Source Onboard Battery ...

Page 76: ...e jumper from J1 except for storage SCSI Terminator Enable Header J14 The controller provides terminators for the SCSI bus The SCSI terminators are enabled disabled by a jumper on header J14 The SCSI terminators may be configured as follows Caution If the controller is to be used at one end of the SCSI bus the SCSI bus terminators must be enabled 1 2 3 1 2 3 J1 Factory configuration 1 J1 Backup Po...

Page 77: ...g connector options govern stacking arrangements The 4 MB and 8 MB boards has connectors on the top and bottom primary and secondary sides of the board It can be used as follows Individually as the only mezzanine board with nothing stacked on top Stacked with another 4 MB or 8 MB board on top Stacked with either an 8 MB or 32 MB board on top The 8 MB or 32 MB board has connectors on the bottom onl...

Page 78: ...ure 2 1 for the connector locations Orient the IP s so that the tapered connector shells mate properly Plug IP_a into connectors J5 and J6 plug IP_b into J7 and J8 If a double sized IP is used plug IP_ab into J5 J6 J7 and J8 Two additional 50 pin connectors J3 and J4 are provided behind the controller s front panel for external cabling connections to the IP modules There is a one to one correspond...

Page 79: ...over as instructed in the user s manual for the equipment 3 Remove the filler panel from the card slot where you are going to install the controller If you intend to use the MVME162LX as system controller it must occupy the leftmost card slot slot 1 The system controller must be in slot 1 to correctly initiate the bus grant daisy chain and to ensure proper operation of the IACK daisy chain driver ...

Page 80: ...P2 connectors on the VMEbus backplane P2 is also used for the upper 16 bits of data in 32 bit transfers and for the upper 8 address lines in extended addressing mode The controller may not operate properly without its main board connected to VMEbus backplane connectors P1 P2 Whether the controller operates as a VMEbus master or as a VMEbus slave it is configured for 32 bits of address and 32 bits ...

Page 81: ...ow one controller processor to broadcast a signal to any other controller processors All eight registers are accessible from any local processor as well as from the VMEbus The controller provides 5 Vdc power to the remote LED switch connector J2 as well as to IP_b through a 2A fuse F3 located near J7 Connector J2 is the interface for a remote control and indicator panel If none of the LEDs light a...

Page 82: ...strictlyasynchronous The Z85230 is interfaced as DTE data terminal equipment with EIA 232 D signal levels The serial ports are routed to four RJ45 connectors on the front panel This chapter provides connection diagrams for the four serial ports on the controller These ports are connected to external devices through cables connected to the front panel The figures showing this are as follows Figure ...

Page 83: ...to RJ45 Adapter Figure 2 4 diagrams the pin assignments required in a typical eight conductor serial cable having RJ45 connectors at both ends Note that all wires are crossed Figure 2 4 Typical RJ45 Serial Cable TXD RXD RTS CTS DTR DCD 1 2 3 4 5 6 7 8 DB25 DCE DEVICE RJ45 JACK 6 8 4 2 3 7 5 20 DSR SG RXD TXD CTS RTS DCD DTR 1 2 3 4 5 6 7 8 RJ45 CONNECTOR RJ45 CONNECTOR 8 7 5 4 6 2 1 SG 3 SG ...

Page 84: ...2 18 Computer Group Literature Center Web Site Hardware Preparation and Installation 2 ...

Page 85: ...sassembler useful for patching programs and a power up self test which verifies the integrity of the system Various 162Bug routines that handle I O data conversion and string functions are available to user programs through the TRAP 15 system calls The 162Bug consists of three parts 1 A command driven user interactive software debugger referred to as the debugger Its usage is described in Chapter ...

Page 86: ...ore of Motorola s other debugging packages you will find the CISC 162Bug very similar Some effort has also been made to make the interactive commands more consistent For example delimiters between commands and arguments may now be commas or spaces interchangeably 162Bug Implementation The 162Bug is written mostly in the C programming language providing the benefits of portability and maintainabili...

Page 87: ...11 affect the 162Bug operation as listed below The default condition for the controller MVME162 2xx is with seven jumpers installed This is between pins 1 2 3 4 5 6 9 10 11 12 13 14 and 15 16 No jumper is installed on pins 7 8 These readable jumpers can be read as a register at FFF4202D on the Memory Controller ASIC MCchip The bit values are read as a one when the jumper is removed off and as a ze...

Page 88: ...its work page i e variables stack vector tables etc Bit 1 GPI1 3 4 When this bit is a one high it instructs the debugger to use the default setup operation parameters in flash memory or ROM versus the user setup operation parameters in Non Volatile RAM NVRAM This is the same as depressing the RESET and ABORT switches at the same time This feature can be used in the event the user setup is corrupte...

Page 89: ... characters check the terminal to ensure XON XOFF handshaking is enabled 5 If you want to connect devices such as a host computer system and or serial printer to the other EIA 232 D port connectors you must connect the appropriate cables and configure the port s as shown in step 4 above After power up this these port s can be reconfigured by programming the MVME162LX Z85230 Serial Communications C...

Page 90: ...boot is a software routine that is contained in the 162Bug Flash PROM to provide an independent mechanism for booting an operating system This autoboot routine automatically scans for controllers and devices in a specified sequence until a valid bootable device containing the boot media is found or the list is exhausted If a valid bootable device is found a system boot from that device is started ...

Page 91: ...an EPROM installed in socket XU24 This leaves three sockets XU21 XU23 and the flash available for your use Contact your Motorola sales office for assistance This function is configured enabled by the Environment ENV command refer to Appendix A and executed at power up optionally also at reset or by the RB command assuming there is valid code in the memory devices or optionally elsewhere on the con...

Page 92: ...t device is started The controller scanning sequence goes from the lowest controller Logical Unit Number LUN detected to the highest LUN detected Refer to Appendix C for default LUNs At power up Network Boot is enabled and providing the drive and controller numbers encountered are valid the following message is displayed upon the system console Network Boot in progress To abort hit BREAK Following...

Page 93: ...efresh may be inhibited and memory contents may be lost To ensure that the contents of DRAM will not be altered press and release the RESET button as quickly as possible Pressing and releasing the controller s front panel RESET switch initiates a system reset COLD and WARM reset modes are available By default the 162Bug is in COLD mode During COLD reset a total system initialization takes place as...

Page 94: ...e remains intact Control is returned to the debugger Break A Break is generated by pressing and releasing the BREAK key on the terminal keyboard Break does not generate an interrupt The only time break is recognized is when characters are sent or received by the console port Break removes any breakpoints in your code and keeps the breakpoint table intact Break also takes a snapshot of the machine ...

Page 95: ...checked against known clock speeds and tolerances Memory Requirements The program portion of the 162Bug is approximately 512KB of code consisting of download debugger and diagnostic packages It is contained entirely in Flash or PROM The 162Bug executes from FF800000 whether in Flash or PROM If you remove the jumper at J11 pins 7 and 8 the address spaces of the Flash and PROM are swapped For the MV...

Page 96: ...he following control codes may be entered for limited command line editing Note The presence of the caret symbol before a character indicates that the Control CTRL key must be held down while striking the character key X cancel line The cursor is backspaced to the beginning of the line If the terminal port is configured with the hardcopy or TTY option refer to PF command then a carriage return and...

Page 97: ...ed and the type and number of devices attached to the controller module are kept in tables by the 162Bug Default values for these parameters are assigned at power up and cold start reset but may be altered as described in the section on default parameters later in this chapter Appendix B contains a list of the controllers presently supported as well as a list of the default configurations for each...

Page 98: ...r is non SCSI the probe simply returns a status of device present and unknown The device probe makes an entry into the device descriptor table with the pertinent data After an entry has been made the next time a probe is done it simply returns with device present status pointer to the device descriptor Disk I O via 162Bug Commands These following 162Bug commands are provided for disk I O Detailed ...

Page 99: ...ackets as defined by the particular controller directly IOC can also be used to look at the resultant device packet after using the IOP command BO Bootstrap Operating System BO reads an operating system or control program from the specified device into memory and then transfers control to it BH Bootstrap and Halt BH reads an operating system or control program from a specified device into memory a...

Page 100: ...vice Refer to the system call descriptions in the Debugging Package for Motorola 68K CISC CPUs User s Manual for additional information on the format and construction of these standardized user packets The packets which a controller module expects to be given vary from controller to controller The disk driver module for the particular hardware module board must take the standardized packet given t...

Page 101: ... and the parameters corresponding to that device are rewritten according to the parameter information contained in the configuration area This is a temporary change If a cold start reset occurs then the default parameter information is written back into the tables 2 Using the IOT command You can use this command to reconfigure the parameter table manually for any controller and or device that is d...

Page 102: ...bed in the following paragraphs Intel 82596 LAN Coprocessor Ethernet Driver This driver manages surrounds the Intel 82596 LAN Coprocessor Management is in the scope of the reception of packets the transmission of packets receive buffer flushing and interface initialization This module ensures that the packaging and unpackaging of Ethernet packets is done correctly in the Boot PROM UDP IP Protocol ...

Page 103: ... a file to be loaded into memory and executed TFTP Protocol Module The Trivial File Transfer Protocol TFTP is a simple protocol to transfer files It is implemented on top of the Internet User Datagram Protocol UDP or Datagram so it may be used to move files between machines on different networks implementing UDP The only thing it can do is read and write files from to a remote server Network Boot ...

Page 104: ...fset from the base address the debugger loads it at contains one of two longwords used to control communication between processors The MPCR contents are organized as follows The status codes stored in the MPCR are of two types 1 Status returned from the monitor 2 Status set by the bus master The status codes that may be returned from the monitor are You can only program flash memory by the MPCR me...

Page 105: ...comes to the prompt routine Before sending the prompt this routine places an R in the MPCR to indicate that initialization is complete Then the prompt is sent If no terminal is connected to the port the MPCR is still polled to see whether an external processor requires control to be passed to the dual port RAM If a terminal does respond the MPCR is polled for the same purpose while the serial port...

Page 106: ...ote processor then sets bit 8 SIG0 of the VMEchip2 LM SIG register This causes the controller to install breakpoints and begin execution The result is identical to the MPCR method with status code B described in the previous section The GCSR registers are accessed in the VMEbus short I O space Each general purpose register is two bytes wide occurring at an even address The general purpose register...

Page 107: ...at some diagnostics depend on restart defaults that are set up only in a particular restart mode The documentation for such diagnostics includes restart information Manufacturing Test Process During the manufacturing process for MVME162LX Embedded Controllers the manufacturing test parameters and testing state flags are stored in NVRAM These strings are installed during the manufacturing process a...

Page 108: ...3 24 Computer Group Literature Center Web Site Debugger General Information 3 ...

Page 109: ...n of user target code for example GO then control may or may not return to the debugger depending on what the user program does For example if a breakpoint has been specified then control returns to the debugger when the breakpoint is encountered during execution of the user program Alternately the user program could return to the debugger by means of the TRAP 15 function RETURN In general a debug...

Page 110: ...ic variable and is to be replaced by one of a class of items it represents A vertical bar separating two or more items indicates that a choice is to be made only one of the items separated by this symbol should be selected Square brackets enclose an item that is optional The item may appear zero or one time Braces enclose an optional symbol that may occur zero or more times DEL Delimiter either a ...

Page 111: ...literal of up to four characters The string literal must begin and end with the single quote mark The numeric value is interpreted as the concatenation of the ASCII values of the characters This value is right justified as any other numeric value would be Evaluation of an expression is always from left to right unless parentheses are used to group part of the expression There is no operator preced...

Page 112: ... accepted by the 162Bug is similar to the one accepted by the MC68040 one line assembler All control addressing modes are allowed An address offset register mode is also provided Address Formats Table 4 1 summarizes the address formats which are acceptable for address parameters in debugger command lines Expression Result In Hex Notes FF0011 FF0011 45 99 DE 45 99 90 35 67 10 5C 10011110 1001 A7 88...

Page 113: ...nt two formats accepted d An Xn or d An Xn 120 A1 D2 120 A1 D2 Address register indirect with index and displacement two formats accepted bd An Xn od C A2 A3 100 Memory indirect preindexed bd An Xn od 12 A3 D2 10 Memory indirect postindexed For the memory indirect modes fields can be omitted For example three of many permutations are as follows An od A1 4 bd FC1E bd Xn 8 D2 NOTES N Absolute addres...

Page 114: ...that is not the one at which they are loaded so it is harder to correlate addresses in the listing with addresses in the loaded program The offset registers solve this problem by taking into account this difference and forcing the display of addresses in a relative address offset format Offset registers have adjustable ranges and may even have overlapping ranges The range for each offset register ...

Page 115: ... 1 D0 9 0 0000000A 12D8 LOOP MOVE B A0 A1 10 0 0000000C 51C8FFFC MOVS DBRA D0 LOOP 11 0 00000010 4CDF0101 MOVEM L A7 D0 A0 12 0 00000014 4E75 RTS 13 14 END TOTAL ERRORS 0 TOTAL WARNINGS 0 The above program was loaded at address 0001327C The disassembled code is shown next 162Bug MD 1327C DI 0001327C 48E78080 MOVEM L D0 A0 A7 00013280 4280 CLR L D0 00013282 1018 MOVE B A0 D0 00013284 5340 SUBQ W 1 ...

Page 116: ... input or output Valid port numbers which may be used for these commands are as follows 1 MVME162LX EIA 232 D Debug Terminal Port 0 or 00 PORT 1 on the MVME162LX J17 front panel connector Sometimes known as the console port it is used for interactive user I O by default 2 MVME162LX EIA 232 D Terminal Port 1 or 01 PORT 2 on the MVME162LX J17 front panel connector Sometimes known as the host port th...

Page 117: ...ated using the 162Bug MM command as outlined above and stored to the host using the Dump DU command A communication link must exist between the host system and the MVME162LX port 1 Hardware configuration details are in the section on Installation and Startup in Chapter 3 The file is downloaded from the host to MVME162LX memory by the Load LO command Another way is by reading in the program from di...

Page 118: ...4KB of read write memory to operate The 162Bug reserves a 1024 byte area for a user program vector table area and then allocates another 1024 byte area and builds an exception vector table for the debugger itself to use Next 162Bug reserves space for static variables and initializes these static variables to predefined default values After the static variables 162Bug allocates space for the system...

Page 119: ...r handles one of the exceptions shown in Table 4 2 the target stack pointer is left pointing past the bottom of the exception stack frame created that is it reflects the system stack pointer values just before the exception occurred In this way the operation of the debugger facility through an exception is transparent to users Table 4 2 Exception Vectors Used by 162Bug Vector Offset Exception 162B...

Page 120: ...000 A4 00000000 A5 00000000 A6 00000000 A7 0000FFFC 00010006 D280 ADD L D0 D1 162Bug Notice that the value of the target stack pointer register A7 has not changed even though a trace exception has taken place Your program may either use the exception vector table provided by the 162Bug or it may create a separate exception vector table of its own The two following sections detail these two methods...

Page 121: ...ny modifications to the vectors contained in it Creating a New Vector Table Your program may create a separate vector table in memory to contain its exception vectors If this is done the program must change the value of the VBR to point at the new vector table In order to use the debugger facilities you can copy the proper vectors from the 162Bug vector table into the corresponding vector location...

Page 122: ...turn out that your program uses one or more of the exception vectors that are required for debugger operation Debugger facilities may still be used however if your exception handler can determine when to handle the exception itself and when to pass the exception to the debugger When an exception occurs which you want to pass on to the debugger i e ABORT your exception handler must read the vector ...

Page 123: ... L A0 D0 W 4 A6 Store address of debugger exc handler MOVEM L SP A0 A5 D0 D7 Restore registers UNLK A6 RTS Put addr of exc handler into PC and go 162Bug Generalized Exception Handler The 162Bug has a generalized exception handler which it uses to handle all of the exceptions not listed in Table 4 2 For all these exceptions the target stack pointer is left pointing to the top of the exception stack...

Page 124: ... 00010000 SR 2708 TR OFF_S _7_ N VBR 00000000 USP 0000DFFC MSP 0000EFFC ISP 0000FFFC SFC 0 F0 DFC 0 F0 CACR 0 D0 00000001 D1 00000001 D2 00000000 D3 00000000 D4 00000000 D5 00000002 D6 00000000 D7 00000000 A0 00000000 A1 00000000 A2 00000000 A3 00000000 A4 00000000 A5 00000000 A6 00000000 A7 0000FFC0 00010000 203900F0 0000 MOVE L F00000 L D0 162Bug Notice that the target stack pointer is different...

Page 125: ... observed 1 The sign field is the first field and is a binary field 2 The exponent field is the second field and is a hexadecimal field 3 The mantissa field is the last field and is a hexadecimal field 4 The sign field the exponent field and at least the first digit of the mantissa field must be present any unspecified digits in the mantissa field are set to zero 5 Each field must be separated fro...

Page 126: ...recision formats have an implied integer bit always 1 Extended Precision Real This format would appear in memory as An extended precision number takes 10 bytes in memory 1 bit sign field 1 binary digit 8 bit biased exponent field 2 hex digits Bias 7F 23 bit fraction field 6 hex digits 1 bit sign field 1 binary digit 11 bit biased exponent field 3 hex digits Bias 3FF 52 bit fraction field 13 hex di...

Page 127: ...of the specified data type Entering data in this format requires the following fields An optional sign bit or One decimal digit followed by a decimal point Up to 17 decimal digits at least one must be entered An optional exponent field that consists of An optional underscore The exponent field identifier letter E An optional exponent sign From 1 to 3 decimal digits For more information about the M...

Page 128: ...d their LUNs are listed in Appendix B or Appendix C All other command details are explained in the Debugging Package for Motorola 68K CISC CPUs User s Manual Table 4 3 Debugger Commands Command Mnemonic Title Command Line Syntax AB Automatic Bootstrap Operating System AB V NOAB No Autoboot NOAB AS One Line Assembler AS ADDR BC Block of Memory Compare BC RANGE DEL ADDR B W L BF Block of Memory Fill...

Page 129: ... Conversion DC EXP ADDR B O A DMA DMA Block of Memory Move DMA RANGE DEL ADDR DEL VDIR DEL AM DEL BLK B W L DS One Line Disassembler DS ADDR COUNT DEL ADDR DU Dump S records DU PORT DEL RANGE DEL TEXT DEL ADDR DEL OFFSET B W L ECHO Echo String ECHO PORT DEL hexadecimal number string ENV Set Environment to Bug Operating System ENV D GD Go Direct Ignore Breakpoints GD ADDR GN Go to Next Instruction ...

Page 130: ... MAE name line string MAL Enable Macro Expansion Listing MAL NOMAL Disable Macro Expansion Listing NOMAL MAW Save Macros MAW controller LUN DEL device LUN DEL block MAR Load Macros MAR controller LUN DEL device LUN DEL block MD Memory Display MD S ADDR COUNT ADDR B W L S D X P DI MENU Menu MENU MM Memory Modify MM ADDR B W L S D X P A N DI MMD Memory Map Diagnostic MMD RANGE DEL increment B W L MS...

Page 131: ...IOP NIOT Network I O Teach NIOT H A NPING Network Ping NPING Controller LUN Device LUN Source IP Destination IP N Packets OF Offset Registers Display Modify OF Rn A PA Printer Attach PA n NOPA Printer Detach NOPA n PF Port Format PF PORT NOPF Port Detach NOPF PORT PFLASH Program FLASH Memory PFLASH SSADDR SEADDR DSADDR IEADDR A R X or PFLASH SSADDR COUNT DSADDR IEADDR B W L A R X PS Put RTC Into P...

Page 132: ...n C SYM Symbol Table Attach SYM ADDR NOSYM Symbol Table Detach NOSYM SYMS Symbol Table Display Search SYMS symbol name S T Trace T COUNT TA Terminal Attach TA port TC Trace on Change of Control Flow TC count TIME Display Time and Date TIME C L O TM Transparent Mode TM n ESCAPE TT Trace to Temporary Breakpoint TT ADDR VE Verify S records Against Memory VE n ADDR X C text VER Display Revision Versio...

Page 133: ...d does not describe the elements and their use The board information block contents are checksummed for validation purposes This checksum is the last element of the block Although the factory fills all fields except the Industry Pack fields only these fields MUST contain correct information MPU clock speed Ethernet address Local SCSI identifier The board structure for the MVME162LX is as follows 1...

Page 134: ...ng Parameters that are not quoted are considered data strings and data strings are right justified The data strings are padded with zeroes if the length is not met In the event of corruption of the board information block the command displays a question mark for nondisplayable characters A warning message WARNING Board Information Block Checksum Error is also displayed in the event of a checksum f...

Page 135: ...rtain default values are assumed as stated below The bug operational parameters which are kept in NVRAM are not initialized automatically on power up warm reset It is up to the Bug user to invoke the ENV command Once the ENV command is invoked and executed without error Bug default and or user parameters are loaded into NVRAM along with checksum data If any of the operational parameters have been ...

Page 136: ...for Supported I O Controllers Y N Y Accesses will be made to the appropriate system busses e g VMEbus local MPU bus to determine presence of supported controllers Negate VMEbus SYSFAIL Always Y N N Negate VMEbus SYSFAIL after successful completion or entrance into the bug command monitor Local SCSI Bus Reset on Debugger Startup Y N N Local SCSI bus is not reset on debugger startup Local SCSI Bus N...

Page 137: ...e starting the boot The purpose for the delay is to allow you the option of stopping the boot by use of the Break key The time value is from 0 through 255 seconds Auto Boot Default String Y NULL String String You may specify a string filename which is passed on to the code being booted Maximum length is 16 characters Default is the null string ROM Boot Enable Y N N ROMboot function is disabled ROM...

Page 138: ...ule Network Auto Boot Enable Y N N Network Auto Boot function is disabled Network Auto Boot at power up only Y N Y Network Auto Boot is attempted at power up reset only Network Auto Boot Controller LUN 00 LUN of a disk tape controller module currently supported by the Bug Default is 0 Network Auto Boot Device LUN 00 LUN of a disk tape device currently supported by the Bug Default is 0 Network Auto...

Page 139: ...debuggers to operate simultaneously Memory Search Ending Address 00100000 Top limit of the Bug s search for a work page If a contiguous block of memory 64KB in size is not found in the range specified by Memory Search Starting Address and Memory Search Ending Address parameters then the bug will place its work page in the onboard static RAM on the MVME162LX Default Memory Search Ending Address is ...

Page 140: ...et In a multi 162LX environment where the work pages of several Bugs will reside in the memory of the primary first MVME162LX the non primary CPUs will wait for the data at the Memory Search Delay Address to be set to 00 01 or 02 refer to the Memory Requirements section in Chapter 3 for the definition of these values before attempting to locate their work page in the memory of the primary CPU Memo...

Page 141: ...of Dynamic Memory Parity and or ECC type memory It must be a multiple of the Dynamic Memory board size starting with 0 Default is 0 Size of Parity Memory 00100000 This is the size of the Parity type dynamic RAM mezzanine if any The default is the calculated size of the Dynamic memory mezzanine board Size of ECC Memory Board 0 00000000 This is the size of the first ECC type memory mezzanine The def...

Page 142: ...al resource that is accessible by the VMEbus Default is the base of local memory 0 Slave Ending Address 1 000FFFFF Ending address of the local resource that is accessible by the VMEbus Default is the end of calculated memory Slave Address Translation Address 1 00000000 This register will allow the VMEbus address and the local address to be different The value in this register is the base address o...

Page 143: ...he same as Slave Address Translation Select 1 Default is 0 Slave Control 2 0000 Defines the access restriction for the address space defined with this slave address decoder Default is 0000 Master Enable 1 Y N Y Yes setup and enable the Master Address Decoder 1 Master Starting Address 1 02000000 Base address of the VMEbus resource that is accessible from the local bus Default is the end of calculat...

Page 144: ...is 00000000 Master Control 2 00 Defines the access characteristics for the address space defined with this master address decoder Default is 00 Master Enable 3 Y N N Yes setup and enable the Master Address Decoder 3 This is the default if the board contains less than 16MB of calculated RAM Do not setup and enable the Master Address Decoder 3 This is the default for boards containing at least 16MB ...

Page 145: ...00 Ending address of the VMEbus resource that is accessible from the local bus Default is 0 Master Address Translation Address 4 00000000 This register will allow the VMEbus address and the local address to be different The value in this register is the base address of VMEbus resource that is associated with the starting and ending address selection from the previous questions Default is 0 Master ...

Page 146: ...ace defined with the F Page address decoder Default is 02 ROM Access Time Code 03 This defines the ROM access time The default is 03 which sets an access time of 180 ns Flash Access Time Code 02 This defines the FLASH access time The default is 02 which sets an access time of 140 ns MCC Vector Base VMEC2 Vector Base 1 VMEC2 Vector Base 2 05 06 07 Base interrupt vector for the component specified D...

Page 147: ...lobal Time Out Code 01 This controls the VMEbus timeout when the MVME162LX is systems controller Default 01 64 µs Local Bus Time Out Code 02 This controls the local bus timeout Default 02 256 µs VMEbus Access Time Out Code 02 This controls the local bus to VMEbus access timeout Default 02 32 µs Table A 1 ENV Command Parameters Continued ENV Parameter and Options Default Meaning of Default ...

Page 148: ...PIC chip on the MVME162LX Embedded Controller supports up to four IndustryPack interfaces designated IP_a through IP_d The controller itself accommodates two IPs IP_a and IP_b In the following discussion the segments applicable to IP_c and IP_d are not used in the controller IP A Base Address 00000000 IP B Base Address 00000000 IP C Base Address 00000000 IP D Base Address 00000000 Base address for...

Page 149: ...rol requirements for the IP modules channel 0 IP D C B A Interrupt 1 Control 00000000 Define the interrupt control requirements for the IP modules channel 1 Bits IP Register Address 31 24 D FFFBC01B 23 16 C FFFBC01A 15 08 B FFFBC019 07 00 A FFFBC018 Bits IP Register Address 31 24 D FFFBC016 23 16 C FFFBC014 15 08 B FFFBC012 07 00 A FFFBC010 Bits IP Register Address 31 24 D FFFBC017 23 16 C FFFBC01...

Page 150: ...le Overlap M Type Memory MAP Name 00000000 FFFFFFFF Yes Yes Master Local Memory DRAM FFE00000 FFE7FFFF Yes Yes Master Static RAM 01000000 EFFFFFFF Yes Yes Master VMEbus Master 1 00000000 00000000 No No Master VMEbus Master 2 00000000 00FFFFFF Yes Yes Master VMEbus Master 3 00000000 00000000 No No Master VMEbus Master 4 F0000000 FF7FFFFF Yes Yes Master VMEbus F Pages A24 A32 FFFF0000 FFFFFFFF Yes Y...

Page 151: ...econd one must have its address changed by its onboard jumpers and or switches so that it matches Second Address and can be called up by Second CLUN Notes If an MVME162LX Embedded Controller with a SCSI port is used then the controller has CLUN 0 For MVME162LX Embedded Controllers the first MVME320 has CLUN 11 and the second MVME320 has CLUN 12 Controller Type First CLUN First Address Second CLUN ...

Page 152: ...ontrollers 7 Devices MVME320 4 Devices Controller LUN Address Device LUN Device Type 0 XXXXXXXX 00 10 20 30 40 50 60 SCSI Common Command Set CCS which may be any of these Fixed direct access Removable flexible direct access TEAC style CD ROM Sequential access Controller LUN Address Device LUN Device Type 11 FFFFB000 0 1 2 3 Winchester hard drive Winchester hard drive 5 1 4 DS DD 96 TPI floppy driv...

Page 153: ...er hard drive ESDI Winchester hard drive ESDI Winchester hard drive 9 FFFFA200 ESDI Winchester hard drive Controller LUN Address Device LUN Device Type 2 FFFFA600 00 10 20 30 40 50 60 SCSI Common Command Set CCS which may be any of these Fixed direct access Removable flexible direct access TEAC style CD ROM Sequential access 3 FFFFA700 80 81 Local floppy drive Local floppy drive ...

Page 154: ...SCSI Common Command Set CCS which may be any of these Removable flexible direct access TEAC style CD ROM Sequential access 7 FFFF9800 16 FFFF4800 40 48 50 58 60 68 70 Same as above but these will only be available if the daughter card for the second SCSI channel is present 17 FFFF5800 18 FFFF7000 19 FFFF7800 Controller LUN Address Device LUN Device Type 4 FFFF5000 0 QIC 02 streaming tape drive 5 F...

Page 155: ...512 3 1024 4 2048 5 4096 1 1 1 1 1 1 1 Sectors Track 10 8 9 9 F 12 24 Number of Heads 2 2 2 2 2 2 2 Number of Cylinders 50 28 28 50 50 50 50 Precomp Cylinder 50 28 28 50 50 50 50 Reduced Write Current Cylinder 50 28 28 50 50 50 50 Step Rate Code 0 0 0 0 0 0 0 Single Double DATA Density D D D D D D D Single Double TRACK Density D D D D D D D Single Equal_in_all Track Zero Density S E E E E E E Slow...

Page 156: ...IOT Command Parameters for Supported Floppy Types B 6 Computer Group Literature Center Web Site B ...

Page 157: ...e debugger commands NBH NBO NIOP NIOC NIOT NPING and NAB and also with the debugger system calls NETRD NETWR NETFOPN NETFRD NETCFIG and NETCTRL Controller Type CLUN DLUN Address Interface Type MVME162LX 00 00 FFF46000 Ethernet MVME376 02 00 FFFF1200 Ethernet MVME376 03 00 FFFF1400 Ethernet MVME376 04 00 FFFF1600 Ethernet MVME376 05 00 FFFF5400 Ethernet MVME376 06 00 FFFF5600 Ethernet MVME376 07 00...

Page 158: ...C 2 Computer Group Literature Center Web Site C ...

Page 159: ... a modem in most cases Table D 1 Connector J17 Interconnect Signals Pin Number Signal Mnemonic Signal Name and Description 1 DCD Data Carrier Detect Output from modem to terminal to indicate that a valid carrier is being received 2 RTS Request To Send Input to modem from terminal when required to transmit a message With RTS off the modem carrier remains off When RTS is turned on the modem immediat...

Page 160: ...t receive data signals Because the serial clocks are omitted in the MVME162LX implementation serial communications are strictly asynchronous The Z85230 is interfaced as DTE data terminal equipment with EIA 232 D signal levels Figure D 1 shows the connections between the Z85230 and the RJ45 connectors Figure D 1 Serial Interface Connections TXD RXD RTS CTS DTR DCD TXC RXC 4 5 2 7 8 1 3 6 Z85230 RJ4...

Page 161: ... connectors Figure D 2 DB25 DTE to RJ45 Adapter Figure D 3 shows the pin assignments required in a cable to adapt a DB25 DCE device to the RJ45 connectors Figure D 3 DB25 DCE to RJ45 Adapter TXD RXD RTS CTS DTR DCD 1 2 3 4 5 6 7 8 DB25 DTE DEVICE RJ45 JACK 6 8 4 2 3 7 5 20 DSR SG TXD RXD RTS CTS DTR DCD 1 2 3 4 5 6 7 8 DB25 DCE DEVICE RJ45 JACK 8 4 2 3 7 5 20 SG ...

Page 162: ...re D 4 shows the pin assignments required in a typical eight conductor serial cable having RJ45 connectors at both ends Note that all wires are crossed Figure D 4 Typical RJ45 Serial Cable RXD TXD CTS RTS DCD DTR 1 2 3 4 5 6 7 8 RJ45 CONNECTOR RJ45 CONNECTOR 8 7 5 4 6 2 1 SG 3 SG ...

Page 163: ...ion 1 Ground 2 C Collision Ethernet input A signal to indicate that multiple stations are contending for access to the transmission medium 3 T Transmit Ethernet output A line intended for operation into terminated transmission lines 4 Ground 5 R Receive Ethernet input A data input sourced by the Medium Attachment Unit MAU 6 Ground 7 NC Not used 8 Ground 9 C Collision Ethernet input Part of a diffe...

Page 164: ...Ethernet Interconnections E 2 Computer Group Literature Center Web Site E ...

Page 165: ... 16 Return 17 18 TERMPWR Terminator Power 5 Vdc for SCSI terminators 19 NC Not used 20 34 DTRB Return 35 38 DB12 DB15 Data Bus bits 12 15 SCSI interconnect lines 39 DBP1 Data Bus Parity 1 parity for data bits 08 15 SCSI interconnect line 40 47 DB00 DB07 Data Bus bits 00 07 SCSI interconnect lines 48 DBP Data Bus Parity parity for data bits 00 07 SCSI interconnect line 49 50 Return 51 52 TERMPWR Te...

Page 166: ...C Data Command Driven by the target indicates whether control or data information is on the data bus True low indicates control information 63 REQ Request Driven by the target indicates a request for a REQ ACK data transfer handshake 64 O I Output Input Driven by a target controls the direction of data movement on the SCSI bus True low indicates input to the initiator False high indicates output f...

Page 167: ...15 Table G 1 Mezzanine Connector J15 Interconnect Signals Pin Number Signal Mnemonic Signal Direction Signal Name and Description 1 GND Ground 2 MPUCLK1 Input MPU Clock 1 Bus clock 25 MHz 3 4 GND Ground 5 PURESET Input Power Up Reset 6 LTS Bidirectional Local Transfer Start MC68040 transfer start strobe 7 LBRESET Input Local Bus Reset 8 GND Ground 9 LRD Bidirectional Local Read MC68040 read write ...

Page 168: ...onal Local Transfer Modifier 0 MC68040 transfer modifier attribute 22 MIACKIN Output Local IACK Daisy chain signal Assert MIACKIN if the IACK cycle is not for the mezzanine in question 23 LTM1 Bidirectional Local Transfer Modifier 1 MC68040 transfer modifier attribute 24 GND Ground 25 LTM2 Bidirectional Local Transfer Modifier 2 MC68040 transfer modifier attribute 26 LST0 Bidirectional Local Error...

Page 169: ...t line from mezzanine 35 GND Ground 36 MEZZIPL2 Output Mezzanine Interrupt Line 2 Encoded interrupt line from mezzanine 37 LTT1 Bidirectional Local Transfer Type 1 MC68040 transfer type attribute 38 MEZZBR Output Mezzanine Bus Request Local bus request from mezzanine 39 LMI Input Local Memory Inhibit MC68040 memory inhibit signal 40 GND Ground 41 LOCKOK Input Lock OK OK to start a locked bus cycle...

Page 170: ...bits 1 4 MC68040 address lines 56 GND Ground 57 58 LA 6 LA 5 Bidirectional Local Address bus bits 6 5 MC68040 address lines 59 GND GND Ground 60 63 LA 7 LA 10 Bidirectional Local Address bus bits 7 10 MC68040 address lines 64 GND Ground 65 66 LA 12 LA 11 Bidirectional Local Address bus bits 12 11 MC68040 address lines 67 GND Ground 68 71 LA 13 LA 16 Bidirectional Local Address bus bits 13 16 MC680...

Page 171: ...ress bus bits 25 28 MC68040 address lines 88 GND Ground 89 90 LA 30 LA 29 Bidirectional Local Address bus bits 30 29 MC68040 address lines 91 Reserved 92 LA 31 Bidirectional Local Address bus bit 31 MC68040 address line Bit 31 is the most significant bit 93 12 V 12 Vdc Power 94 12 V 12 Vdc Power 95 12 V 12 Vdc Power 96 12 V 12 Vdc Power 97 98 GND Ground 99 100 5 V 5 Vdc Power Table G 1 Mezzanine C...

Page 172: ...s Pin Number Signal Mnemonic Signal Direction Signal Name and Description 1 GND Ground 2 3 LD 1 LD 0 Bidirectional Local Data bus bits 1 0 MC68040 data lines Bit 0 is the least significant bit 4 5 LD 3 LD 2 Bidirectional Local Data bus bits 3 2 MC68040 data lines 6 GND Ground 7 8 LD 4 LD 5 Bidirectional Local Data bus bits 4 5 MC68040 data lines 9 GND Ground 10 11 LD 7 LD 6 Bidirectional Local Dat...

Page 173: ...al Local Data bus bits 25 24 MC68040 data lines 36 37 LD 27 LD 26 Bidirectional Local Data bus bits 27 26 MC68040 data lines 38 GND Ground 39 40 LD 28 LD 29 Bidirectional Local Data bus bits 28 29 MC68040 data lines 41 GND Ground 42 LD 30 Bidirectional Local Data bus bit 30 MC68040 data line 43 DRAM_PD0 Bidirectional DRAM Parity Data bit 0 Bit 0 is the least significant bit 44 LD 31 Bidirectional ...

Page 174: ...umn address line 54 RDRAM_A5 Input DRAM Address bit 5 Parity DRAM row column address line 55 RDRAM_A1 Input DRAM Address bit 1 Parity DRAM row column address line 56 RDRAM_A6 Input DRAM Address bit 6 Parity DRAM row column address line 57 RDRAM_A2 Input DRAM Address bit 2 Parity DRAM row column address line 58 GND Ground 59 RDRAM_A3 Input DRAM Address bit 3 Parity DRAM row column address line 60 R...

Page 175: ... Strobe line 2 Parity DRAM column address strobe 70 DRAMOE0 Input DRAM Output Enable line 0 Parity DRAM output enable signal 71 DRAMCAS3 Input DRAM Column Address Strobe line 3 Parity DRAM column address strobe 72 DRAMOE1 Input DRAM Output Enable line 1 Parity DRAM output enable signal 73 GND Ground 74 DRAMOE2 Input DRAM Output Enable line 2 Parity DRAM output enable signal 75 DRAMWELL Input DRAM ...

Page 176: ...le lines D31 D24 Parity DRAM write enable signal 85 SRAMCS0 Input SRAM Chip Select line 0 86 SRAMWEUU Input SRAM Write Enable lines D31 D24 87 SRAMCS1 Input SRAM Chip Select line 1 88 GND Ground 89 SRAMCS2 Input SRAM Chip Select line 2 90 SRAM_PA2 Input SRAM Address bit 2 91 SRAMCS3 Input SRAM Chip Select line 3 92 SRAM_PA3 Input SRAM Address bit 3 93 94 Reserved 95 GND Ground 96 5V STDBY 5 Vdc St...

Page 177: ...nting hole placement on the mezzanine boards used with the MVME162LX Embedded Controller They may be helpful in the event you wish to fabricate your own mezzanine boards for use with the controller Figure G 1 Mezzanine Board Dimensions Parity DRAM 3 400 0 185 PRI 0 265 PIN 1 2 475 BOTTOM CONNECTOR 3 025 3 011 0 084 0 100 DIA 2 965 P16 1 2 99 100 BOTTOM VIEW 0 125 2 PL ...

Page 178: ...ature Center Web Site G Figure G 2 Mezzanine Board Dimensions SRAM and ECC DRAM 4 725 3 400 0 185 PRI 0 265 PIN 1 0 125 2 PL 2 475 SEC TOP CONNECTOR BOTTOM CONNECTOR 5 255 PIN 1 3 025 3 011 0 084 4 634 0 100 2 PL P16 P15 1 2 99 100 1 2 99 100 BOTTOM VIEW ...

Page 179: ...he FUSES or RUN LED is not lit the board may not be getting correct power 1 Make sure the system is plugged in 2 Check that the board is securely installed in its backplane or chassis 3 Check that all necessary cables are connected to the board per this manual 4 Check for compliance with System Considerations per this manual 5 Review the Installation and Startup procedures per this manual This inc...

Page 180: ... per this manual 3 Remove the jumper from J11 pins 7 and 8 This enables the use of the EPROM instead of the Flash memory 3 Reconnect power 4 Restart the system by double button reset press the RESET and ABORT switches at the same time quickly release RESET wait seven seconds then release ABORT 5 If the debug prompt appears go to step IV or step V as indicated If the debug prompt does not appear go...

Page 181: ...be 162 Diag 6 You may need to use the cnfg command see your board Debugger Manual to change clock speed and or Ethernet Address and then later return to env CR and step 3 7 Run the selftests by typing in st CR The tests take as much as 10 minutes depending on RAM size They are complete when the prompt returns The onboard selftest is a valuable tool in isolating defects 8 The system may indicate th...

Page 182: ...are required VI The board has failed one or more of the tests listed above and cannot be corrected using the steps given A There may be some fault in the board hardware or the on board debugging and diagnostic firmware 1 Document the problem and return the board for service 2 Phone 1 800 222 5640 TROUBLESHOOTING PROCEDURE COMPLETE Table H 1 Troubleshooting MVME162LX Boards Continued Condition Poss...

Page 183: ...wer supplies furnishing operating voltages to the IndustryPack 2 CLK Clock An 8 MHz clock signal supplied to the IndustryPack by the controller Synchronizes all data transfers to or from the IndustryPack 3 Reset Reset Driven by the MVME162 to the IndustryPack to halt all IP activity and reset the IP circuitry to a known state 4 19 D0 D15 Data Bus bits 0 15 The 16 lines of the data bus used to read...

Page 184: ...n by the IndustryPack to indicate that the IP wishes to have a DMA cycle performed on DMA channel 0 31 MemSel Memory Select Second of four select lines driven by the MVME162 to enable the IP This line is used in memory read or write cycles MemSel is not bussed the signal is unique to each IndustryPack An IP need not respond to MemSel if it has no memory 32 DMAReq1 DMA Request 1 One of two DMA requ...

Page 185: ...he event of a a non recoverable error e g component failure Less serious errors are signaled by interrupts 41 A3 Address Line 3 One of six address lines driven by the MVME162 to address I O locations on the IndustryPack module designated by the four select lines 42 IntReq0 Interrupt Request 0 One of two interrupt request lines driven by an IndustryPack to indicate that the IP is requesting service...

Page 186: ... J4 to provide the I O 47 A6 Address Line 6 One of six address lines driven by the MVME162 to address I O locations on the IndustryPack module designated by the four select lines 48 Ack Data Acknowledge Asserted by an IndustryPack module to terminate each data transfer 49 5STBY 5 Vdc Standby Second of two 5V pins Available for standby functions on the IndustryPack such as non volatile memory real ...

Page 187: ...et switch and LED Table I 2 lists the pin numbers and signal mnemonics for connector J2 Table I 2 Remote Reset LED interconnect Signals Pin Number Signal Mnemonic 1 5VF 2 LAN LED 3 12V LED 4 SCSI LED 5 VME LED 6 NC 7 RUN LED 8 STS LED 9 FAIL STAT 10 NC 11 SCON LED 12 ABORT SW 13 RESET SW 14 GND 15 GND 16 GPIO 1 TO VME CHIP 17 GPIO 2 18 GPIO 3 19 NC 20 GND ...

Page 188: ...ectional data lines that provide the data path between the data transfer bus master and slave A9 GND Ground A10 SYSCLK System Clock A constant 16 MHz clock signal that is independent of processor speed or timing and is used as a timing reference A11 GND Ground A12 DS1 Data Strobe 1 A three state driven signal that indicates during byte and word transfers that a data transfer will occur on data bus...

Page 189: ...ted directly to ACKOUT on the controller A22 ACKOUT Interrupt Acknowledge Out See ACKIN pin A21 A23 AM4 Address Modifier bit 4 One of six input lines that provide additional information about the address bus such as size cycle type and or data transfer bus master identification A24 A27 A07 A04 Address Bus bits 7 4 Four of 31 three state input lines that specify an address in the memory map A28 A30...

Page 190: ... B10 BG3IN Bus Grant 3 In Same as BG0IN on pin B4 B11 BG3OUT Bus Grant 3 Out Same as BG0OUT on pin B5 B12 BR0 Bus Request level 0 One of four open collector driven signals generated by the bus requesters to request access to VMEbus B13 BR1 Bus Request level 1 Same as BR0 on pin B12 B14 BR2 Bus Request level 2 Same as BR0 on pin B12 B15 BR3 Bus Request level 3 Same as BR0 on pin B12 B16 B19 AM0 AM3...

Page 191: ...red during the data transfer cycle A low level indicates the slave may be active on the data bus C12 SYSRESET System Reset An open collector driven signal which when low will reset all modules in the system C13 LWORD Longword A three state driven signal specifying that the cycle is a byte word transfer when high or a longword transfer when low C14 AM5 Address Modifier bit 5 Same as AM4 on pin A23 ...

Page 192: ...gnificant bit and the highest priority during the arbitration phase A9 DBP Data Bus Parity SCSI Data parity is odd Use of parity is a system option Parity is not valid during the arbitration phase A10 ATN Attention SCSI Signal driven by the initiator Indicates the attention condition A11 BSY Bus Busy SCSI OR tied signal indicating that the bus is in use A12 ACK Acknowledge SCSI Signal driven by an...

Page 193: ...iately turns on the carrier A22 CTS3 EIA 232 D Clear to Send serial port 3 Output from modem to terminal to indicate that message transmission can begin When a modem is used CTS3 follows the off to on transition of RTS3 after a time delay A23 DTR3 EIA 232 D Data Terminal Ready serial port 3 Input to modem from terminal indicates that the terminal is ready to send or receive data A24 DCD3 EIA 232 D...

Page 194: ...dem B1 5V 5 Vdc Power Used by system logic circuits B2 GND Ground B3 Reserved Not used B4 B11 A24 A31 Address Bus bits 24 31 Eight of 31 three state lines that specify an address in the memory map They are driven by the MVME162 as a master and received by the controller as a slave B12 GND Ground B13 5V 5 Vdc Power Used by system logic circuits B14 B21 D16 D23 Data Bus bits 16 23 Eight of 32 bidire...

Page 195: ...RD6 Data bit 6 printer C16 PRD7 Data bit 7 printer C17 PRACK Data Acknowledge printer A low level input pulse indicating that the next character may be sent C18 PRBSY Busy printer An input signal indicating that the printer cannot receive data C19 PRPE Paper Empty printer Out of paper C20 PRSEL Selected printer An input signal indicating that the printer is selected C21 INPRIME Input Prime printer...

Page 196: ...ted from the receive line output from modem to terminal C29 RTS2 EIA 232 D Request to Send serial port 2 Input from modem to terminal when the modem is required to transmit a message With RTS2 off the modem carrier remains off When RTS2 is turned on the modem immediately turns on the carrier C30 CTS2 EIA 232 D Clear to Send serial port 2 Output from modem to terminal to indicate that message trans...

Page 197: ...n PDF and or HTML format from the Motorola Computer Group s World Wide Web site at http www mcg mot com literature Note Although not shown for each document in the following table Motorola Computer Group manual publications numbers are suffixed with characters which represent the revision level of the document such as xx2 the second revision of a manual a supplement bears the same number as a manu...

Page 198: ...NSI IEEE Std 1014 1987 The Institute of Electrical and Electronics Engineers Inc 345 East 47th Street New York NY 10017 VMEbus Specification This is also available as Microprocessor system bus for 1 to 4 byte data IEC 821 BUS Bureau Central de la Commission Electrotechnique Internationale 3 rue de Varembé Geneva Switzerland ANSI Small Computer System Interface 2 SCSI 2 Draft Document X3 131 198X R...

Page 199: ... 53C710 SCSI I O Processor Data Manual Document SCSIP 53C710 NCR Corporation Microelectronics Products Division Colorado Springs CO MK48T08 B Timekeeper TM and 8Kx8 Zeropower TM RAM data sheet in Static RAMs Databook order number DBSRAM71 SGS THOMPSON Microelectronics Group North South American Marketing Headquarters 1000 East Bell Road Phoenix AZ 85022 2699 28F008SA Flash Memory Data Sheet order ...

Page 200: ...J 4 Computer Group Literature Center Web Site J ...

Page 201: ...6 operating environment 4 10 port 0 or 00 4 8 port numbers 4 8 ports used 4 11 pseudo registers 4 6 relative address offset format 4 6 serial port 1 4 8 stack 3 12 syntactic variables 4 2 system routines 4 9 using the debugger 4 1 vector base register 4 11 vector table and workspace 4 10 vector tables 4 10 27C040 EPROM 3 2 5 1 4 DS DD 96 TPI floppy drive B 2 53C710 1 21 SCSI memory map 1 40 82596C...

Page 202: ...t 4 20 commands debug 4 20 configuration area 1 46 configuration default disk tape controller B 2 Configure CNFG and Environment ENV commands A 1 configure BIB A 1 debug parameters A 3 configuring base addresses of IndustryPacks A 16 IndustryPacks A 16 IndustryPacks A 3 VMEbus interface A 10 connectors 1 24 console port 4 8 control bit 1 10 control status registers 2 15 controller B 1 controller L...

Page 203: ... 2 5 mapping 128K x 8 EPROMs 2 6 256K x 8 EPROMs 2 6 1M x 8 EPROMs 2 7 selection 2 4 ESDI Winchester hard drive B 3 Ethernet 1 20 C 1 interface 1 6 1 20 signals E 1 station address 1 21 transceiver 2 15 examples address formats 4 4 exception handler usage 4 15 exception vector 4 12 numeric value expression 4 3 relocatable module 4 7 valid expressions 4 4 exception handler 4 15 vectors 4 11 exponen...

Page 204: ...tallation 2 12 specification J 2 installation 3 3 considerations 2 15 instructions 2 12 Intel 82596 LAN coprocessor Ethernet driver 3 18 interrupt acknowledge IACK 2 14 Interrupt Stack Pointer ISP 3 12 interrupts 1 23 IOC I O control 3 15 IOI input output inquiry 3 14 IOP physical I O to disk 3 15 IOT I O teach 3 15 command parameters for supported floppy types B 5 IP installation on the MVME162LX...

Page 205: ...or Address Register 3 21 Multiprocessor Control Register method 3 20 MVME162Bug 2 2 3 1 debugging package J 1 MVME162FX C 1 board level hardware features 1 1 block diagram 1 11 models 1 3 module installation 2 13 specifications 1 7 switch header connector fuse and LED locations 2 3 MVME320 Winchester Floppy Controller B 1 B 2 MVME323 ESDI Winchester Controller B 1 B 3 MVME327A SCSI Controller B 1 ...

Page 206: ...10 1 21 interface 1 6 1 21 signals F 1 specification J 2 termination 1 21 terminator configuration 1 21 2 10 terminator enable header J14 2 10 terminator power 1 22 2 15 SD command 3 23 sequential access device B 2 B 4 serial cable 2 17 D 3 communications 2 16 Communications Controllers 3 5 communications interface 1 19 interface signals D 1 port s 1 6 4 8 interface 1 19 Set Environment to Bug Ope...

Page 207: ...ransfer type TT signals 1 25 TRAP 15 4 9 troubleshooting procedures H 1 true 1 10 TT see transfer type 1 25 U UDP IP protocol modules 3 18 unpacking instructions 2 1 user definable jumpers 2 4 using 162Bug target vector table 4 12 V vector base register VBR 4 11 table creation 4 14 tables 4 12 4 13 VMEbus 1 19 accesses to the local bus 1 49 interface and VMEchip2 1 19 memory map 1 49 short I O mem...

Page 208: ...Index IN 8 Computer Group Literature Center Web Site I N D E X ...

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