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Motorola MTX series Programmer'S Reference Manual Download Page 105

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Raven PCI Host Bridge & Multi-Processor Interrupt Controller

2

Note

Because a deadlock condition can occur when the task register
priorities for each processor are the same and both processors are
targeted for interrupt delivery, the interrupt will be delivered to
processor 0 or processor 1 as determined by the TIE mode.

Block Diagram Description

The description of the block diagram focuses on the theory of operation for
the interrupt delivery logic. If the preceding section is a satisfactory
description of the interrupt delivery modes and the reader is not interested
the logic implementation, this section can be skipped.

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Summary of Contents for MTX series

Page 1: ...MTX Series Motherboard Programmer s Reference Guide MTXA PG4 January 2001 ...

Page 2: ...C 604TMare trademarks of IBM Corp and are used by Motorola Inc under license from IBM Corp AIXTM is a trademark of IBM Corp TimekeeperTM and ZeropowerTM are trademarks of Thompson Components Motorola and the Motorola symbol are registered trademarks of Motorola Inc All other products mentioned in this document are trademarks or registered trademarks of their respective holders ...

Page 3: ...ide the Equipment Operating personnel must not remove equipment covers Only Factory Authorized Service Personnel or other qualified service personnel may remove equipment covers for internal subassembly or component replacement or any internal adjustment Service personnel should not replace components with power cable connected Under certain conditions dangerous voltages may exist even with the po...

Page 4: ...losion if battery is replaced incorrectly Replace battery only with the same or equivalent type recommended by the equipment manufacturer Dispose of used batteries according to the manufacturer s instructions Attention Il y a danger d explosion s il y a remplacement incorrect de la batterie Remplacer uniquement avec une batterie du même type ou d un type équivalent recommandé par le constructeur M...

Page 5: ...tion of Conformity is available on request Please contact your sales representative Notice While reasonable efforts have been made to assure the accuracy of this document Motorola Inc assumes no liability resulting from any omissions in this document or from the use of the information obtained therein Motorola reserves the right to revise this document and to make changes from time to time in the ...

Page 6: ...d to in writing by Motorola Inc Use duplication or disclosure by the Government is subject to restrictions as set forth in subparagraph b 3 of the Rights in Technical Data clause at DFARS 252 227 7013 Nov 1995 and of the Rights in Noncommercial Computer Software and Documentation clause at DFARS 252 227 7014 Jun 1995 Motorola Inc Computer Group 2900 South Diablo Way Tempe Arizona 85282 ...

Page 7: ...1 5 PCI Memory Maps 1 10 MPC System Bus 1 13 Processors 1 13 Processor Type Identification 1 13 Processor PLL Configuration 1 13 Look Aside Cache 1 13 Falcon FLASH Memory 1 14 System Memory 1 14 Falcon Chipset 1 15 Falcon Registers 1 16 Falcon Controlled System Registers 1 16 System Configuration Register SYSCR 1 17 Memory Configuration Register MEMCR 1 18 System External Cache Control Register SX...

Page 8: ...O Port Pins 1 30 Two Wire Serial I2C Bus Controller 1 31 ISA DMA Channels 1 32 CHAPTER 2 Raven PCI Host Bridge Multi Processor Interrupt Controller Introduction 2 1 Overview 2 1 Requirements 2 1 Features 2 1 Block Diagram 2 3 Functional Description 2 4 PPC Bus Interface 2 4 PPC Map Decoders 2 4 PPC Write Posting 2 5 PPC Master 2 6 PPC Bus Timer 2 9 PCI Interface 2 9 PCI Map Decoders 2 9 PCI Config...

Page 9: ...PC Slave Offset Attribute 0 1 and 2 Registers 2 34 PPC Slave Offset Attribute 3 Registers 2 35 General Purpose Registers 2 36 PCI Registers 2 37 Vendor ID Device ID Registers 2 38 PCI Command Status Registers 2 39 Revision ID Class Code Registers 2 40 Header Type Register 2 41 I O Base Register 2 41 Memory Base Register 2 42 PCI Slave Address 0 1 2 and 3 Registers 2 43 PCI Slave Attribute Offset 0...

Page 10: ...ters 2 64 Spurious Vector Register 2 65 Timer Frequency Register 2 65 Timer Current Count Registers 2 66 Timer Basecount Registers 2 66 Timer Vector Priority Registers 2 67 Timer Destination Registers 2 68 External Source Vector Priority Registers 2 69 External Source Destination Registers 2 70 Raven Detected Errors Vector Priority Register 2 71 Raven Detected Errors Destination Register 2 72 Inte...

Page 11: ...Transfers 3 13 Completing Data Transfers 3 13 Data Parity 3 13 Cache Coherency 3 14 Cache Coherency Restrictions 3 14 L2 Cache Support 3 14 ECC 3 14 Cycle Types 3 15 Error Reporting 3 15 Error Logging 3 18 ROM Flash Interface 3 18 Refresh Scrub 3 22 Blocks A and or B Present Blocks C and D Not Present 3 22 Blocks A and or B Present Blocks C and or D Present 3 23 Chip Defaults 3 24 External Registe...

Page 12: ...ister 3 55 32 Bit Counter 3 56 Power Up Reset Status Register 1 3 56 Power Up Reset Status Register 2 3 57 External Register Set 3 57 Software Considerations 3 58 Parity Checking on the PowerPC Bus 3 58 Programming ROM Flash Devices 3 58 Writing to the Control Registers 3 58 Sizing DRAM 3 59 ECC Codes 3 62 Data Paths 3 64 CHAPTER 4 Programming Details Introduction 4 1 PCI Device Addressing 4 1 PCI...

Page 13: ...PCI SCSI 4 13 PCI Ethernet 4 13 ROM Flash Initialization 4 14 Determining PHB Type 4 14 Determining CPU Type 4 14 APPENDIX A Related Documentation Motorola Computer Group Documents A 1 Manufacturers Documents A 1 Related Specifications A 4 URLs A 5 ...

Page 14: ...ta Path for Reads from the Falcon Internal CSRs 3 25 Figure 3 5 Data Path for Writes to the Falcon Internal CSRs 3 26 Figure 3 6 Memory Map for Byte Reads to the CSR 3 27 Figure 3 7 Memory Map for Byte Writes to the Internal Register Set 3 28 Figure 3 8 Memory Map for 4 Byte Reads to the CSR 3 29 Figure 3 9 Memory Map for 4 Byte Writes to the Internal Register Set 3 29 Figure 3 10 PowerPC Data to ...

Page 15: ... 24 Table 1 16 Module Configuration and Status Registers 1 25 Table 1 17 Z8536 Z85230 Access Registers 1 30 Table 1 18 Z8536 CIO Port Pins Assignment 1 30 Table 1 19 I2C Controller Access Registers 1 31 Table 1 20 Two Wire Serial I2C Bus Addresses 1 32 Table 1 21 PIB DMA Channel Assignments 1 32 Table 2 1 CHRP Compliant Memory Map 2 4 Table 2 2 PPC Transfer Types 2 8 Table 2 3 PCI Command Codes 2 ...

Page 16: ...rations 3 36 Table 3 14 rtest encodings 3 45 Table 3 15 ROM Flash Block A Size Encoding 3 47 Table 3 16 rom_a_rv and rom_b_rv encoding 3 48 Table 3 17 Read Write to ROM Flash 3 49 Table 3 18 ROM Flash Block B Size Encoding 3 51 Table 3 19 Rom Speed Bit Encodings 3 52 Table 3 20 PowerPC 60x Address to DRAM Address Mappings 3 61 Table 3 21 Syndrome Codes Ordered by Bit in Error 3 62 Table 3 22 Singl...

Page 17: ... associated with this manual Summary of Changes The following table shows any changes made to this manual since its last release Model Number Description MTX603 001a 133 603 STANDARD I O 2 PMC MTX603 002a 200 603 STD OPT I O 2PMC MTX603 003a 200 603 STD OPT I O 3 PCI MTX604 001a 300 MHz 604 STANDARD I O 2 PMC MTX604 002a 300 MHz 604 STD OPT I O 2 PMC MTX604 003a 300 MHz 604 STD OPT I O 3 PCI MTX60...

Page 18: ...ails of several programming functions that are not tied to any specific ASIC chip Appendix A Related Documentation contains all documentation related to this product Comments and Suggestions Motorola welcomes and appreciates your comments on its documentation We want to know what you think about our manuals and how we can make them better Mail comments to Motorola Computer Group Reader Comments DW...

Page 19: ...to low transition Note In some places in this document an underscore _ following the signal name is used to indicate an active low signal In this manual assertion and negation are used to specify forcing a signal to a particular state In particular assertion and assert refer to a signal that is active or true negation and negate indicate a signal that is inactive or false These terms are used inde...

Page 20: ... that disables the function it controls In all tables the terms 0 and 1 are used to describe the actual value that should be written to the bit or the value that it yields when read The term status bit is used to describe a bit in a register that reflects a specific condition The status bit can be read by software to determine operational or exception conditions Conventions Used in This Manual The...

Page 21: ...xiii Enter Return or CR CR represents the carriage return or Enter key CTRL represents the Control key Execute control characters by pressing the Ctrl key and the letter simultaneously for example Ctrl d ...

Page 22: ...hip Set covers the Falcon chip set and Chapter 4 Programming Details covers certain programming features such as interrupts and exceptions Appendix A Related Documentation lists all related documentation Feature Summary There are many models based on the MTX series architecture The following table summarizes the major features of the MTX series Table 1 1 MTX Series Features Summary Feature Descrip...

Page 23: ...ce 32 64 bit Data up to 33 MHz operation Form Factor ATX Peripheral Support Two 16550 compatible async serial ports Two sync async serial ports One Host mode Parallel Port One Peripheral mode Parallel Port 8 bit or 16 bit single ended SCSI interface AUI or 10BaseT 100BaseTX Ethernet interface One PS 2 Keyboard and one PS 2 Mouse One PS 2 Floppy Port Two EIDE ports PCI PMC Expansion Build option fo...

Page 24: ...604e processors and dual 604e processors In the dual processor configuration the internal operating frequencies of the 604e s are independently configurable I O peripheral devices on the PCI bus are SCSI interface Ethernet interface two 64 bit PMC and one 64 bit PCI slot or three 32 bit PCI slots Functions provided from the ISA bus are two EIDE ports a host mode P1284 parallel port a peripheral mo...

Page 25: ...C PCI IC Raven ASIC Ethernet DEC21140 SCSI SYM53C875A PIB WINBOND Floppy 64 bit PMC Slot KBD Mouse ISA Registers RTC NVRAM WD MK48T59 Super I O PC87308 Rear Panel 64 bit PMC Slot 10 100BT Serial 2 Serial 1 PIC CL CD1283 Peripheral Parallel ESCC 85230 CIO Z8536 Serial 3 Serial 4 Parallel 16M 128M DIMM Memory Socket 16M 128M DIMM Memory Socket 16M 512M DIMM Memory Socket Processor 0 MPC603e 604e 64 ...

Page 26: ... Maps The following sections describe the memory maps for the MTX series Processor Memory Maps The Processor memory map is controlled by the Raven ASIC and the Falcon chipset The Raven ASIC and the Falcon chipset have flexible programming Map Decoder registers to customize the system to fit many different applications Default Processor Memory Map After a reset the Raven ASIC and the Falcon chipset...

Page 27: ...a recommended CHRP memory map from the point of view of the processor FEF9 0000 FEFE FFFF 384K Not mapped FEFF 0000 FEFF FFFF 64K Raven Registers FF00 0000 FFEF FFFF 15M Not mapped FFF0 0000 FFFF FFFF 1M ROM FLASH Bank A or Bank B 2 Table 1 3 CHRP Memory Map Example Processor Address Size Definition Notes Start End 0000 0000 top_dram dram_size System Memory onboard DRAM 1 2 4000 0000 FCFF FFFF 3G ...

Page 28: ...t this range after a reset if the rom_b_rv control bit is cleared If the rom_b_rv control bit is set then this address range maps to ROM FLASH Bank B 7 The only method to generate a PCI Interrupt Acknowledge cycle 8259 IACK is to perform a read access to the Raven s PIACK register at 0xFEFF0030 FE80 0000 FEF7 FFFF 7 5M Reserved FEF8 0000 FEF8 FFFF 64K Falcon Registers FEF9 0000 FEFE FFFF 384K Rese...

Page 29: ... Value FEFF 0040 MSADD0 4000 FCFF FEFF 0044 MSOFF0 MSATT0 0000 00C2 FEFF 0048 MSADD1 FD00 FDFF FEFF 004C MSOFF1 MSATT1 0300 00C2 FEFF 0050 MSADD2 0000 0000 FEFF 0054 MSOFF2 MSATT2 0000 0002 FEFF 0058 MSADD3 FE00 FE7F FEFF 005C MSOFF3 MSATT3 0200 00C0 Table 1 5 PREP Memory Map Example Processor Address Size Definition Notes Start End 0000 0000 top_dram dram_size System Memory onboard DRAM 1 8000 00...

Page 30: ...rform a read access to the Raven s PIACK register at 0xFEFF0030 The following table shows the programmed values for the associated Raven MPC registers for the processor PREP memory map FF00 0000 FF7F FFFF 4M ROM FLASH Bank A 1 3 FF80 0000 FF8F FFFF 1M ROM FLASH Bank B 1 3 FF90 0000 FFEF FFFF 6M Reserved FFF0 0000 FFFF FFFF 1M ROM FLASH Bank A or Bank B 4 Table 1 6 Raven MPC Register Values for PRE...

Page 31: ...CI memory map is controlled by the Raven ASIC The Raven ASIC has flexible programming Map Decoder registers to customize the system to fit many different applications Default PCI Memory Map After a reset the Raven ASIC turns all the PCI slave map decoders off Software must program the appropriate map decoders for a specific environment PCI CHRP Memory Map The following table shows a PCI memory map...

Page 32: ...PIC 1 FC04 0000 FCFF FFFF 16M 256K PCI Memory Space FD00 0000 FDFF FFFF 16M PCI Memory Space or System Memory Alias Space mapped to 00000000 to 00FFFFFF 1 FE00 0000 FFFF FFFF 32M Reserved Table 1 8 Raven PCI Register Values for CHRP Memory Map Configuration Address Offset Configuration Register Name Register Value Aliasing OFF Register Value Aliasing ON 14 RavenMPIC MBASE FC00 0000 FC00 0000 80 PS...

Page 33: ...9 PCI PREP Memory Map PCI Address Size Definition Notes Start End 0000 0000 00FF FFFF 16M PCI ISA Memory Space 0200 0000 7FFF FFFF 2G 16M PCI Memory Space 8000 0000 FBFF FFFF 2G 64M Onboard ECC DRAM 1 FC00 0000 FC03 FFFF 256K RavenMPIC 1 FC04 0000 FFFF FFFF 64M 256K PCI Memory Space Table 1 10 Raven PCI Register Values for PREP Memory Map Configuration Address Offset Configuration Register Name Re...

Page 34: ...ster PVR The following table shows the PVR values for the supported processors Processor PLL Configuration The processor internal clock frequency Core Frequency is multiple of the system bus frequency Each processor has four configuration pins PLL_CFG for hardware strapping of the processor core frequency Look Aside Cache The look aside external cache when present is implemented with the Glance de...

Page 35: ...red address range FFF00000 FFFFFFFF maps Bank A When rom_b_rv bit is set it maps to Bank B System Memory The system memory is ECC protected and is controlled by the Falcon chipset Up to two blocks of system memory are supported Each block of system memory can be up to 1GB in size The design supports DRAM speed as slow as 70ns Both fast page mode and hyper page EDO mode are supported The best memor...

Page 36: ...ical DIMM SPD Information Byte Value hex Entry Value Description 0 0hxx x Number of SPD bytes 1 0h08 256 Total bytes in SPD EEPROM 2 0h01 0h02 Fast Page EDO Memory type 3 oh0C 12 of row addresses 4 0h0B 11 of column addresses 5 0h01 1 of banks DIMM 6 0h40 0h48 x64 x72 Module data width 7 0h00 0 Module data width cont 8 0h01 LVTTL Module interface levels 9 0h3C 0h46 60ns 70ns RAS access time 10 0h0...

Page 37: ...not go to either Falcon in the pair however the access is terminated normally with TA Falcon Controlled System Registers The Falcon chipset latches the states of the DRAM data lines onto the PR_STAT1 and PR_STAT2 registers The MTX series uses these status registers to provide the system configuration information In addition the Falcon chipset performs the decode and control for an external registe...

Page 38: ...ld specifies the type of the overall system configuration so that the software may appropriately handle any software visible differences For the MTX series this field returns a value of FB SYSCLK System Clock Speed This field relays the system clock speed and the PCI clock speed information as follows SYSXC System External Cache Size This field reflects size of the look aside cache on the system b...

Page 39: ...pull ups are latched by the lower Falcon chip at a rising edge of the power up reset and stored in this Memory Configuration Register In the MTX SYSXC Value External Look aside Cache Size 0b0000 to 0b1011 Reserved 0b1100 1MB 0b1101 512KB 0b1110 256KB 0b1111 None P0 1STAT Value Processor 0 1 Present External In line Cache Size 0b0000 to 0b0011 Reserved Reserved 0b0100 YES 1MB 0b0101 YES 512KB 0b011...

Page 40: ...nk If the bank width is 64 bit and the device width is 16 bit then the FLASH bank consists of four FLASH devices FLSHP 0 2 Bank A Flash memory size This field is encoded as follows Register Memory Configuration Register FEF80404 Bit 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Field M_FREF M_SPD0 M_SPD1 R_A_TYP0 R_A_TYP1 R_A_TYP2 R_B_TYP0 R_B_TYP1...

Page 41: ...es this cache from responding to any bus cycles SXC_FLSH_ System External Cache Flush When this bit is pulsed true for at least 8 clock periods it causes the system external cache to write back dirty cache lines out to system memory and clears all the tag valid bits Flash Size FLSHP0_ FLSHP1_ FLSHP2_ 1MB 0 0 0 2MB 0 0 1 4MB 0 1 0 8MB 0 1 1 16MB 1 0 0 32MB 1 0 1 64MB 1 1 0 No Flash 1 1 1 Register S...

Page 42: ...ion still operates SXC_MI_ System External Cache Miss Inhibit When this bit is cleared it prevents line fills on cache misses Warning Software should never clear more than one of these bits at the same time If more than one is cleared at the same time the Glance pair behaves indeterminately Processor 0 External Cache Control Register P0XCCR The Processor 0 External Cache Control Register is access...

Page 43: ...e Control Register is accessed via the RD 32 39 data lines of the upper Falcon device This register is not implemented for systems without In line Cache This 8 bit register is defined as follows P1XC_CFG Processor 1External Cache Configuration Access Mode When this bit is set it maps the Processor 1 s external cache in Configuration Access Mode Refer to the IBM15 C700A SLC User s Manual for detail...

Page 44: ...th the LEND bit in the Raven for little endian mode P0 1_TBEN Processor 0 1 Time Base Enable When this bit is cleared the TBEN pin of Processor 0 1 will be driven low ISA Local Resource Bus W83C553 PIB Registers The PIB contains ISA Bridge I O registers for various functions These registers are accessible from the PCI bus Refer to the W83C553 Data Book for details Primary and Secondary EIDE Ports ...

Page 45: ... the MK48T59 559 are accomplished via three registers The NVRAM RTC Address Strobe 0 Register the NVRAM RTC Address Strobe 1 Register and the NVRAM RTC Data Port Register The NVRAM RTC Address Strobe 0 Register latches the lower 8 bits of the address and the NVRAM RTC Address Strobe 1 Register latches the upper 5 bits of the address Table 1 14 Strap Pins Configuration for the PC87308VUL Pins Reset...

Page 46: ...on and status information about the board These registers are listed in the following table The following sub sections describe these registers in detail CPU Configuration Register The CPU Configuration Register is an 8 bit register located at ISA I O address x0800 This register is defined for the MTX to provide compatibility with existing firmware and AIX revisions The Base Module Status Register...

Page 47: ...sent If set there is no on board sync serial support If cleared there is on board support for sync serial interface PCI1P_ PMC or 32 bit PCI Slot 1 Present If set there is no PMC PCI device installed in the PMC PCI Slot 1 If cleared the PMC PCI Slot 1 contains a PMC or a PCI device PCI2P_ PMC or 32 bit Slot 2Present If set there is no PMC PCI device installed in the PMC PCI Slot 2 If cleared the P...

Page 48: ... If cleared on board SCSI is supported Base Module Status Register BMSR The Base Module Status Register is an 8 bit read only register located at ISA I O address x0803 BASE_TYPEBase Module Type This eight bit field is used to provide the category of the base module and is defined as follows Extended Status Register The Extended Status Register is an 8 bit read only register located at ISA I O addr...

Page 49: ...ter located at ISA I O address x0950 If a one is written to this register the SCSI terminator is disabled If a zero is written to this register the terminator is enabled assuming the on board jumper described below is not installed This register is cleared by a hard reset terminators are enabled This register may be overriden by installation of an on board jumper at J36 The jumper disables the on ...

Page 50: ...he SCC User s Manual for programming information on the Z85230 ESCC device The Z8536 CIO is used to provide the modem control lines not provided by the Z85230 ESCC Refer to the Z8536 Data Sheet listed in Appendix A Related Documentation for programming information Z8536 Z85230 Registers Accesses to the Z8536 CIO and the Z85230 ESCC are accomplished via Port Control and Port Data Registers The PCLK...

Page 51: ...846 Z8536 CIO Port A s Data Register 0000 0847 Z8536 CIO Control Register 0000 084F Z85230 Z8536 Pseudo IACK Table 1 18 Z8536 CIO Port Pins Assignment Port Pin Signal Name Direction Descriptions PA0 TM3_ Input Port 3 Test Mode PA1 DSR3_ Input Port 3 Data Set Ready PA2 RI3_ Input Port 3 Ring Indicator PA3 LLB3_ Output Port 3 Local Loopback PA4 RLB3_ Output Port 3 Remote Loopback PA5 DTR3_ Output Po...

Page 52: ...nformation Refer to the PCF8584 data sheet for additional programming information The DIMM EEPROM addresses on the two wire serial bus are shown in Table 1 20 PB5 DTR4_ Output Port 4 Data Terminal Ready PB6 Reserved I O Reserved PB7 ABORT_ Input Status of ABORT signal PC0 Reserved I O Reserved PC1 Reserved I O Reserved PC2 Reserved I O Reserved PC3 Reserved I O Table 1 19 I2 C Controller Access Re...

Page 53: ...alid Table 1 20 Two Wire Serial I2 C Bus Addresses I2 C Bus Address Function 1010000 Bank A lower DIMM 1010001 Bank A upper DIMM 1010010 Bank B lower DIMM 1010011 Bank B upper DIMM Table 1 21 PIB DMA Channel Assignments PIB Priority PIB Label Controller DMA Assignment Highest Channel 0 DMA1 Serial Port 3 Receiver Z85230 Port A Rx Channel 1 Serial Port 3 Transmitter Z85230 Port A Tx Channel 2 Flopp...

Page 54: ... bus will be necessary in any PowerPC product This I O bus must be robust and efficient enough to handle the high bandwidth burst oriented traffic required for Ethernet SCSI graphics and VMEbus interfaces PCI is a high performance 32 bit or 64 bit burst mode synchronous bus capable of transfer rates of 132 MB sec in 32 bit mode or 264 MB sec in 64 bit mode using a 33 MHz clock Requirements The Rav...

Page 55: ...2 0 compliant 32 bit or 64 bit address data bus Support for accesses to all four PCI address spaces Single level write posting buffers for writes to the PPC bus Read ahead buffer for reads from the PPC bus Four independent software programmable slave map decoders Interrupt Controller MPIC compliant Support for 16 external interrupt sources and two processors Multiprocessor interrupt control allowi...

Page 56: ... Diagram Figure 2 1 Raven Block Diagram 1914 9610 Data Path B Mux FIFO Endian Mux FIFO Endian Data Path A PCI Regs MPIC PCI Dec Mux Reg Mux Reg PCI Slave PPC Slave Reg Reg PPC Dec PCIADIN PCI Master Mux PCI PPC Master PPC Arbiter PPC Regs Raven PCI Bus PPC Bus Mux PPC ...

Page 57: ...us addresses to which the Raven will respond the PPC Register File Decoder and four programmable decoders Table 2 1 shows a typical CHRP compliant memory map Another similar map is shown in Table 1 3 Table 2 1 CHRP Compliant Memory Map PPC Address Function 00000000 7FFFFFFF System Memory 2G 80000000 FCFFFFFF PCI Memory 2G 48M FD000000 FDFFFFFFF ISA Memory 16M FE000000 FE7FFFFF Discontiguous PCI IO...

Page 58: ...range of each map decoder and if the address falls within the specified range the access is passed on to PCI For each map there is an associated set of attributes These attributes are used to enable read accesses enable write accesses enable write posting and define the PCI transfer characteristics Each map decoder also includes a programmable 16 bit address offset The offset is added to the 16 mo...

Page 59: ...ill perform single beat transfers as required during all non cache aligned writes and some non cache aligned reads A 64 bit by 16 entry FIFO is used to hold data between the PCI slave and the PPC master to ensure that optimum data throughput is maintained While the PCI slave is filling the FIFO with one cache line worth of data the PPC master can be moving another cache line worth onto the PPC bus...

Page 60: ...n is enabled If the user wishes to perform very long burst transactions then the TDIS option should be disabled since the benefits of a long uninterrupted transaction far exceed the penalty of a few unused prefetch cycles The PPC master will never perform prefetch reads beyond the address range mapped within the PCI slave map decoders As an example assume Raven has been programmed to respond to PC...

Page 61: ...r When Bus Hog is not enabled the PPC master will structure its bus request actions around its desire to perform couplets This means the bus request will be deasserted between couplets Caution should be exercised when using this mode since the over generosity of bus ownership to the PPC master can be detrimental to the host CPU s performance The Bus Hog mode can be controlled by the BHOG bit withi...

Page 62: ... transfer is intended for PCI PCI bound transfers will be timed by the PCI master PCI Interface The Raven PCI Interface is designed to connect directly to a PCI Local Bus compliant I O bus The PCI interface may operate at any clock speed up to 33 MHz The PCLK input must be externally synchronized with the MCLK input and the frequency of the PCLK input must be exactly half the frequency of the MCLK...

Page 63: ...nds on the state of the EXT02 pin when the RST pin is released If EXT02 is sampled low the Raven will associate AD30 with IDSEL If EXT02 is sampled high the Raven will associate AD31 with IDSEL PCI Write Posting If write posting is enabled the Raven stores the target address attributes and up to 128 bytes of data from one PCI write transaction and immediately acknowledges the transaction on the PC...

Page 64: ...r burst transactions All single beat transactions will be subdivided into one or two 32 bit transfers depending on the alignment and size of the transaction The PCI master will attempt to transfer all burst transactions in 64 bit mode If at any time during the transaction the PCI target indicates it can not support 64 bit mode the PCI master will continue to transfer the remaining data in 32 bit m...

Page 65: ...addressing contiguous or spread address modes When the MEM bit is cleared the IOM bit is used to select between these two modes whenever a PCI I O cycle is to be performed When MEM is clear or IOM is clear the Raven will take the PPC address apply the offset specified in the MSOFFx register and map the result directly to PCI When MEM is clear and IOM is set the Raven will take the PPC address appl...

Page 66: ...r of 4 bytes starting at address 80000010 is considered a valid transfer An I O transfer of 4 bytes starting at address 80000011 is considered an invalid transfer since it crosses the natural word boundary at address 80000013 80000014 Generating PCI Configuration Cycles Mechanism one as just described above is utilized to generate configuration cycles Two 32 bit PCI I O ports at CF8 and CFC are us...

Page 67: ...er the CONFIG_ADDRESS register definition After the write to CF8 has been accomplished the next write to the CONFIG_DATA register causes the Raven to generate a special cycle on the PCI bus The write data is driven onto AD 31 0 during the special cycle s data phase Generating PCI Interrupt Acknowledge Cycles Performing a read from the PIACK register will initiate a single PCI Interrupt Acknowledge...

Page 68: ...ctive This is shown in the following figure Figure 2 3 Big to Little Endian Data Swap 1916 9610 DH07 00 DH15 08 DH23 16 DH31 24 DL07 00 DL15 08 DL23 16 DL31 24 D0 D1 D2 D3 D4 D5 D6 D7 D7 D6 D5 D4 D3 D2 D1 D0 D0 D1 D2 D3 D4 D5 D6 D7 AD63 56 AD55 48 AD47 40 AD39 32 AD31 24 AD23 16 AD15 08 AD07 00 DH07 00 DH15 08 DH23 16 DH31 24 DL07 00 DL15 08 DL23 16 DL31 24 D7 D6 D5 D4 D3 D2 D1 D0 AD31 24 AD23 16 ...

Page 69: ...fers Cycles Originating From PCI For bus cycles initiated by PCI masters the PCI address will be modified the same way the MCP60x processor does in little endian mode The modification will be the same as that described in the section above Since this method has some difficulties dealing with unaligned transfers the Raven will break up all unaligned PCI transfers into multiple aligned transfers on ...

Page 70: ...as follows Each MERST error bit may be programmed to generate a machine check and or a standard interrupt The error response is programmed through the PPC Error Enable Register on a source by source basis When a machine check is enabled either the MID field in the PPC Error Attribute Register or the DFLT bit in the MEREN Register determine the master to which the machine check is directed For erro...

Page 71: ...ction determines its future actions based on the stall signal and the current PPC bus activity If the PPC Slave function determines there will be contention between a cycle completing on the PPC bus and an incoming PCI cycle the PPC Slave will issue a retry for the current PPC transaction This retry will free up the PPC bus and allow the PCI initiated transaction to complete An idle PPC bus obviou...

Page 72: ...ed write buffers in both directions must be flushed before completing a read in either direction Raven supports this by providing two optional FIFO flushing options The PPCFBR PPC Flush Before Read bit within the GCSR register controls the flushing of PCI write posted data when performing PPC originated read transactions The PCIFBR bit within the GCSR register controls the flushing of PPC write po...

Page 73: ...m the PPC bus are flushed in the following manner The PPC slave will set a signal called ppcs_fbrabt anytime it has committed to performing a posted write transaction This signal will remain asserted until the PCI bound FIFO count has reached zero The PCI slave decode logic settles out several clocks after the assertion of FRAME at which time the PCI slave can determine the transaction type If it ...

Page 74: ...Table 2 5 Raven PPC Register Map Bit 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 FEFF0000 VENID DEVID FEFF0004 REVID FEFF0008 GCSR FEAT FEFF000C FEFF0010 PADJ FEFF0014 FEFF0018 FEFF001C FEFF0020 ERRTST ERREN FEFF0024 ERRST FEFF0028 ERRAD FEFF002C ERRAT FEFF0030 PIACK FEFF0034 FEFF0038 FEFF003C FEFF0040 PPCSADD0 FEFF0044 PPCSOFF0 PPCSA...

Page 75: ...ys return 4801 This register is duplicated in the PCI Configuration Registers FEFF0050 PPCSADD2 FEFF0054 PPCSOFF2 PPCSATT2 FEFF0058 PPCSADD3 FEFF005C PPCSOFF3 PPCSATT3 FEFF0060 WDT1CNTL FEFF0064 WDT1STAT FFEF0068 WDT2CNTL FEFF006C WDT2STAT FEFF0070 GPREG0 Upper FEFF0074 GPREG0 Lower FEFF0078 GPREG1 Upper FEFF007C GPREG1 Lower Address FEFF0000 Bit 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7...

Page 76: ...as described in the section When PPC Devices are Big Endian on page 2 15 Address FEFF0004 Bit 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 Name REVID Operation R R R R Reset 00 03 00 00 Address FEFF0008 Bit 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 Name GCSR FEAT Operati...

Page 77: ...l request the bus in a normal manner Please refer to the section on PPC Master for more information PPCFBR PPC Flush Before Read If set the Raven will guarantee that all PCI initiated posted write transactions will be completed before any PPC initiated read transactions will be allowed to complete When PPCFBR is clear there will be no correlation between these transaction types and their order of ...

Page 78: ...RESET This register may be used to report hardware configuration parameters to system software Prescaler Adjust Register PADJ Prescaler Adjust This register is used to specify a scale factor for the prescaler to ensure that the time base for the bus timer is 1 MHz The scale factor is calculated as follows PADJ 256 Clk where Clk is the frequency of the CLK input in MHz The following table shows the...

Page 79: ...hich MCHK pin will be asserted for error conditions in which the PPC master ID cannot be determined or the Raven was the PPC master For example in event of a PCI parity error for a transaction in which the Raven s PCI master was not involved the PPC master ID cannot be determined When DFLT is set MCHK1 is used When DFLT is clear MCHK0 will be used Frequency PADJ 66 BE 50 CE 40 D8 33 DF 25 E7 Addre...

Page 80: ...the MCHK output to bus master 0 When this bit is clear MCHK will not be asserted SMAM PCI Signalled Master Abort Machine Check Enable When this bit is set the SMA bit in the ERRST register will be used to assert the MCHK output to the bus master which initiated the transaction When this bit is clear MCHK will not be asserted RTAM PCI Master Received Target Abort Machine Check Enable When this bit ...

Page 81: ... the ERRST register will be used to assert an interrupt through the OpenPIC interrupt controller When this bit is clear no interrupt will be asserted RTAI PCI Master Received Target Abort Interrupt Enable When this bit is set the RTA bit in the ERRST register will be used to assert an interrupt through the OpenPIC interrupt controller When this bit is clear no interrupt will be asserted PPC Error ...

Page 82: ...ed It may be cleared by writing it to a 1 writing it to a 0 has no effect When the PERRM bit in the ERREN register is set the assertion of this bit will assert MCHK to the master designated by the DFLT bit in the ERRAT register When the PERRI bit in the ERREN register is set the assertion of this bit will assert an interrupt through the OpenPIC interrupt controller SERR PCI System Error This bit i...

Page 83: ...t an interrupt through the OpenPIC interrupt controller PPC Error Address Register EERAD PPC Error Address This register captures the PPC address when the PATO bit is set in the EERST register It captures the PCI address when the SMA or RTA bits are set in the EERST register Its contents are not defined when the PDPE PERR or SERR bits are set in the EERST register PPC Error Attribute Register MERA...

Page 84: ...error occurred Refer to PowerPC documents listed in Table A 2 on page A 2 If the SMA or RTA bit are set the register is defined by the following table Address FEFF002C Bit 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 Name MERAT MID1 MID0 TBST TSIZ0 TSIZ1 TSIZ2 TT0 TT1 TT2 TT3 TT4 Operation R R R R R R R R R R R R R R R R R R Reset 00 0...

Page 85: ... field contains the PCI byte enables of the PCI transfer in which the error occurred A set bit designates a selected byte PCI Interrupt Acknowledge Register PIACK PCI Interrupt Acknowledge Performing a read from this register will initiate a single PCI Interrupt Acknowledge cycle Any single byte or combination of bytes may be read from and the actual byte enable pattern used during the read will b...

Page 86: ...ss END End Address This field determines the end address of a particular memory area on the PPC bus which will be used to access PCI bus resources The value of this field will be compared with the upper 16 bits of the incoming PPC address PPC Slave Address 3 Register Address MSADD0 FEFF0040 MSADD1 FEFF0048 MSADD2 FEFF0050 Bit 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 ...

Page 87: ...l to the START field and less than or equal to the END field START Start Address This field determines the start address of a particular memory area on the PPC bus which will be used to access PCI bus resources The value of this field will be compared with the upper 16 bits of the incoming PPC address END End Address This field determines the end address of a particular memory area on the PPC bus ...

Page 88: ... If set the corresponding PPC slave will generate transfers to or from PCI memory space When clear the corresponding PPC slave will generate transfers to or from PCI I O space using the addressing mode defined by the IOM field IOM PCI I O Mode If set the corresponding PPC slave will generate PCI I O cycles using spread addressing as defined in the section on Generating PCI Memory and I O Cycles Wh...

Page 89: ... is enabled for write transactions WPEN Write Post Enable If set write posting is enabled for the corresponding PPC slave IOM PCI I O Mode If set the corresponding PPC slave will generate PCI I O cycles using spread addressing as defined in the section on Generating PCI Memory and I O Cycles When clear the corresponding PPC slave will generate PCI I O cycles using contiguous addressing General Pur...

Page 90: ...l be completed normally on the bus and the data will be discarded Read accesses to reserved or unimplemented registers will be completed normally and a data value of 0 returned The Raven PCI Configuration Register map is shown in Table 2 6 The Raven PCI I O Register map is shown in Table 2 7 Table 2 6 Raven PCI Configuration Register Map 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 ...

Page 91: ...uplicated in the PPC Registers DEVID Device ID This register identifies the particular device The Raven will always return 4801 This register is duplicated in the PPC Registers Table 2 7 Raven PCI I O Register Map 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 Bit CONFIG_ADDRESS CF8 CONFIG_DATA CFC Offset 00 Bit 3 1 3 0 2 9 2 8 2 7 2 6 2...

Page 92: ...ers If cleared the Raven will ignore any parity errors that it detects and continue normal operation SERR System Error Enable This bit enables the SERR output pin If clear the Raven will never drive SERR If set the Raven will drive SERR active when a system error is detected FAST Fast Back to Back Capable This bit indicates that the Raven is capable of accepting fast back to back transactions with...

Page 93: ... transaction is terminated by a target abort It is cleared by writing it to 1 writing a 0 has no effect RCVMA Received Master Abort This bit is set by the PCI master whenever its transaction except for Special Cycles is terminated by a master abort It is cleared by writing it to 1 writing a 0 has no effect SIGSE Signaled System Error This bit is set whenever the Raven asserts SERR It is cleared by...

Page 94: ... Base Class Code 06 PCI Bridge Device Subclass Code 00 PCI Host Bridge Program Class Code 00 Not Used Offset 0C Bit 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 Name HEADER Operation R R R R Reset 00 00 00 00 Header Type 00 Single Function Configuration Header Offset 10 Bit 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 ...

Page 95: ...IO MEMIO Space Indicator This bit is hard wired to a logic zero to indicate PCI memory space MTYPx Memory Type These bits are hard wired to zero to indicate that the MPIC registers can be located anywhere in the 32 bit address space PRE Prefetch This bit is hard wired to zero to indicate that the MPIC registers are not prefetchable MEMBA Memory Base Address These bits define the memory space base ...

Page 96: ...to access PPC bus resources The value of this field will be compared with the upper 16 bits of the incoming PCI address END End Address This field determines the end address of a particular memory area on the PCI bus which will be used to access PPC bus resources The value of this field will be compared with the upper 16 bits of the incoming PCI address Offset PSADD0 80 PSADD1 88 PSADD2 90 PSADD3 ...

Page 97: ...r FIFO threshold mechanism is disabled See the section titled PPC Master for more information on the relationship between TDIS and RAEN RAEN Read Ahead Enable If set read ahead is enabled for the corresponding PCI slave WPEN Write Post Enable If set write posting is enabled for the corresponding PCI slave WEN Write Enable If set the corresponding PCI slave is enabled for write transactions REN Rea...

Page 98: ...rows indicate the source bit positions on the PPC data bus when data is written to this register A read from the CONFIG_ADDRESS register will return contents to these locations One row defines the source for big endian operation and the second is for little endian operation LEND is the little endian control bit in the GCSR The MSADD3 MSOFF3 and MSATT3 are initialized at reset so software can acces...

Page 99: ...tries for the device number The Raven will drive all 0 s in bit position AD11 through AD31 if a illegal device id is initialized into the configuration address register A value of 0B sets PCI AD bit 11 IDSEL 11 during the address phase of a Configuration cycle A value of 0C sets AD bit 12 As the device number increments the AD bit increments until a the value of 1E sets AD bit 30 A value of 00 in ...

Page 100: ... PCI bus Raven Interrupt Controller Implementation Introduction The Raven Interrupt Controller Raven MPIC Features MPIC programming model Support for two processors Support for 16 external interrupts Support for 15 programmable Interrupt Processor Task priority levels Support for the connection of an external 8259 for ISA AT compatibility Distributed interrupt delivery for external I O interrupts ...

Page 101: ...ther level or edge activated with either polarity The Interprocessor and timers interrupts are event activated CSR s Readability Unless explicitly specified all registers are readable and return the last value written The exceptions are the IPI dispatch registers and the EOI registers which return zeros on reads the interrupt source ACT bit which returns current interrupt source status the interru...

Page 102: ...or that interrupt The EOI cycle indicates the end of processing for the highest priority in service interrupt Spurious Vector Generation Under certain circumstances the Raven MPIC will not have a valid vector to return to the processor during an interrupt acknowledge cycle In these cases the spurious vector from the spurious vector register will be returned The following cases would cause a spurio...

Page 103: ...ot interact with the vector fetch from the 8259 interrupt controller Raven Detected Errors Raven detected errors are grouped together and sent to the interrupt logic as a singular interrupt source The interrupt delivery mode for this interrupt is distributed For system implementations where the Raven MPIC controller is not used the Raven Detected Error condition will be made available by a signal ...

Page 104: ...pt which is in service for that processor An interrupt is considered to be in service from the time its vector is returned during an interrupt acknowledge cycle until an EOI is received for that interrupt The EOI cycle indicates the end of processing for the highest priority in service interrupt In the distributed delivery mode the interrupt is pointed to one or more processors but it will be deli...

Page 105: ...ors are targeted for interrupt delivery the interrupt will be delivered to processor 0 or processor 1 as determined by the TIE mode Block Diagram Description The description of the block diagram focuses on the theory of operation for the interrupt delivery logic If the preceding section is a satisfactory description of the interrupt delivery modes and the reader is not interested the logic impleme...

Page 106: ...ion http www motorola com computer literature 2 53 2 Figure 2 4 Raven MPIC Block Diagram 1917 9610 IPR Interrupt Selector_1 IRR_1 Interrupt Router ISR_1 interrupt signals Program Visible Registers Interrupt Selector_0 IRR_0 ISR_0 INT1 INT 0 ...

Page 107: ...ince the internally generated interrupts use direct delivery mode with multicast capability there are two bits in the IPR one for each processor associated with each IPI and Timer interrupt source The MASK bits from the Vector Priority registers are used to qualify the output of the IPR Therefore if an interrupt condition is detected when the MASK bit is set that interrupt will be requested when t...

Page 108: ...ed to store the source identification of each interrupt which is in service Therefore there is one bit for each possible interrupt priority and one bit for each possible interrupt source Interrupt Router The Interrupt Router monitors the outputs from the ISRs Current Task Priority Registers Destination Registers and the IRRs to determine when to assert a processor s INT pin When considering the fo...

Page 109: ...a 0 for this interrupt The priority from IRR_0 is greater than the highest priority in ISR_0 The priority from IRR_0 is greater than the contents of task register_0 Set2 The source ID in IRR_0 is from an external source The destination bit for processor 1 is a 1 for this interrupt The source ID in IRR_0 is not present is ISR_1 The priority from IRR_0 is greater than the highest priority in ISR_0 T...

Page 110: ...ing a ONE to this field sets this field C Writing a ONE to this field clears this field Raven MPIC Registers The Raven MPIC register map is shown in the following table The Off field is the address offset from the base address of the Raven MPIC registers in the MPC IO or MPC MEMORY space Note This map does not depict linear addressing The Raven PCI SLAVE has two decoders for generating the Raven M...

Page 111: ...IPI2 VECTOR PRIORITY REGISTER 010c0 IPI3 VECTOR PRIORITY REGISTER 010d0 SP REGISTER 010e0 TIMER FREQUENCY REPORTING REGISTER 010f0 TIMER 0 CURRENT COUNT REGISTER 01100 TIMER 0 BASE COUNT REGISTER 01110 TIMER 0 VECTOR PRIORITY REGISTER 01120 TIMER 0 DESTINATION REGISTER 01130 TIMER 1 CURRENT COUNT REGISTER 01140 TIMER 1 BASE COUNT REGISTER 01150 TIMER 1VECTOR PRIORITY REGISTER 01160 TIMER 1DESTINAT...

Page 112: ...INATION REGISTER 100b0 INT SRC 6 VECTOR PRIORITY REGISTER 100c0 INT SRC 6 DESTINATION REGISTER 100d0 INT SRC 7 VECTOR PRIORITY REGISTER 100e0 INT SRC 7 DESTINATION REGISTER 100f0 INT SRC 8 VECTOR PRIORITY REGISTER 10100 INT SRC 8 DESTINATION REGISTER 10110 INT SRC 9 VECTOR PRIORITY REGISTER 10120 INT SRC 9 DESTINATION REGISTER 10130 INT SRC 10 VECTOR PRIORITY REGISTER 10140 INT SRC 10 DESTINATION ...

Page 113: ...ATCH REGISTER PROC 0 20040 IPI 1 DISPATCH REGISTER PROC 0 20050 IPI 2 DISPATCH REGISTER PROC 0 20060 IPI 3 DISPATCH REGISTER PROC 0 20070 CURRENT TASK PRIORITY REGISTER PROC 0 20080 IACK REGISTER P0 200a0 EOI REGISTER P0 200b0 IPI 0 DISPATCH REGISTER PROC 1 21040 IPI 1 DISPATCH REGISTER PROC 1 21050 IPI 2 DISPATCH REGISTER PROC 1 21060 IPI 3 DISPATCH REGISTER PROC 1 21070 CURRENT TASK PRIORITY REG...

Page 114: ...this interrupt controller This value reports what level of the specification is supported by this implementation Version level of 03 is used for this release of the MPIC specification Global Configuration Register Offset 01000 Bit 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 Name FEATURE REPORTING NIRQ NCPU VID Operatio n R R R R R Res...

Page 115: ...MPIC is essentially disabled In the mixed mode 8259 interrupts are delivered using the priority and distribution mechanism of Raven MPIC The Vector Priority and Destination registers for interrupt source 0 are used to control the delivery mode for all 8259 generated interrupt sources T Tie Mode Writing a one to this register bit will cause a tie in external interrupt processing to swap back and fo...

Page 116: ...ssert the Soft Reset input of processor 1 Writing a 0 to it will negate the SRESET signal P0 PROCESSOR 0 Writing a 1 to P0 will assert the Soft Reset input of processor 0 Writing a 0 to it will negate the SRESET signal The Soft Reset input to the 604 is negative edge sensitive Offset 01080 Bit 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1...

Page 117: ...The ACT bit is set to a one when its associated bit in the Interrupt Pending Register or In Service Register is set PRIOR Interrupt priority 0 is the lowest and 15 is the highest Note that a priority level of 0 will not enable interrupts VECTOR This vector is returned when the Interrupt Acknowledge register is examined during a request for the interrupt associated with this vector Offset IPI 0 010...

Page 118: ...register contains zero system initialization code must initialize this register to one eighth the MPIC clock frequency For the Raven implementation of MPIC a typical value would be 7de290 which is 66 8 MHz or 8 25 MHz Offset 010E0 Bit 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 Name VECTOR Operation R R R R W Reset 00 00 00 FF Offset ...

Page 119: ...aded from the Base Count register and the timer s interrupt becomes pending in the MPIC processing Timer Basecount Registers Offset Timer 0 01100 Timer 1 01140 Timer 2 01180 Timer 3 011C0 Bit 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 Name TIMER CURRENT COUNT T CC Operation R R Reset 0 00000000 Offset Timer 0 01110 Timer 1 01150 Time...

Page 120: ...er Vector Priority Registers MASK MASK Setting this bit disables any further interrupts from this source If the mask bit is cleared while the bit associated with this interrupt is set in the IPR the interrupt request will be generated ACT ACTIVITY The activity bit indicates that an interrupt has been requested or that it is in service The ACT bit is set to a one when its associated bit in the Inte...

Page 121: ...s for this timer s interrupts Timer interrupts operate in the Directed delivery interrupt mode This register may specify multiple destinations multicast delivery P1 PROCESSOR 1 The interrupt is directed to processor 1 P0 PROCESSOR 0 The interrupt is directed to processor 0 Offset Timer 0 01130 Timer 1 01170 Timer 2 011B0 Timer 3 011F0 Bit 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7...

Page 122: ...o a one enables active high or positive edge Only External Interrupt Source 0 uses this bit in this register SENSE SENSE This bit sets the sense for external interrupts Setting this bit to a zero enables edge sensitive interrupts Setting this bit to a one enables level sensitive interrupts For external interrupt sources 1 through 15 setting this bit to a zero enables positive edge triggered interr...

Page 123: ...ter indicates the possible destinations for the external interrupt sources These interrupts operate in the Distributed interrupt delivery mode P1 PROCESSOR 1 The interrupt is pointed to processor 1 P0 PROCESSOR 0 The interrupt is pointed to processor 0 Offset Int Src 0 10010 Int Src 2 Int Src 15 10030 101F0 Bit 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0...

Page 124: ...ster or In Service Register is set SENSE SENSE This bit sets the sense for the internal Raven Detected Errors interrupt This bit is hardwired to 1 to enable active low level sensitive interrupts PRIOR Interrupt priority 0 is the lowest and 15 is the highest Note that a priority level of 0 will not enable interrupts VECTOR This vector is returned when the Interrupt Acknowledge register is examined ...

Page 125: ...re four Interprocessor Interrupt Dispatch Registers Writing to an IPI Dispatch Register with the P0 and or P1 bit set causes an interprocessor interrupt request to be sent to one or more processors Offset 10210 Bit 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 Name RAVEN DETECTED ERROR DESTINATION P1 P0 Operation R R R R R W R W Reset 0...

Page 126: ...st to 15 highest are supported Setting the Task Priority Register to 15 masks all interrupts to this processor Hardware will set the task register to F when it is reset or when the Init bit associated with this processor is written to a one Interrupt Acknowledge Registers Offset Processor 0 20080 Processor 1 21080 Bit 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 ...

Page 127: ...ex End of Interrupt Registers EOI END OF INTERRUPT There is one EOI register per processor EOI Code values other than 0 are currently undefined Data values written to this register are ignored zero is assumed Writing to this register signals the end of processing for the highest priority interrupt currently in service by the associated processor The write operation will update the In Service regis...

Page 128: ...nd re enables for external interrupts the MSRee bit is set to 1 Raven MPIC blocks interrupts from sources with equal or lower priority until an End of Interrupt is received for that interrupt source Interrupts from higher priority interrupt sources continue to be enabled If the interrupt source was the 8259 the interrupt handler issues an EOI request to the MPIC This resets the In Service bit for ...

Page 129: ...rs stopped and interrupts disabled Controller mode set to 8259 pass through Operation Interprocessor Interrupts Four interprocessor interrupt IPI channels are provided for use by all processors During system initialization the IPI vector priority registers for each channel should be programmed to set the priority and vector returned for each IPI event During system operation a processor may genera...

Page 130: ...il all processing of pending interrupts is complete EOI Register Each processor has a private EOI register which is used to signal the end of processing for a particular interrupt event If multiple nested interrupts are in service the EOI command terminates the interrupt service of the highest priority source Once an interrupt is acknowledged only sources of higher priority will be allowed to inte...

Page 131: ...e Architectural Notes The hardware and software overhead required to update the task priority register synchronously with instruction execution may far outweigh the anticipated benefits of the task priority register To minimize this overhead the interrupt controller architecture should allow the task priority register to be updated asynchronously with respect to instruction execution Lower priorit...

Page 132: ...model for the Falcon Most of the information for using the device in a system programming it in a system and testing it is contained here Bit Ordering Convention All Falcon bused signals are named using big endian bit ordering bit 0 is the most significant bit Features DRAM Interface Double bit error detect Single bit error correct on 72 bit basis Up to four blocks Programmable base address for ea...

Page 133: ... ROM Flash Interface Two blocks with each block being 16 bits wide 8 bits per Falcon or 64 bits wide 32 bits per Falcon Software programmable access time for each block Block Diagrams Figure 3 1 depicts a Falcon pair as it would be connected in a system Figure 3 2 shows the Falcon s internal data paths Figure 3 3 shows the overall DRAM connections ...

Page 134: ... Lower DRAM ARRAYS Check Data Upper DRAM ARRAYS Data 32Bits Lower DRAM Data 64 Bits Lower DRAM Address Control Lower DRAM Check bits 8 Bits Upper DRAM Data 64 Bits Upper DRAM Address Control Upper DRAM Check bits 8 Bits Upper PowerPC Data 32 Bits PowerPC Address Control Serial Bus PowerPC 60x Bus Lower PowerPC Data Parity 4 Bits Upper PowerPC Data Parity 4 Bits ...

Page 135: ... Set 3 Figure 3 2 Falcon Internal Data Paths Simplified CKD 0 7 RD 0 63 D 0 31 LATCHES HAMGEN SYNDEC MUX HAMGEN Corrected Data Uncorrected Data 64 Bits DRAM PowerPC Side Side DFF s Latched D 64 Bits 64 Bits 8 Bits 8 Bits 8 Bits 64 Bits 64 Bits 64 Bits LATCHES DP 0 3 PARCHK PARGEN ...

Page 136: ...onnections DRAM Block A DRAM Block B DRAM Block C DRAM Block D RD0 63 CKD0 7 LOWER FALCON Lower Lower Lower Lower DRAM Block A DRAM Block B DRAM Block C DRAM Block D RD0 63 CKD0 7 UPPER FALCON Upper Upper Upper Upper BD_RAS_ CAS_ AC_RAS_ CAS_ RA OE_ WE_ BD_RAS_ CAS_ AC_RAS_ CAS_ RA OE_ WE_ ...

Page 137: ...the Falcon pair accesses the full 144 bit width of DRAM at once so that when the DRAM access time is reached not only is the first 64 bit double word of data ready to be transferred to the PowerPC 60x bus master but so is the next While the Falcon pair is presenting the first two double words to the PowerPC 60x bus it cycles CAS without cycling RAS to obtain the next two double words The Falcon pa...

Page 138: ...peeds of DRAM 50ns 60ns and 70ns When the Falcon pair is configured for 50ns DRAMs it assumes that the devices are Extended Data Out EDO parts When the Falcon pair is configured for 70ns DRAMs it assumes that the devices are fast page mode parts When the pair is configured for 60ns DRAMs it allows the devices to be either fast page or EDO parts Performance summaries using the different devices are...

Page 139: ...Beat Read after 1 Beat Read 11 7 1 11 7 1 Beat Write after Idle 4 4 1 Beat Write after 1 Beat Write 15 11 1 15 11 Table 3 2 PowerPC 60x Bus to DRAM Access Timing when Configured for 60ns Fast Page Devices ACCESS TYPE CLOCK PERIODS REQUIRED FOR Total Clocks 1st Beat 2nd Beat 3rd Beat 4th Beat 4 Beat Read after Idle Quad word aligned 9 1 2 1 13 4 Beat Read after Idle Quad word misaligned 9 3 1 1 14 ...

Page 140: ...t column are for page miss page hit 4 Beat Write after Idle 4 1 1 1 7 4 Beat Write after 4 Beat Write Quad word aligned 7 3 1 1 1 1 10 6 1 Beat Read after Idle 9 9 1 Beat Read after 1 Beat Read 9 6 1 9 6 1 Beat Write after Idle 4 4 1 Beat Write after 1 Beat Write 13 10 1 13 10 Table 3 2 PowerPC 60x Bus to DRAM Access Timing when Configured for 60ns Fast Page Devices Continued ACCESS TYPE CLOCK PER...

Page 141: ...stances may be longer or shorter Table 3 3 PowerPC 60x Bus to DRAM Access Timing when Configured for 50ns EDO Devices ACCESS TYPE CLOCK PERIODS REQUIRED FOR Total Clocks 1st Beat 2nd Beat 3rd Beat 4th Beat 4 Beat Read after Idle Quad word aligned 8 1 1 1 11 4 Beat Read after Idle Quad word misaligned 8 2 1 1 12 4 Beat Read after 4 Beat Read Quad word aligned 5 2 1 1 1 1 8 5 4 Beat Read after 4 Bea...

Page 142: ...s 1st Beat 2nd Beat 3rd Beat 4th Beat 16 Bits 64 Bits 16 Bits 64 Bits 16 Bits 64 Bits 16 Bits 64 Bits 16 Bits 64 Bits 4 Beat Read 68 20 64 16 64 16 64 16 260 68 4 Beat Write N A N A 1 Beat Read 1 byte 20 20 20 20 1 Beat Read 2 to 8 bytes 68 20 68 20 1 Beat Write 19 19 19 19 Table 3 5 PowerPC 60x Bus to ROM Flash Access Timing when configured for 120ns Devices ACCESS TYPE CLOCK PERIODS REQUIRED FOR...

Page 143: ...Beat 3rd Beat 4th Beat 16 Bits 64 Bits 16 Bits 64 Bits 16 Bits 64 Bits 16 Bits 64 Bits 16 Bits 64 Bits 4 Beat Read 40 13 36 9 36 9 36 9 148 40 4 Beat Write N A N A 1 Beat Read 1 byte 13 13 13 13 1 Beat Read 2 to 8 bytes 40 13 40 13 1 Beat Write 19 19 19 19 Table 3 7 PowerPC 60x Bus to ROM Flash Access Timing when configured for 45ns Devices ACCESS TYPE CLOCK PERIODS REQUIRED FOR Total Clocks 1st B...

Page 144: ...0x bus as soon as the entity has data ready and the PowerPC 60x data bus is granted If the data transfer will be a write the Falcon pair begins latching data from the PowerPC data bus as soon as any previously latched data is no longer needed and the PowerPC 60x data bus is available Data Parity The Falcon pair has 8 DP pins 4 per Falcon for generating and checking 60x data bus parity In addition ...

Page 145: ...or that access If the access is a DRAM write the Falcon does not write the data for that access Depending upon when the retry occurs the Falcon may cycle the DRAM even though the data transfer does not happen Cache Coherency Restrictions The PowerPC 60x GBL_ signal must not be asserted in the CSR areas L2 Cache Support The Falcon pair provides support for a look aside L2 cache by implementing a ho...

Page 146: ... DRAM the Falcon pair reads 144 bits at least once When the PowerPC 60x bus master requests a four beat write to DRAM the Falcon pair writes all 144 bits twice When the PowerPC 60x bus master requests a single beat write to DRAM the Falcon pair performs a 144 bit wide read cycle to DRAM merges in the appropriate PowerPC 60x bus write data and writes 144 bits back to DRAM Error Reporting The Falcon...

Page 147: ...er Web Site Falcon ECC Memory Controller Chip Set 3 Note The Falcon pair does not assert TEA_ on double bit errors In fact the Falcon pair does not have a TEA_ signal pin and it assumes that the system does not implement TEA_ The Falcon ...

Page 148: ...bus Write corrected data back to DRAM if so enabled Assert INT_ if so enabled Double Bit Error Terminate the PowerPC 60x bus cycle normally Provide miss corrected raw DRAM data to the PowerPC 60x bus master Assert INT_ if so enabled Assert MCP_ if so enabled Terminate the PowerPC 60x bus cycle normally May or may not perform the write portion of the read modify write cycle to DRAM 2 Assert INT_ if...

Page 149: ...nnected it records the address and syndrome bits associated with the data in error Each Falcon performs this logging function independently of the other Once a Falcon has logged an error it does not log any more until the elog control status bit has been cleared by software unless the currently logged error is single bit and a new double bit error is encountered The logging of errors that occur du...

Page 150: ...pears at FFF00000 FFFFFFFF if the reset vector enable bit is set 3 The assumed size for each block is software programmable It is initialized to its smallest setting at reset 4 The access time for each block is software programmable 5 The assumed width for Block A B is determined by an external jumper at reset time It also is available as a status bit and cannot be changed by software When the wid...

Page 151: ... 8 bits per Falcon Table 3 10 shows how they map when Flash is 64 bits wide 32 bits per Falcon Table 3 9 PowerPC 60x to ROM Flash Address Mapping when ROM Flash is 16 Bits Wide 8 Bits per Falcon PowerPC 60x A0 A31 ROM Flash A22 A0 ROM Flash Selected XX000000 000000 Upper XX000001 000001 Upper XX000002 000002 Upper XX000003 000003 Upper XX000004 000000 Lower XX000005 000001 Lower XX000006 000002 Lo...

Page 152: ...00000 Upper X0000001 000000 Upper X0000002 000000 Upper X0000003 000000 Upper X0000004 000000 Lower X0000005 000000 Lower X0000006 000000 Lower X0000007 000000 Lower X0000008 000001 Upper X0000009 000001 Upper X000000A 000001 Upper X000000B 000001 Upper X000000C 000001 Lower X000000D 000001 Lower X000000E 000001 Lower X000000F 000001 Lower X3FFFFF0 7FFFFE Upper X3FFFFF1 7FFFFE Upper Table 3 9 Powe...

Page 153: ...rted to both of Blocks A and B during each of the 4 cycles Along with RAS_ the Falcon pair also asserts CAS_ with OE_ then WE_ to one of the blocks during one of the four cycles This forms a read modify write which is a scrub cycle to that location X3FFFFF2 7FFFFE Upper X3FFFFF3 7FFFFE Upper X3FFFFF4 7FFFFE Lower X3FFFFF5 7FFFFE Lower X3FFFFF6 7FFFFE Lower X3FFFFF7 7FFFFE Lower X3FFFFF8 7FFFFF Upp...

Page 154: ...B during the third cycle and to blocks C and D during the fourth cycle Along with RAS the Falcon pair also asserts CAS_ with OE_ then WE_ to one of the blocks during one of the four cycles This forms a read modify write which is a scrub cycle to that location After the second and fourth cycles the DRAM row address increments by one When it reaches all 1 s it rolls over and starts over at 0 Each ti...

Page 155: ...al Register Set Each chip in the Falcon pair has an external register chip select pin which enables it to talk to an external set of registers This interface is like the ROM Flash interface but with less flexibility It is intended for the system designer to be able to implement general purpose status control signals with this external set Refer to the Programming Model for a description of this re...

Page 156: ...t and its external register set The base address of the CSR is hard coded to the address FEF80000 or FEF90000 if the SIO pin is low at reset Accesses to the CSR are mapped differently depending on whether they are reads or writes For reads CSR data read on the upper half of the data bus comes from the upper Falcon while CSR data read on the lower half of the data bus comes from the lower Falcon Se...

Page 157: ... Falcon Internal CSRs External register data that is written on the upper data bus goes through the upper Falcon while data that is written on the lower data bus goes through the lower Falcon Unlike the internal register set there is no automatic copying of upper data to lower data for the external register set CSR read accesses can have a size of 1 2 4 or 8 bytes with any alignment CSR write acce...

Page 158: ...ry Map for Byte Reads to the CSR 1905 9609 Upper Falcon Upper Falcon Upper Falcon Upper Falcon Lower Falcon Lower Falcon Lower Falcon Lower Falcon Upper Falcon Upper Falcon FEF80000 Lower Falcon FEF80001 FEF80002 FEF80003 FEF80004 FEF80005 FEF80006 FEF80007 FEF80008 FEF80009 FEF807FF ...

Page 159: ...Set 3 Figure 3 7 Memory Map for Byte Writes to the Internal Register Set 1906 9609 Both Falcons Both Falcons Both Falcons Both Falcons Both Falcons Both Falcons FEF80000 FEF80001 FEF80002 FEF80003 FEF80004 FEF80005 FEF80006 FEF80007 FEF80008 FEF80009 FEF807FF Writes not allowed Here ...

Page 160: ...s to the CSR Figure 3 9 Memory Map for 4 Byte Writes to the Internal Register Set 1907 9609 Upper Falcon Lower Falcon Upper Falcon Lower Falcon FEF80000 Lower Falcon FEF80004 FEF80008 FEF8000C FEF807FC 1908 9609 Both Falcons Both Falcons FEF80000 FEF80004 FEF80008 FEF8000C FEF807FC Writes not allowed Here ...

Page 161: ...the external register set are not duplicated from upper to lower so writes to them can be via the upper or lower Falcon Table 3 11 Register Summary BIT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 FEF80000 VENDID DEVID FEF80008 REVID aonly_en isa_hole adis ram fref ram spd0 ram spd1 chipu FEF80010 ram a en RA M A SIZ ram b en RA M B SIZ ram c en RA M C SIZ ...

Page 162: ... COL ADDRESS FEF80050 ROM A BASE rom_a_64 RO M A SIZ rom_a_rv rom a en rom a we FEF80058 ROM B BASE rom_b_64 RO MB SIZ rom_b_rv rom b en rom b we FEF80060 rom_a_spd0 rom_a_spd1 rom_b_spd0 rom_b_spd1 FEF80068 dpelog DPE_TT DPE_D P dpe_ckall dpe_me GWDP FEF80070 DPE_A FEF80078 DPE_D FEF80100 CTR32 FEF80400 PR_STAT1 FEF80500 PR_STAT2 FEF88000 FEF8FFF8 EXTERNAL REGISTER SET BIT 0 1 2 3 4 5 6 7 8 9 10 ...

Page 163: ... bits after local and power up reset are as defined below P The bit is affected by power up reset PURESET_ L The bit is affected by local reset HRESET_ X The bit is not affected by reset V The effect of reset on the bit is variable Vendor Device Register VENDID This read only register contains the value 1057 It is the vendor number assigned to Motorola Inc DEVID This read only register contains th...

Page 164: ...in at power up reset isa_hole When it is set isa_hole disables any of the DRAM or ROM Flash blocks from responding to PowerPC accesses in the range from 000A0000 to 000BFFFF This has the effect of creating a hole in the DRAM memory map for accesses to ISA When isa_hole is cleared there is no hole created in the memory map adis When adis is clear fast page mode operation is used for back to back pi...

Page 165: ...d so that these two bits are encoded to match the slowest devices that are used Also if any parts do not support EDO then these bits must set for Page Mode The only case in which it is permissible to set ram spd0 ram spd1 for 50ns EDO is when all parts are 50ns and all support EDO chipu indicates which of the two positions within the Falcon pair is occupied by this chip When chipu is low this chip...

Page 166: ...uency Register offset FEF80020 is within a factor of 2 of matching the actual 60x clock frequency ram a b c d en ram a b c d en enables accesses to the corresponding block of DRAM when set and disables them when cleared Address FEF80010 Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Name ram a en 0 0 0 0 ram a siz0 ram a siz1 ram a siz2 ram b en 0 0 0 0 r...

Page 167: ...ocks This includes clearing them to 000 if their corresponding blocks are not present Failure to do so will cause problems with addressing and with scrub error logging Table 3 13 Block_A B C D Configurations ram a b c d siz0 2 Block SIZE Devices Used Technology Comments 000 0MB Block Not Present 001 16MB 36 1Mx4 s 4Mb 8 1Mx18 s 16Mb 4 1Mx36 s 4Mb 1Mb SIMM DIMM 010 32MB 18 2Mx8 s 16Mb 011 64MB 144 ...

Page 168: ...dress as the CSR ROM Flash External Register Set or any other slave on the PowerPC bus CLK Frequency Register CLK FREQUENCY These bits should be programmed with the hexadecimal value of the operating CLOCK frequency in MHz that is 42 for 66 MHz When these bits are programmed this way the chip s Address FEF80018 Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 ...

Page 169: ...nts the generation of illegal cycles to the DRAM when refdis is updated rwcb When set causes reads and writes to DRAM from the PowerPC 60x bus to access check bit data rather than normal data The data path used for this mode is DH24 31 for check bit data controlled by the upper Falcon and DL24 31 for check bit data controlled by the lower Falcon Each 8 bit check bit location services 64 bits of no...

Page 170: ...t error This can be avoided by disabling scrub writes Also note that writing bad check bits can set the elog bit in the Error Logger Register The writing of check bits causes the Falcon to perform a read modify write to DRAM If the location to which check bits are being written has a single or double bit error data in the location may be altered by the write check bits operation To avoid this it i...

Page 171: ...om the DRAM array 2 During single beat writes data is written without correcting single bit errors that may occur on the read portion of the read modify write Check bits are generated for the data being written 3 During single beat writes the write portion of the read modify write happens regardless of whether there is a multiple bit error during the read portion No correction of data is attempted...

Page 172: ...iple bit error In fact the Falcon pair does not have a TEA_ signal pin and it assumes that the system does not implement TEA_ Error Logger Register The Error Logger and Error Address Registers behave the same as the other registers in that data written to the upper Falcon is automatically duplicated in the lower Falcon They also behave the same as the other registers in that status read from the u...

Page 173: ...bit Writing a one to the elog bit clears the elog bit for both the upper and lower Falcons Because of this software needs to check the status of both upper and lower Error Logger and Error Address Registers before it clears the elog bits Otherwise it could miss a logged error elog When set elog indicates that a single or a multiple bit error has been logged by its Falcon If elog is set by a multip...

Page 174: ... there was no error Note that if the logged error was non correctable then these bits are meaningless Refer to the section on ECC Codes for a decoding of the syndromes esblk0 esblk1 Together these two bits indicate which block of DRAM was being accessed when their Falcon logged a scrub error esblk0 esblk1 are 0 0 for Block A 0 1 for Block B 1 0 for Block C and 1 1 for Block D scof is set by its SB...

Page 175: ...1 These bits increment every time the scrubber completes a scrub of the entire DRAM When these bits reach binary 11 they roll over to binary 00 and continue These bitsare cleared by power up reset swen When set swen allows the scrubber to perform write cycles When cleared swen prevents scrubber writes rtest0 1 2 The rtest bits enable certain refresh counter test modes Table 3 14 shows their encodi...

Page 176: ...S is readable and writable for test purposes Note Within each block the most significant bits of ROW ADDRESS are used only when their DRAM devices are large enough to require them Table 3 14 rtest encodings rtest0 rtest1 rtest2 Test Mode selected 000 Normal Counter Operation 001 RA counts at 16x 010 RA counts at 256x 011 RA is always at roll value for CA 100 CA counts at 16x 101 CA counts at 256x ...

Page 177: ...se control bits define the base address for ROM Flash Block A ROM A BASE bits 0 11 correspond to PowerPC 60x address bits 0 11 respectively For larger ROM Flash sizes the lower significant bits of ROM A BASE are ignored This means that the block s base address will always appear at an even multiple of its size ROM A BASE is initialized to FF0 at power up or local bus reset Address FEF80050 Bit 0 1...

Page 178: ...n the PowerPC bus rom_a_64 indicates the width of ROM Flash device devices being used for Block A When rom_a_64 is cleared Block A is 16 bits wide where each Falcon interfaces to 8 bits When rom_a_64 is set Block A is 64 bits wide where each Falcon interfaces to 32 bits rom_a_64 matches the value that was on the CKD2 pin at power up reset It cannot be changed by software rom a siz The rom a siz co...

Page 179: ... address range selected by ROM A BASE are enabled When rom a en is cleared they are disabled rom a we When rom a we is set writes to Block A ROM Flash are enabled When rom a we is cleared they are disabled Note that if rom_a_64 is cleared only 1 byte writes are allowed If rom_a_64 is set only 4 byte writes are allowed The Falcon ignores other writes If a valid Table 3 16 rom_a_rv and rom_b_rv enco...

Page 180: ...t rom_x_64 rom_x_we Falcon Response write 1 byte X 0 0 Normal termination but no write to ROM Flash write 1 byte X 0 1 Normal termination write occurs to ROM Flash write 1 byte X 1 X No Response write 4 byte Misaligned X X No Response write 4 byte Aligned 0 X No Response write 4 byte Aligned 1 0 Normal termination but no write to ROM Flash write 4 byte Aligned 1 1 Normal termination write occurs t...

Page 181: ...SE and rom_b_siz should never be programmed such that ROM Flash Block B responds at the same address as the CSR DRAM External Register Set or any other slave on the PowerPC bus rom_b_64 indicates the width of ROM Flash device devices being used for Block B When rom_b_64 is cleared Block B is 16 bits wide where each Falcon interfaces to 8 bits When rom_b_64 is set Block B is 64 bits wide where each...

Page 182: ..._b_rv is initialized at power up reset to match the inverse of the value on the CKD1 pin rom b en When rom b en is set accesses to Block B ROM Flash in the address range selected by ROM B BASE are enabled When rom b en is cleared they are disabled rom b we When rom b we is set writes to Block B ROM Flash are enabled When rom b we is cleared they are disabled Refer back to Table 3 17 for more detai...

Page 183: ...rmine the access timing used for ROM Flash Block B See table above Address FEF80060 Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Name 0 0 rom a spd0 rom a spd1 0 0 rom b spd0 rom b spd1 Operation READ ZERO READ ZERO READ ZERO R R R W R W R R R W R W Reset X X X X X 0 PL 0 PL X X 0 PL 0 PL Table 3 19 Rom Speed Bit Encodings rom_a b_spd0 1 ROM Block A B A...

Page 184: ...the upper Falcon logs an error it updates its attribute bits dpe0 3 DATA PARITY ERROR ADDRESS and DATA PARITY ERROR DATA to match the results of the read cycle for the upper 60x data bus When the lower Falcon logs an error it updates its attribute bits to match the results of the read cycle for the lower 60x data bus While the logging of data parity errors by one Falcon in a pair does not affect t...

Page 185: ..._ckall is cleared the Falcon checks data parity on cycles when ta_ is asserted only during writes to the Falcon Pair Note The Falcon does not check parity during cycles in which there is a qualified artry_ at the same time as the ta_ When dpe_me is set the transition of a Falcon s dpelog bit from false to true causes it to pulse its machine check interrupt request pin MCP_ true When dpe_me is clea...

Page 186: ...ster DPE_D is the value on the Falcon s half of the 60x data bus at the time it last logged a 60x data bus parity error DPE_D updates only when the associated dpelog bit goes from 0 to 1 Address FEF80070 Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Name DPE_A Operation READ ONLY Reset 0 P Address FEF80078 Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ...

Page 187: ...gister Power Up Reset Status Register 1 PR_STAT1 power up reset status reflects the value that was on the RD0 RD31 signal pins at power up reset This register is read only Note For descriptions of how this register is used in the PowerPC series boards refer to the Falcon Controlled System Registers on page 1 16 especially the System Configuration Register SYSCR on page 1 17 and the Memory Configur...

Page 188: ...o the external devices is via the RD32 RD63 pins Reads to the external devices can be any size except burst Note that if the devices are less than 32 bits wide reads to unused data lanes will yield undefined data Note that writes are restricted to one or 4 byte length only 4 byte writes can be used for any size device data should be placed on the correct portion of the data bus so that valid data ...

Page 189: ...e parity checking for the address bus The Falcon does generate parity on the PowerPC data bus The appropriate registers in the MPC60x can be programmed to enable parity checking for the data bus Programming ROM Flash Devices Those who program devices to be controlled by the Falcon should make note of the address mapping that is shown in Table 3 9 and in Table 3 10 For example when using 8 bit devi...

Page 190: ...ecuting initially in the reset vector area FFF00000 FFFFFFFF Warning To satisfy DRAM component requirements before the memory is used at start up software must always wait at least 500µs between the initial setting of a bank s size bits to a non zero value and the first accessing of that bank These settings are in the DRAM Attributes Register offset FEF80010 The delay is intended to make sure that...

Page 191: ...sses within the block The data patterns do not matter as long as each 64 bit data pattern is unique The addresses to be written vary depending on the size that is currently being checked and are specified in Table 3 20 Table 3 20 shows how PowerPC addresses correspond to DRAM row column addresses 5 Read back all of the addresses that have been written If all of the addresses still contain exactly ...

Page 192: ...PowerPC 60x Address to DRAM Address Mappings RA 4 Block Size 6 0 1 2 3 4 5 6 7 8 9 10 11 12 16MB ROW A19 A18 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 COL A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 32MB ROW A18 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 COL A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 64MB ROW A18 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 COL A6 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 128MB R...

Page 193: ...bers the user needs to understand how the Falcon pair positions PowerPC data in DRAM See the section on Data Paths on page 3 64 for an explanation of this Note Table and Table 3 23 are the same whether the Falcon is configured as upper or as lower Table 3 21 Syndrome Codes Ordered by Bit in Error Bit Syndrome Bit Syndrome Bit Syndrome Bit Syndrome Bit Syndrome rd0 4A rd16 92 rd32 A4 rd48 29 ckd0 0...

Page 194: ... Syndrome Bit Syndrome Bit Syndrome Bit 00 20 ckd5 40 ckd6 60 80 ckd7 A0 C0 E0 rd45 01 ckd0 21 41 61 rd42 81 A1 rd38 C1 rd37 E1 02 ckd1 22 42 62 rd41 82 A2 rd35 C2 rd34 E2 03 23 rd31 43 rd30 63 83 rd29 A3 C3 E3 04 ckd2 24 44 64 rd55 84 A4 rd32 C4 rd33 E4 05 25 rd8 45 rd27 65 85 rd26 A5 C5 E5 06 26 rd9 46 rd23 66 86 rd22 A6 C6 E6 07 rd21 27 47 67 87 A7 rd52 C7 E7 08 ckd3 28 48 68 rd54 88 A8 rd51 C8...

Page 195: ...3 90 B0 rd50 D0 rd46 F0 11 31 rd49 51 rd43 71 91 rd39 B1 D1 F1 12 32 rd63 52 rd40 72 92 rd16 B2 D2 F2 13 rd17 33 53 73 93 B3 D3 rd60 F3 14 34 rd62 54 rd59 74 94 rd56 B4 D4 F4 rd12 15 rd11 35 55 75 95 B5 D5 F5 16 rd10 36 56 76 96 B6 D6 F6 17 37 57 77 97 B7 D7 F7 18 38 rd61 58 rd58 78 98 rd57 B8 D8 F8 19 rd7 39 59 79 99 B9 D9 F9 1A rd6 3A 5A 7A rd20 9A BA DA FA 1B 3B 5B 7B 9B BB DB FB 1C rd5 3C 5C 7...

Page 196: ...ure 3 65 3 Figure 3 10 PowerPC Data to DRAM Data Correspondence 1909 9609 Lower Falcon s DRAM Upper Falcon s DRAM ra12 1 PowerPC Data ra12 0 ra12 1 ra12 0 rd63 dl31 rd32 rd31 rd0 rd63 rd32 rd31 rd0 dl0 dh31 dh0 a 27 28 0 a 27 28 1 a 27 28 2 a 27 28 3 ...

Page 197: ...1 0 0 dl 00 07 0 rd 00 07 0 0 dl 08 15 0 rd 08 15 0 0 dl 16 23 0 rd 16 23 0 0 dl 24 31 0 rd 24 31 0 1 dh 00 07 0 rd 32 39 0 1 dh 08 15 0 rd 40 47 0 1 dh 16 23 0 rd 48 55 0 1 dh 24 31 0 rd 56 63 0 1 dl 00 07 0 rd 32 39 0 1 dl 08 15 0 rd 40 47 0 1 dl 16 23 0 rd 48 55 0 1 dl 24 31 0 rd 56 63 1 0 dh 00 07 1 rd 00 07 1 0 dh 08 15 1 rd 08 15 1 0 dh 16 23 1 rd 16 23 1 0 dh 24 31 1 rd 24 31 1 0 dl 00 07 1...

Page 198: ...ter literature 3 67 3 1 1 dh 16 23 1 rd 48 55 1 1 dh 24 31 1 rd 56 63 1 1 dl 00 07 1 rd 32 39 1 1 dl 08 15 1 rd 40 47 1 1 dl 16 23 1 rd 48 55 1 1 dl 24 31 1 rd 56 63 Table 3 23 PowerPC Data to DRAM Data Mapping Continued PowerPC DRAM Array ...

Page 199: ...pace accesses The following table shows the IDSEL assignments for the PCI devices on the MTX Table 4 1 IDSEL Mapping for PCI Devices Device Number Field PCI Address Line IDSEL Connection 0b0_0000 AD31 Raven PCI Host Bridge MPIC ASIC 0b0_1011 AD11 PCI ISA Bridge 0b0_1100 AD12 SCSI Device 0b0_1101 AD13 Unused 0b0_1110 AD14 Ethernet Device 0b0_1111 AD15 Unused 0b1_0000 AD16 PMC or 32 bit PCI Slot 1 0...

Page 200: ...re as follows Upon power up the PIB defaults to a round robin arbitration mode The relative priority of each request grant pair can be customized via the PCI Priority Control Register 1 Refer to the W83C553 Data Book listed in Appendix A Related Documentation for additional details Table 4 2 PCI Arbitration Assignments PCI BUS REQUEST PCI Master s PIB internal PIB CPU Raven ASIC Request 0 PMC PCI ...

Page 201: ...Interrupt Handling The interrupt architecture of the MTX series SBC is shown in the following figure Figure 4 1 MTX Series Interrupt Architecture 11559 00 9609 PIB 8529 Pair Processor INT_ MCP_ Processor INT_ MCP_ RavenMPIC INT SERR_ PERR_ PCI Interrupts ISA Interrupts ...

Page 202: ...or Interrupt Controller for details on the Raven MPIC The following table shows the interrupt assignments for the Raven MPIC on the MTX series Table 4 3 Raven MPIC Interrupt Assignments MPIC IRQ Edge Level Polarity Interrupt Source Notes IRQ0 Level High PIB 8259 1 IRQ1 Edge Low Falcon ECC Error 2 IRQ2 Level Low PCI Ethernet 3 IRQ3 Level Low PCI SCSI 3 IRQ4 Level Low Reserved IRQ5 Level Low Reserve...

Page 203: ...ch of the interrupt lines can be configured for either edge sensitive mode or level sensitive mode by programming the appropriate ELCR registers in the PIB There is also support for four PCI interrupts PIRQ3_ PIRQ0_ The PIB has four PIRQ Route Control Registers to allow each of the PCI interrupt lines to be routed to any of eleven ISA interrupt lines IRQ0 IRQ1 IRQ2 IRQ8_ and IRQ13 are reserved for...

Page 204: ...Handler Block Diagram 1897 9609 IRQx PIRQ Route Control Register PIRQ Route Control Register PIRQ Route Control Register PIRQ Route Control Register PIRQ3_ IRQx PIRQ2_ IRQx PIRQ1_ IRQx PIRQ0_ Controller 2 INT2 IRQ8 IRQ9 IRQ11 IRQ10 IRQ12 IRQ13 IRQ14 IRQ15 0 1 2 3 4 5 6 7 Controller 1 INT1 Timer1 Counter0 IRQ1 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 0 1 2 3 4 5 6 7 INTR ...

Page 205: ...ge High Timer 1 Counter 0 1 2 IRQ1 Edge High Keyboard 2 3 10 IRQ2 Edge High Cascade Interrupt from INT2 3 IRQ8_ INT2 Edge Low ABORT Switch Interrupt 4 IRQ9 Level High Z8536 CIO 3 4 Z85230 ESCC 5 IRQ10 PIRQ0_ Level Low PCI Ethernet Interrupt 3 5 6 6 IRQ11 Level Low Not Used 6 7 IRQ12 Edge High Mouse 8 IRQ13 Edge High Not Used 6 9 IRQ14 PIRQ2_ Level Low PCI SCSI Interrupt 3 5 6 10 IRQ15 PIRQ3_ Level...

Page 206: ...Q Route Control Registers in the PIB The PCI to ISA interrupt assignments in this table are suggested Each ISA IRQ to which a PCI interrupt is routed to MUST be programmed for level sensitive mode Use this routing for PCI interrupts only when the Raven MPIC is either not present or not used 6 The Raven MPIC when present should be used for these interrupts ISA DMA Channels Refer to Chapter 1 Board ...

Page 207: ...of the Raven MPIC appropriately Error Notification and Handling The Raven and Falcon chipset can detect certain hardware errors and can be programmed to report these errors via the Raven MPIC interrupts or Machine Check Interrupt Table 4 5 Reset Sources and Devices Affected Device Affected Processor s Raven ASIC Falcon Chipset PCI Devices ISA Devices Power On 3 3 3 3 3 Reset Switch 3 3 3 3 3 Watch...

Page 208: ...cycle normally Load Present undefined data to the MPC master Generate interrupt via Raven MPIC if so enabled Generate Machine Check Interrupt to the Processor s if so enabled PCI Target Abort Store Discard write data and terminate bus cycle normally Load Return all 1 s and terminate bus cycle normally Generate interrupt via Raven MPIC if so enabled Generate Machine Check Interrupt to the Processor...

Page 209: ...rently big endian PCI is inherently little endian and the VMEbus is big endian things do get rather confusing The following figures shows how the MTX series handles the endian issue in big endian and little endian modes Figure 4 3 Big Endian Mode Big Endian PROGRAM 1898 9609 Raven Universe Falcons DRAM Big Endian Little Endian Big Endian Little Endian PCI Local Bus VMEbus N way Byte Swap N way Byt...

Page 210: ...h big endian and little endian mode However it always treats the external processor memory bus as big endian by performing address rearrangement and reordering when running in little endian mode EA Modification XOR Raven Falcons DRAM Big Endian Little Endian Little Endian PCI Local Bus EA Modification 60X System Bus Big Endian Little Endian Little Endian PROGRAM ...

Page 211: ...operate in little endian mode regardless of the mode of operation in the processor s domain PCI SCSI SCSI is byte stream oriented with the byte having the lowest address in memory being the first one to be transferred regardless of the endian mode Since address invariance is maintained by the Raven in both little endian and big endian mode there should be no endian issues for the SCSI data Big end...

Page 212: ...ase Size Register Determining PHB Type The initialization software can determine the PCI Host Bridge PHB type by reading its Device ID To be backward compatible with the older Genesis products which used the MPC105 as the PHB the Raven defaults the addresses of its CONADD register and its CONDAT register to 80000CF8 and 80000CFC respectively The alternative method is to read the CPUTYPE from the O...

Page 213: ... or HTML format visit http www motorola com computer literature Manufacturers Documents For additional information refer to the following table for manufacturers data sheets or user s manuals As an additional help a source for the listed document is provided Please note that while these sources have been verified the information is subject to change without notice Table A 1 Motorola Computer Group...

Page 214: ...tribution Center for Motorola Telephone 1 800 441 2447 FAX 602 994 6430 or 303 675 2150 Web Site http merchant hibbertco com mtrlext E mail ldcformotorola hibbertco com OR IBM Microelectronics PowerPC603 EM603e User Manual PowerPC604e User Manual Web Site http www chips ibm com techlib products powerpc manuals MPC603EUM D MPC604EUM AD G522 0297 00 G522 0330 00 PowerPCTM Microprocessor Family The P...

Page 215: ...ectronics http eu st com stonline index shtml M48T59 SYM 53CXX was NCR 53C8XX Family PCI SCSI I O Processor Data Manual LSI Logic Corporation http www lsilogic com SYM53C875 875E Data Manual SCC Serial Communications Controller User s Manual for Z85230 and other Zilog parts http www zilog com pdfs serial scc_escc_iscc_manual contents html SCC ESCC User s Manual Z8536 CIO Counter Timer and Parallel...

Page 216: ...stem Interface 2 SCSI 2 Draft Document Global Engineering Documents http global ihs com index cfm X3 131 1990 IEEE Common Mezzanine Card Specification CMC Institute of Electrical and Electronics Engineers Inc http standards ieee org catalog P1386 Draft 2 0 IEEE PCI Mezzanine Card Specification PMC Institute of Electrical and Electronics Engineers Inc http standards ieee org catalog P1386 1 Draft 2...

Page 217: ...C Microprocessor Common Hardware Reference Platform A System Architecture CHRP Version 1 0 Literature Distribution Center for Motorola Telephone 1 800 441 2447 FAX 602 994 6430 or 303 675 2150 http merchant hibbertco com mtrlext E mail ldcformotorola hibbertco com OR Morgan Kaufmann Publishers Inc Telephone 415 392 2665 Telephone 1 800 745 7323 http www mkp com books_catalog ISBN 1 55860 394 8 Pow...

Page 218: ...it ordering convention 3 1 block diagram 2 3 block diagram description 2 52 block diagrams 3 2 blocks A and or B present blocks C and D not present 3 22 blocks A and or B present blocks C and or D present 3 23 bus interface 60x 3 12 byte ordering xxii byte definition xxi C cache coherency 3 13 cache coherency restrictions 3 14 chip defaults 3 24 CHRP compliant memory map 2 4 CHRP memory map exampl...

Page 219: ...des 3 62 error detection 3 14 error handling 2 16 Error Logger Register 3 41 error logging 3 18 error notification and handling 4 9 4 10 error reporting 3 17 ERROR_ADDRESS 3 44 ERROR_SYNDROME 3 43 esbt 3 43 escb 3 42 esen 3 42 exceptions 4 8 External Register Set 3 57 external register set 3 24 external register set reads and writes 3 25 External Source Destination Registers 2 70 External Source V...

Page 220: ...n Register MEMCR 1 18 memory map for 4 byte reads to the CSR 3 29 memory map for 4 byte writes to the internal register set and test SRAM 3 29 memory map for byte reads to the CSR 3 27 memory map for byte writes to the internal register set and test SRAM 3 28 memory maps 1 5 mien 3 41 MK48T59 access registers 1 24 module configuration and status registers 1 25 Motorola Computer Group documents A 1...

Page 221: ...ide 8 Bits per Falcon 3 20 PowerPC 60x to ROM Flash Address Map ping when ROM Flash is 64 Bits Wide 32 Bits per Falcon 3 21 power up reset status bit 3 38 Power Up Reset Status Register 1 3 56 Power Up Reset Status Register 2 3 57 PR_STAT1 bits 3 56 PR_STAT2 bits 3 57 PREP memory map example 1 8 Prescaler Adjust Register 2 25 processor CHRP memory map 1 6 Processor Init Register 2 63 processor mem...

Page 222: ... Flash A Width control bit 3 47 ROM Flash B Base Address control bits 3 50 ROM Flash B Base Size Register 3 50 ROM Flash B size encoding bits 3 51 ROM Flash B Width control bit 3 50 ROM FLASH bank default 4 14 ROM Flash initialization 4 14 ROM Flash speeds 3 11 rom_a_64 bit 3 47 ROM_A_BASE 3 46 rom_a_en bit 3 48 rom_a_rv bit 3 48 rom_a_siz bit 3 47 rom_a_we bit 3 48 rom_b_64 bit 3 50 ROM_B_BASE bi...

Page 223: ...ition xxii trun 3 52 U Universe s involvement 4 14 upper lower chip status bit 3 34 URLs uniform resource locators A 5 V Vendor ID Device ID Registers 2 38 Vendor ID Device ID Registers 2 22 Vendor Identification Register 2 63 Vendor Device Register 3 32 VMEbus domain 4 14 W W83C553 PIB registers 1 23 when MPC devices are big endian 2 15 when MPC devices are little endian 2 16 word definition xxii...

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