Motorola MPC860 PowerQUICC, User Manual

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Part I. Overview
MOTOROLA Chapter 1. MPC860 Overview 1-7
1.4 System Interface Unit (SIU)
The SIU on the MPC860 integrates general-purpose features useful in almost any 32-bit
processor system, enhancing the performance provided by the system integration module
(SIM) on the MC68360 QUICC device.
Dynamic bus sizing is supported. Bus sizing allows 8-, 16-, and 32-bit peripherals and
memory to exist in the 32-bit system bus mode.
The SIU also provides power management functions, reset control, PowerPC decrementer,
PowerPC time base and the real-time clock.
The memory controller supports up to eight memory banks with glueless interfaces to
DRAM, SRAM, SSRAM, EPROM, ßash EPROM, SRDRAM, EDO and other peripherals
with two-clock access to external SRAM and bursting support. It provides variable block
sizes from 32 Kbytes to 256 Mbytes. The memory controller provides 0Ð30 wait states for
each bank of memory and can use address type matching to qualify each memory bank
access. It provides four byte enable signals, one output enable signal and one boot chip
select available at reset.
The DRAM interface supports port sizes of 8, 16, and 32 bits. Memory banks can be
deÞned in depths of 256 or 512 Kbytes or 1, 2, 4, 8, 16, 32, or 64 Mbytes for all port sizes.
In addition the memory depth can be deÞned as 64 Kbytes and 128 Kbytes for 8-bit memory
or 128 Mbytes and 256 Mbytes for 32-bit memory. The DRAM controller supports page
mode access for successive transfers within bursts. The MPC860 supports a glueless
interface to one bank of DRAM while external buffers are required for additional memory
banks. The refresh unit provides CAS before RAS, a programmable refresh timer, refresh
active during external reset, disable refresh mode, and stacking up to 7 refresh cycles. The
DRAM interface uses a programmable state machine to support almost any memory
interface.
1.5 PCMCIA Controller
The PCMCIA interface is a master (socket) controller and is compliant with release 2.1.
The interface supports up to two independent PCMCIA sockets requiring only external
transceivers/buffers. The interface provides 8 memory or I/O windows where each window
can be allocated to a particular socket. If only one PCMCIA port is being used, the unused
PCMCIA port may be used as general-purpose input with interrupt capability.
1.6 Power Management
The MPC860 supports a wide range of power management features including full on, doze,
sleep, deep sleep, and low power stop. In full on mode the MPC860 processor is fully
powered with all internal units operating at the full speed of the processor. A gear mode is
provided which is determined by a clock divider, allowing the operating system to reduce
the operational frequency of the processor. Doze mode disables core functional units other