Motorola MPC860 PowerQUICC, User Manual

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27-18 MPC860 PowerQUICC UserÕs Manual MOTOROLA
Part V. The Communications Processor Module
After ETX, a BCS is expected; then the buffer should be closed. Hunt mode should be
entered when a line turnaround occurs. ENQ characters are used to stop sending a block
and to designate the end of the block for a receiver, but no CRC is expected. After control
character reception, set SCCM[RCH] to reenable interrupts for each byte of data received.
27.17 SCC BISYNC Programming Example
This BISYNC controller initialization example for SCC2 uses an external clock. The
controller is conÞgured with RTS2, CTS2, and CD2 active. Both the receiver and
transmitter use CLK3.
1. ConÞgure the port A pins to enable TXD2 and RXD2. Write PAPAR[12,13] and
PAODR[12,13] with ones and PADIR[12,13] with zeros.
2. ConÞgure the port C pins to enable RTS2, CTS2, and CD2. Set PCSO[8, 9] and
PCPAR[14]; clear PCPAR[8, 9] and PCDIR[8, 9, 14].
3. ConÞgure port A to enable CLK3. Set PAPAR[5] and clear PADIR[5].
4. Connect CLK3 to SCC2 using the serial interface. Set SICR[R2CS, T2CS] to 0b110.
5. Connect the SCC2 to the NMSI and clear SICR[SC2].
6. Initialize the SDMA conÞguration register (SDCR).
7. Assuming one RxBD at the beginning of dual-port RAM followed by one TxBD,
write RBASE with 0x0000 and TBASE with 0x0008.
8. Program CPCR (for SCC1 write 0x0041) to execute
INIT RX AND TX PARAMETERS
.
This updates RBPTR and TBPTR to the new values of RBASE and TBASE.
9. Write RFCR and TFCR with 0x10 for normal operation.
10. Write MRBLR with the maximum number of bytes per receive buffer. For this case,
assume 16 bytes, so MRBLR = 0x0010.
11. Write PRCRC with 0x0000 to comply with CRC16.
12. Write PTCRC with 0x0000 to comply with CRC16.
13. Clear PAREC for clarity.
14. Write BSYNC with 0x8033, assuming a SYNC value of 0x33.
15. Write DSR with 0x3333.
Table 27-15. Control Characters
Control Characters E B H
ETX 0 1 1
ITB 0 1 0
ETB 0 1 1
ENQ 0 0 0
Next entry 0 X X