Motorola MPC860 PowerQUICC, User Manual

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MOTOROLA Chapter 26. SCC Asynchronous HDLC Mode and IrDA 26-7
Part V. The Communications Processor Module
26.9.2 Data Synchronization Register (DSR)
The data synchronization register (DSR) is reserved in asynchronous HDLC mode. It
should be left in its reset state of 0x7E7E.
26.10 Programming the Asynchronous HDLC
Controller
Asynchronous HDLC mode is selected for an SCC by writing GSMR_L[MODE] =
0b0110. The asynchronous HDLC controller uses the same buffer and BD data structure as
other modes and supports multibuffer operation. Receive errors are reported through the
RxBD; transmit errors are reported through the TxBD. Status line information (CD and
CTS) is reported through the port C pins; a maskable interrupt is generated when the status
of either line changes.
26.11 Asynchronous HDLC Commands
The transmit and receive commands are issued to the CP command register (CPCR).
Transmit commands are described in Table 26-3. After a hardware or software reset and a
channel is enabled in the GSMR, the transmitter starts polling the Þrst BD in the TxBD
table every 8 transmit clocks, or immediately if TODR[TOD] = 1, and begins sending data
if TxBD[R] is set.
Table 26-2. Asynchronous HDLC-Specific GSMR Field Descriptions
Name Description
IRP Infrared Rx polarity (GSMR_H[13]). Determines the polarity of the received signal when SCC2 uses IrDA
encoding/decodingÑfor SCC2 only. See Section 26.18, ÒIrDA Encoder/Decoder (SCC2 Only).Ó
0 Active high polarity. An active high pulse is decoded as 0.
1 Active low polarity. An active low pulse is decoded as 0.
RFW Rx FIFO width (GSMR_H[26])
0 Do not use.
1 Low-latency operationÑfor character-oriented protocols like UART, BISYNC, and asynchronous HDLC.
The Rx FIFO is 8 bits wide and the Rx FIFO is one-fourth its normal size (8 bytes for SCC1; 4 bytes for
SCC otherwise). This allows each character to be written to the buffer without waiting for 32 bits to be
received.
SIR Serial infrared encodingÑfor SCC2 only (GSMR_L[0]). Setting SIR activates the serial infrared
coder/encoder.Reserved, should be cleared. See Section 26.18, ÒIrDA Encoder/Decoder (SCC2 Only).Ó
TDCR/
RDCR Tx/Rx divide clock rate (GSMR_L[14Ð15/16Ð17]). For asynchronous HDLC mode, 8
´
, 16
´
, or 32
´
must be
chosen. Set TDCR = RDCR in most applications.
00 Do not use.
01 8
´
clock mode (do not use for IrLAP).
10 16
´
clock mode.
11 32
´
clock mode (do not use for IrLAP).