Motorola MPC860 PowerQUICC, User Manual

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MOTOROLA Chapter 16. Memory Controller 16-29
Part IV. Hardware Interface
Figure 16-30. Asynchronous External Master, GPCM-Handled Memory Access
Timing (TRLX = 0)
When an external asynchronous master performs accesses a memory device via the GPCM
in the memory controller, ORx[CSNT] has no effect.
For a comprehensive discussion of external master interfacing, see Section 16.8, ÒExternal
Master Support.Ó
16.5.4 Special Case: Bursting with External Transfer Acknowledge:
The memory controller supports bursting to and from an external slave that supplies its own
TA termination signal in the following special case:
The GPCM is the subsystem of the memory controller that supports provision of chip-select
signals (CSx) for slaves that provide their TA signal external to the MPC8560 (ORx[SETA]
= 1). However, the GPCM keeps its chip-select asserted only until the Þrst TA is sampled.
The GPCM cannot be used to burst to an external device the requires that the chip-select
signal remain asserted throughout a burst transaction. However, if the device requires only
that the chip-select be asserted up to the Þrst data beat of the burst, it is possible to burst to
this device. The user can program ORx[SETA] = 1 and ORx[BIH] = 0 to enable this
operation. This is the only case in which it is valid to program ORx[BIH] = 0 for a
chip-select controlled by the GPCM.
During a burst cycle, the user sees the chip-select assertion follow the same pattern as for a
single-beat cycle. However, BI remains negated, and the burst continues for the following
data beats after the negation of chip-select following TA for the Þrst data beat.
Clock
Address
AS
TA
CS
WE
OE
Data