Motorola MPC860 PowerQUICC, User Manual

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MOTOROLA Chapter 14. MPC860 External Bus Interface 14-7
Part IV. Hardware Interface
¥ ArbitrationÑA device requests bus access
¥ Address phaseÑThe address and the transfer attributes are generated.
¥ Data phaseÑAny data to be transferred is transferred. The data phase may transfer
a single beat of data (4 bytes or less) for nonburst operations, a 4-beat data burst (4
´
4 bytes), an 8-beat data burst (8
´
2 bytes), or a 16-beat data burst (16
´
1 bytes).
¥ TerminationÑThe transfer completes successfully or it was aborted.
14.4.2 Single-Beat Transfer
During the data transfer, the master writes data to the slave or reads data from the slave. On
a write cycle, the master drives the data as soon as it can, but not before the cycle after the
address transfer phase. The master must consider the one dead clock cycle switching
between drivers to avoid electrical contention. The master can stop driving the data bus as
soon as it samples TA asserted on the rising edge of CLKOUT. On a read cycle the master
accepts the data bus contents as valid at the rising edge of CLKOUT in which TA is sampled
asserted.
14.4.2.1 Single-Beat Read Flow
The basic read cycle begins with a bus arbitration, followed by the address transfer, then the
data transfer. The following ßow and timing diagrams show the handshakes applicable to
the Þxed transaction protocol.
Figure 14-4. Basic Flow Diagram of a Single-Beat Read Cycle
MASTER
Bus Request (BR)
Receives Bus Grant (BG) from arbiter
Asserts Bus Busy (BB) if no other master is driving
Asserts Transfer Start (TS)
Drives address and attributes
Receives Address
Returns data
Asserts Transfer Acknowledge (TA)
Receives data
SLAVE