Motorola MPC860 PowerQUICC, User Manual

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8-20 MPC860 PowerQUICC UserÕs Manual MOTOROLA
Part II. PowerPC Microprocessor Module
8.4.5 Data Cache Block Flush (dcbf)
The effective address is computed, translated, and checked for protection violations as
deÞned in the PowerPC architecture. This instruction is treated as a load with respect to
address translation and memory protection.
If the address hits in the cache, and the block is in the modiÞed-valid state, the modiÞed
block is written back to memory and the cache block is placed in the invalid state. If the
address hits in the cache, and the cache block is in the unmodiÞed-valid state, the cache
block is placed in the invalid state. If the address misses in the cache, no action is taken.
If a bus error occurs while executing the dcbf instruction, DC_CST[CCER1] is set and a
machine check exception is generated. The data of the cache block ßagged by the bus error
is retrieved from the copyback buffer, not from the data cache. See Section 8.3.2.1,
ÒReading Data Cache Tags and Copyback Buffer,Ó for more information.
The function of this instruction is independent of the memory/cache access attributes. The
dcbf instruction executes regardless of whether the cache is disabled or the cache block is
locked.
8.4.6 Data Cache Block Invalidate (dcbi)
The effective address is computed, translated, and checked for protection violations as
deÞned in the PowerPC architecture. This instruction is treated as a store with respect to
address translation and memory protection.
If the address hits in the cache, the cache block is placed in the invalid state, regardless of
whether the data is modiÞed. If the address misses in the cache, no action is taken. Because
this instruction may effectively destroy modiÞed data, it is privileged (that is, dcbi is
available only to programs at the supervisor privilege level, MSR[PR] = 0).
The function of this instruction is independent of the memory/cache access attributes. The
dcbi instruction executes regardless of whether the cache is disabled or the cache block is
locked.
8.5 Instruction Cache Operations
When the instruction MMU is enabled (MSR[IR] = 1), the instruction cache operates as
deÞned by the memory/cache access attributes. When the instruction MMU is disabled
(MSR[IR] = 0), the instruction cache operates as deÞned by the default instruction memory
access attributes. The default state of the caching-inhibited/caching-allowed attribute is
determined by MI_CTR[CIDEF], and the entire memory space defaults to the guarded
attribute. See Chapter 9, ÒMemory Management Unit (MMU),Ó for more information.
An instruction cache access begins with an instruction fetch request from the instruction
sequencer in the PowerPC core. As shown in Figure 8-1, bits 21Ð27 of the instruction
address provide the index to select a set (0Ð127) within the instruction cache array. The tags
from both ways of the set are compared against bits 0Ð20 of the instruction address. If a