Motorola MPC860 PowerQUICC, User Manual

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8-18 MPC860 PowerQUICC UserÕs Manual MOTOROLA
Part II. PowerPC Microprocessor Module
ßushed from the data cache array. See Section 8.3.2.1, ÒReading Data Cache Tags and
Copyback Buffer,Ó for more information.
The PowerPC cache control instructions dcbst and dcbf can also be used to ßush the data
cache. Note that the PowerPC cache control instructions operate on effective addresses that
are translated while the DC_CST ßush cache block command operates on a physically
addressed block contained within the data cache. When there is a need to restrict the
ßushing to a speciÞc memory area or to maintain architectural compliance, it is
recommended to use the PowerPC cache control instructions; when there is a need to ßush
the entire data cache and there is no concern for architectural compliance, using the
DC_CST ßush cache block command is more efÞcient.
8.4 PowerPC Cache Control Instructions
The PowerPC architecture deÞnes instructions for controlling both the instruction and data
caches. The cache control instructions, icbi, dcbt, dcbtst, dcbz, dcbst, dcbf, and dcbi, are
intended for the management of the local caches. In the following descriptions, the
memory/cache access attributes refer to the write-through/write-back,
caching-inhibited/caching-allowed, guarded/not guarded status of the addressed page.
Note that the MPC860 does not broadcast cache control instructions nor does it snoop such
broadcasts.
A TLB miss exception is generated if the effective address of one of these instructions
cannot be translated and data address relocation is enabled. A TLB error exception is
generated if these instructions encounter a TLB protection violation.
8.4.1 Instruction Cache Block Invalidate (icbi)
The effective address is computed, translated, and checked for protection violations as
deÞned in the PowerPC architecture. This instruction is treated as a store with respect to
address translation and memory protection. If the address hits an unlocked block in the
instruction cache, the cache block is placed in the invalid state. If the address misses in the
instruction cache or if the block is locked, no action is taken. The function of this instruction
is independent of the memory/cache access attributes.
This command is not privileged and has no associated error cases. The instruction cache
performs the icbi instruction in one clock cycle. To accurately calculate the latency of this
instruction, bus latency should be taken into consideration.
8.4.2 Data Cache Block Touch (dcbt) and
Data Cache Block Touch for Store (dcbtst)
The Data Cache Block Touch (dcbt) and Data Cache Block Touch for Store (dcbtst)
instructions provide potential system performance improvement through the use of
software-initiated prefetch hints. The MPC860 treats these instructions identically (that is,
a dcbtst instruction behaves exactly the same as a dcbt instruction on the MPC860).