Motorola MPC8240, User Manual, Page: 78 / 642

2-10 MPC8240 Integrated Processor User’s Manual
Detailed Signal Descriptions
2.2.1.4 Parity (PAR)
The PCI parity (PAR) signal is both an input and output signal on the MPC8240. See
Section 7.6.1, “PCI Parity,” for more information on PCI parity.
2.2.1.4.1 Parity (PAR)—Output
Following is the state meaning for PAR as an output signal.
State Meaning Asserted—This signal is driven by the MPC8240 to indicate odd
parity across the AD[31:0] and C/BE[3:0] signals (driven by the
MPC8240) during the address and data phases of a transaction.
Negated—Indicates even parity across the AD[31:0] and
C/BE[3:0] signals driven by the MPC8240 during address and data
phases.
2.2.1.4.2 Parity (PAR)—Input
Following is the state meaning for PAR as an input signal.
State Meaning Asserted—Indicates odd parity driven by another PCI master or the
PCI target during read data phases.
Negated—Indicates even parity driven by another PCI master or the
PCI target during read data phases.
2.2.1.5 Command/Byte Enable (C/BE[3:0])
The four command/byte enable (C/BE[3:0]) signals are both input and output signals on the
MPC8240.
2.2.1.5.1 Command/Byte Enable (C/BE[3:0])—Output
Following is the state meaning for C/BE[3:0] as output signals.
State Meaning Asserted/Negated—During the address phase, C/BE[3:0] define the
bus command of the transaction initiated by the MPC8240 as a PCI
master. Table 2-3 summarizes the PCI bus command encodings. See
Section 7.3.2, “PCI Bus Commands,” for more detailed information
on the bus commands.
During the data phase, C/BE[3:0] are used as byte enables. Byte
enables determine which byte lanes carry meaningful data. The
C/BE0 signal applies to the least-significant byte.