Motorola MPC8240, User Manual, Page: 56 / 642

1-8 MPC8240 Integrated Processor User’s Manual
Processor Core Overview
The processor core is a superscalar processor that can issue and retire as many as three
instructions per clock. Instructions can execute out of order for increased performance;
however, the processor core makes completion appear sequential.
The processor core integrates five execution units—an integer unit (IU), a floating-point
unit (FPU), a branch processing unit (BPU), a load/store unit (LSU), and a system register
unit (SRU). The ability to execute five instructions in parallel and the use of simple
instructions with rapid execution times yield high efficiency and throughput. Most integer
instructions execute in one clock cycle. On the processor core, the FPU is pipelined so a
single-precision multiply-add instruction can be issued and completed every clock cycle.
The processor core supports integer data types of 8, 16, and 32 bits, and floating-point data
types of 32 and 64 bits.
The processor core provides independent on-chip, 16-Kbyte, four-way set-associative,
physically addressed caches for instructions and data and on-chip instruction and data
memory management units (MMUs). The MMUs contain 64-entry, two-way
set-associative, data and instruction translation lookaside buffers (DTLB and ITLB) that
provide support for demand-paged virtual memory address translation and variable-sized
block translation. The TLBs and caches use a least recently used (LRU) replacement
algorithm. The processor also supports block address translation through the use of two
independent instruction and data block address translation (IBAT and DBAT) arrays of four
entries each. Effective addresses are compared simultaneously with all four entries in the
BAT array during block translation. In accordance with the PowerPC architecture, if an
effective address hits in both the TLB and BAT array, the BAT translation takes priority.
As an added feature to the processor core, the MPC8240 can lock the contents of one to
three ways in the instruction and data cache (or an entire cache). For example, this allows
embedded applications to lock interrupt routines or other important (time-sensitive)
instruction sequences into the instruction cache. It allows data to be locked into the data
cache, which may be important to code that must have deterministic execution.
The processor core has a selectable 32- or 64-bit data bus and a 32-bit address bus. The
processor core supports single-beat and burst data transfers for memory accesses, and
supports memory-mapped I/O operations.
Figure 1-5 provides a block diagram of the MPC8240 processor core that shows how the
execution units (IU, FPU, BPU, LSU, and SRU) operate independently and in parallel. Note
that this is a conceptual diagram and does not attempt to show how these features are
physically implemented on the chip.