4-50
MPC8240 Integrated Processor User’s Manual
Memory Control Configuration Registers
18–15
RAS
6P
0000
RAS assertion interval for CBR refresh. For DRAM/EDO only. These bits
control the number of clock cycles RAS is held asserted during CBR refresh.
The value for RAS
6P
depends on the specific DRAMs used and the frequency
of the memory interface. See Section 6.3.10, “FPM or EDO DRAM Refresh,”
for more information.
0001 1 clock
0010 2 clocks
0011 3 clocks
...
...
1111 15 clocks
0000 16 clocks
14–12
CAS
5
000
CAS assertion interval for page mode access. For DRAM/EDO only. These bits
control the number of clock cycles CAS is held asserted during page mode
accesses. The value for CAS
5
depends on the specific DRAMs used and the
frequency of the memory interface. Note that when ECC is enabled, CAS
5
+
CP
4
must equal four clock cycles. See Section 6.3.5, “FPM or EDO DRAM
Interface Timing,” for more information.
001 1 clock
010 2 clocks
011 3 clocks
...
...
111 7 clocks
000 8 clocks
11–9
CP
4
000
CAS precharge interval. For DRAM/EDO only. These bits control the number
of clock cycles that CAS must be held negated in page mode (to allow for
column precharge) before the next assertion of CAS. Note that when ECC is
enabled, CAS
5
+ CP
4
must equal four clock cycles. See Section 6.3.5,
“FPM or EDO DRAM Interface Timing,” for more information.
001 1 clock
010 2 clocks
011 reserved
...
...
111 Reserved
000 Reserved
8–6
CAS
3
000
CAS assertion interval for the first access. For DRAM/EDO only. These bits
control the number of clock cycles CAS is held asserted during a single beat or
during the first access in a burst. The value for CAS
3
depends on the specific
DRAMs used and the frequency of the memory interface. See Section 6.3.5,
“FPM or EDO DRAM Interface Timing,” for more information.
001 1 clock
010 2 clocks
011 3 clocks
...
...
111 7 clocks
000 8 clocks
Table 4-40. Bit Settings for MCCR3—0xF8 (Continued)
Bits
Name
Reset
Value
Description
Summary of Contents for MPC8240
Page 1: ...MPC8240UM D Rev 1 1 2001 MPC8240 Integrated Processor User s Manual ...
Page 38: ...xviii MPC8240 Integrated Processor User s Manual TABLES Table Number Title Page Number ...
Page 48: ...xlviii MPC8240 Integrated Processor User s Manual Acronyms and Abbreviations ...
Page 312: ...6 94 MPC8240 Integrated Processor User s Manual ROM Flash Interface Operation ...
Page 348: ...7 36 MPC8240 Integrated Processor User s Manual PCI Host and Agent Modes ...
Page 372: ...8 24 MPC8240 Integrated Processor User s Manual DMA Register Descriptions ...
Page 394: ...9 22 MPC8240 Integrated Processor User s Manual I2O Interface ...
Page 412: ...10 18 MPC8240 Integrated Processor User s Manual Programming Guidelines ...
Page 454: ...12 14 MPC8240 Integrated Processor User s Manual Internal Arbitration ...
Page 466: ...13 12 MPC8240 Integrated Processor User s Manual Exception Latencies ...
Page 516: ...16 14 Watchpoint Trigger Applications ...
Page 538: ...B 16 MPC8240 Integrated Processor User s Manual Setting the Endian Mode of Operation ...
Page 546: ...C 8 MPC8240 Integrated Processor User s Manual ...
Page 640: ...INDEX Index 16 MPC8240 Integrated Processor User s Manual ...