Motorola MCPN750A, Installation And Use Manual

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Startup and Operation
2
L2 Cache
The MCPN750A SBC uses a backside L2 cache structure via the MPC750
processor chip. The MPC750 L2 cache is implemented with an onchip 2-
way set-associative tag memory and external direct-mapped synchronous
SRAMs for data storage. The external SRAMs are accessed through a
dedicated 72-bit wide (64 bits of data and 8 bits of parity) L2 cache port.
The MPC750 will support 256KB, 512KB or 1MB of L2 cache SRAMs.
The L2 cache can operate in copyback or writethru modes and supports
system cache coherency through snooping. Parity generation and checking
may be disabled by programming the MPC750 accordingly. Refer to the
MPC750 Data Sheet and the MCPN750A CompactPCI Single Board
Computer Programmer’s Reference Guide (MCPN750A/PG) for
additional information.
System Clock Generator
The system clocks for the processor, Raven/Falcon chipset (66 MHz) and
each of the onboard PCI devices (33 MHz) are generated by a 66 MHz
oscillator and distributed by the MPC949 clock buffer. Separate oscillators
are provided as follows: 14.31818 MHz for the PBC internal timer; 20
MHz for the ethernet MAC interface; 25 MHz for the ethernet PHY
device; 48 MHz for the USB interface; 1.843 MHz for the serial ports.
PPC Bus Arbitration
The arbitration control for the PPC bus is provided by a Programmable
Logic Device (PLD). There are only two potential PPC masters, Raven and
MPC750, with Raven having the highest priority. See the following
section titled “PCI Arbitration” for a description of arbitration control of
onboard PCI devices.
PCI Host Bridge
The Raven ASIC provides the bridge function between the PPC60X bus
and the onboard PCI Local Bus. Raven is a PCI 2.1 compliant 64-bit PCI
implementation for 32/64-bit data transfers. Dual Address Cycle is not